From ba0f28ad8b91365c7b6a2fe61ef41099aa33254b Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 1 Jan 2024 19:16:38 -0400 Subject: [PATCH] asahi: rm layered bit from shader key Just always use layered, like AGXV. This was a pointless bit of optimization that only affects render target spilling with neglible impact. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/lib/agx_nir_lower_tilebuffer.c | 17 +++++++---------- src/gallium/drivers/asahi/agx_state.c | 15 ++++++++------- src/gallium/drivers/asahi/agx_state.h | 1 - 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/src/asahi/lib/agx_nir_lower_tilebuffer.c b/src/asahi/lib/agx_nir_lower_tilebuffer.c index 64e5f0dfb13..e0b37a05d0d 100644 --- a/src/asahi/lib/agx_nir_lower_tilebuffer.c +++ b/src/asahi/lib/agx_nir_lower_tilebuffer.c @@ -193,11 +193,11 @@ store_memory(nir_builder *b, unsigned bindless_base, unsigned nr_samples, if (bindless) { nir_bindless_image_store(b, image, coords, sample, value, lod, - .image_dim = dim, .image_array = !!layer_id, + .image_dim = dim, .image_array = true, .format = format); } else { nir_image_store(b, image, coords, sample, value, lod, .image_dim = dim, - .image_array = !!layer_id, .format = format); + .image_array = true, .format = format); } if (nr_samples > 1) @@ -224,12 +224,12 @@ load_memory(nir_builder *b, unsigned bindless_base, unsigned nr_samples, nir_begin_invocation_interlock(b); if (bindless) { - return nir_bindless_image_load( - b, comps, bit_size, image, coords, sample, lod, .image_dim = dim, - .image_array = !!layer_id, .format = format); + return nir_bindless_image_load(b, comps, bit_size, image, coords, sample, + lod, .image_dim = dim, .image_array = true, + .format = format); } else { return nir_image_load(b, comps, bit_size, image, coords, sample, lod, - .image_dim = dim, .image_array = !!layer_id, + .image_dim = dim, .image_array = true, .format = format); } } @@ -246,10 +246,7 @@ agx_internal_layer_id(nir_builder *b) static nir_def * tib_layer_id(nir_builder *b, struct ctx *ctx) { - if (!ctx->tib->layered) { - /* If we're not layered, there's no explicit layer ID */ - return NULL; - } else if (ctx->layer_id_sr) { + if (ctx->layer_id_sr) { return agx_internal_layer_id(b); } else { /* Otherwise, the layer ID is loaded as a flat varying. */ diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c index e42f670f26b..d42a0be7c75 100644 --- a/src/gallium/drivers/asahi/agx_state.c +++ b/src/gallium/drivers/asahi/agx_state.c @@ -1234,7 +1234,7 @@ target_is_array(enum pipe_texture_target target) static void agx_batch_upload_pbe(struct agx_batch *batch, struct agx_pbe_packed *out, struct pipe_image_view *view, bool block_access, - bool arrays_as_2d) + bool arrays_as_2d, bool force_2d_array) { struct agx_resource *tex = agx_resource(view->resource); const struct util_format_description *desc = @@ -1252,7 +1252,8 @@ agx_batch_upload_pbe(struct agx_batch *batch, struct agx_pbe_packed *out, * * Likewise, cubes are accessed as arrays for consistency with NIR. */ - if ((arrays_as_2d && target_is_array(target)) || target_is_cube(target)) + if ((arrays_as_2d && target_is_array(target)) || target_is_cube(target) || + force_2d_array) target = PIPE_TEXTURE_2D_ARRAY; unsigned level = is_buffer ? 0 : view->u.tex.level; @@ -1780,7 +1781,7 @@ agx_compile_variant(struct agx_device *dev, struct pipe_context *pctx, struct asahi_fs_shader_key *key = &key_->fs; struct agx_tilebuffer_layout tib = agx_build_tilebuffer_layout( - key->rt_formats, key->nr_cbufs, key->nr_samples, key->layered); + key->rt_formats, key->nr_cbufs, key->nr_samples, true); if (dev->debug & AGX_DBG_SMALLTILE) tib.tile_size = (struct agx_tile_size){16, 16}; @@ -2320,7 +2321,6 @@ agx_update_fs(struct agx_batch *batch) ctx->stage[MESA_SHADER_VERTEX].shader->info.cull_distance_size, .clip_plane_enable = ctx->rast->base.clip_plane_enable, .nr_samples = nr_samples, - .layered = util_framebuffer_get_num_layers(&batch->key) > 1, /* Only lower sample mask if at least one sample is masked out */ .api_sample_mask = @@ -2517,9 +2517,10 @@ agx_upload_spilled_rt_descriptors(struct agx_texture_packed *out, struct agx_resource *rsrc = agx_resource(surf->texture); struct pipe_image_view view = image_view_for_surface(surf); struct pipe_sampler_view sampler_view = sampler_view_for_surface(surf); + sampler_view.target = PIPE_TEXTURE_2D_ARRAY; agx_pack_texture(texture, rsrc, surf->format, &sampler_view); - agx_batch_upload_pbe(batch, pbe, &view, false, true); + agx_batch_upload_pbe(batch, pbe, &view, false, false, true); } } @@ -2588,7 +2589,7 @@ agx_upload_textures(struct agx_batch *batch, struct agx_compiled_shader *cs, agx_pack_texture(texture, agx_resource(view->resource), view->format, &sampler_view); - agx_batch_upload_pbe(batch, pbe, view, false, false); + agx_batch_upload_pbe(batch, pbe, view, false, false, false); } if (stage == PIPE_SHADER_FRAGMENT && @@ -2878,7 +2879,7 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render) /* The tilebuffer is already in sRGB space if needed. Do not convert */ view.format = util_format_linear(view.format); - agx_batch_upload_pbe(batch, pbe.cpu, &view, true, true); + agx_batch_upload_pbe(batch, pbe.cpu, &view, true, true, false); agx_usc_pack(&b, TEXTURE, cfg) { cfg.start = rt; diff --git a/src/gallium/drivers/asahi/agx_state.h b/src/gallium/drivers/asahi/agx_state.h index fe30c55de16..59bc2a7876f 100644 --- a/src/gallium/drivers/asahi/agx_state.h +++ b/src/gallium/drivers/asahi/agx_state.h @@ -393,7 +393,6 @@ struct asahi_fs_shader_key { uint8_t cull_distance_size; uint8_t clip_plane_enable; uint8_t nr_samples; - bool layered; enum pipe_format rt_formats[PIPE_MAX_COLOR_BUFS]; };