diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index c4af1b88a08..bc3f72fec72 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -639,7 +639,7 @@ registers:
 	00000000	CP_CHICKEN_DBG: 0
 	00000001	CP_ADDR_MODE_CNTL: ADDR_64B
 	00000000	CP_DBG_ECO_CNTL: 0
-	00000003	CP_PROTECT_CNTL: 0x3
+	00000003	CP_PROTECT_CNTL: { ACCESS_FAULT_ON_VIOL_EN | ACCESS_PROT_EN }
 	01440600	CP_PROTECT[0].REG: { BASE_ADDR = 0x600 | MASK_LEN = 0x51 }
 	8008ae50	CP_PROTECT[0x1].REG: { BASE_ADDR = 0xae50 | MASK_LEN = 0x2 | READ }
 	804c9624	CP_PROTECT[0x2].REG: { BASE_ADDR = 0x9624 | MASK_LEN = 0x13 | READ }
diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
index b2f1fbeea6e..4dc602243f4 100644
--- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
@@ -854,7 +854,7 @@ registers:
 	00000000	CP_CHICKEN_DBG: 0
 	00000001	CP_ADDR_MODE_CNTL: ADDR_64B
 	00000000	CP_DBG_ECO_CNTL: 0
-	0000000b	CP_PROTECT_CNTL: 0xb
+	0000000b	CP_PROTECT_CNTL: { LAST_SPAN_INF_RANGE | ACCESS_FAULT_ON_VIOL_EN | ACCESS_PROT_EN }
 	13fc0000	CP_PROTECT[0].REG: { BASE_ADDR = 0 | MASK_LEN = 0x4ff }
 	00140501	CP_PROTECT[0x1].REG: { BASE_ADDR = 0x501 | MASK_LEN = 0x5 }
 	0bd0050b	CP_PROTECT[0x2].REG: { BASE_ADDR = 0x50b | MASK_LEN = 0x2f4 }
diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
index 94127b4bf79..33e142de999 100644
--- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log
+++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
@@ -1433,7 +1433,7 @@ registers:
 	00000000	CP_CHICKEN_DBG: 0
 	00000001	CP_ADDR_MODE_CNTL: ADDR_64B
 	00000000	CP_DBG_ECO_CNTL: 0
-	0000000b	CP_PROTECT_CNTL: 0xb
+	0000000b	CP_PROTECT_CNTL: { LAST_SPAN_INF_RANGE | ACCESS_FAULT_ON_VIOL_EN | ACCESS_PROT_EN }
 	13fc0000	CP_PROTECT[0].REG: { BASE_ADDR = 0 | MASK_LEN = 0x4ff }
 	00140501	CP_PROTECT[0x1].REG: { BASE_ADDR = 0x501 | MASK_LEN = 0x5 }
 	0bd0050b	CP_PROTECT[0x2].REG: { BASE_ADDR = 0x50b | MASK_LEN = 0x2f4 }
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 002c5ad7fbf..c390201bd37 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1083,7 +1083,11 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
 	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
-	<reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
+	<reg32 offset="0x084F" name="CP_PROTECT_CNTL">
+		<bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
+		<bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
+		<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
+	</reg32>
 
 	<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
 		<reg32 offset="0x0" name="REG" type="uint"/>