diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 7adec6f7381..e5a129bbb30 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -2912,6 +2912,57 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, } } +static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info, + struct gfx9_meta_equation *equation, + int blkSizeBias, unsigned blkStart, + nir_ssa_def *meta_pitch, nir_ssa_def *meta_slice_size, + nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, + nir_ssa_def *pipe_xor) +{ + nir_ssa_def *zero = nir_imm_int(b, 0); + nir_ssa_def *one = nir_imm_int(b, 1); + + assert(info->chip_class >= GFX10); + + unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width); + unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height); + unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + blkSizeBias; + + nir_ssa_def *coord[] = {x, y, z, 0}; + nir_ssa_def *address = zero; + + for (unsigned i = blkStart; i < blkSizeLog2 + 1; i++) { + nir_ssa_def *v = zero; + + for (unsigned c = 0; c < 4; c++) { + unsigned index = i * 4 + c - (blkStart * 4); + if (equation->u.gfx10_bits[index]) { + unsigned mask = equation->u.gfx10_bits[index]; + nir_ssa_def *bits = coord[c]; + + while (mask) + v = nir_ixor(b, v, nir_iand(b, nir_ushr_imm(b, bits, u_bit_scan(&mask)), one)); + } + } + + address = nir_ior(b, address, nir_ishl(b, v, nir_imm_int(b, i))); + } + + unsigned blkMask = (1 << blkSizeLog2) - 1; + unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) - 1; + unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config); + nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2); + nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2); + nir_ssa_def *pb = nir_ushr_imm(b, meta_pitch, meta_block_width_log2); + nir_ssa_def *blkIndex = nir_iadd(b, nir_imul(b, yb, pb), xb); + nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl(b, nir_iand_imm(b, pipe_xor, pipeMask), + nir_imm_int(b, m_pipeInterleaveLog2)), blkMask); + + return nir_iadd(b, nir_iadd(b, nir_imul(b, meta_slice_size, z), + nir_imul(b, blkIndex, nir_ishl(b, one, nir_imm_int(b, blkSizeLog2)))), + nir_ixor(b, nir_ushr(b, address, one), pipeXor)); +} + nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, unsigned bpe, struct gfx9_meta_equation *equation, nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height, @@ -2924,43 +2975,10 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info if (info->chip_class >= GFX10) { unsigned bpp_log2 = util_logbase2(bpe); - unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width); - unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height); - unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + bpp_log2 - 8; - nir_ssa_def *coord[] = {x, y, z, 0}; - nir_ssa_def *address = zero; - - for (unsigned i = 1; i < blkSizeLog2 + 1; i++) { - nir_ssa_def *v = zero; - - for (unsigned c = 0; c < 4; c++) { - unsigned index = i * 4 + c - 4; - if (equation->u.gfx10_bits[index]) { - unsigned mask = equation->u.gfx10_bits[index]; - nir_ssa_def *bits = coord[c]; - - while (mask) - v = nir_ixor(b, v, nir_iand(b, nir_ushr_imm(b, bits, u_bit_scan(&mask)), one)); - } - } - - address = nir_ior(b, address, nir_ishl(b, v, nir_imm_int(b, i))); - } - - unsigned blkMask = (1 << blkSizeLog2) - 1; - unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) - 1; - unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config); - nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2); - nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2); - nir_ssa_def *pb = nir_ushr_imm(b, dcc_pitch, meta_block_width_log2); - nir_ssa_def *blkIndex = nir_iadd(b, nir_imul(b, yb, pb), xb); - nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl(b, nir_iand_imm(b, pipe_xor, pipeMask), - nir_imm_int(b, m_pipeInterleaveLog2)), blkMask); - - return nir_iadd(b, nir_iadd(b, nir_imul(b, dcc_slice_size, z), - nir_imul(b, blkIndex, nir_ishl(b, one, nir_imm_int(b, blkSizeLog2)))), - nir_ixor(b, nir_ushr(b, address, one), pipeXor)); + return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1, + dcc_pitch, dcc_slice_size, + x, y, z, pipe_xor); } else { assert(info->chip_class == GFX9); @@ -3016,3 +3034,15 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info nir_ishl(b, pipeXor, nir_imm_int(b, m_pipeInterleaveLog2))); } } + +nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, + struct gfx9_meta_equation *equation, + nir_ssa_def *htile_pitch, + nir_ssa_def *htile_slice_size, + nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, + nir_ssa_def *pipe_xor) +{ + return gfx10_nir_meta_addr_from_coord(b, info, equation, -4, 2, + htile_pitch, htile_slice_size, + x, y, z, pipe_xor); +} diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 75ae433fb40..8674e9c9a72 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -466,6 +466,13 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info nir_ssa_def *dcc_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *sample, nir_ssa_def *pipe_xor); + +nir_ssa_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, + struct gfx9_meta_equation *equation, + nir_ssa_def *htile_pitch, + nir_ssa_def *htile_slice_size, + nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, + nir_ssa_def *pipe_xor); #endif #ifdef __cplusplus