diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 3b7fcc958e0..17b123a478f 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1754,7 +1754,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
        *
        * Clear accumulator register before end of thread.
        */
-      if (inst->eot && is_accum_used && devinfo->ver >= 12) {
+      if (inst->eot && is_accum_used &&
+          intel_needs_workaround(devinfo, 14010017096)) {
          brw_set_default_exec_size(p, BRW_EXECUTE_16);
          brw_set_default_mask_control(p, BRW_MASK_DISABLE);
          brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 8bead7fc84f..c6543e8bc28 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1081,7 +1081,7 @@ backend_instruction::writes_accumulator_implicitly(const struct intel_device_inf
             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
           (opcode == FS_OPCODE_LINTERP &&
            (!devinfo->has_pln || devinfo->ver <= 6)) ||
-          (eot && devinfo->ver >= 12); /* See Wa_14010017096. */
+          (eot && intel_needs_workaround(devinfo, 14010017096));
 }
 
 bool