diff --git a/src/intel/compiler/brw/brw_compiler.c b/src/intel/compiler/brw/brw_compiler.c
index 1b89bcbcbff..bd76081546b 100644
--- a/src/intel/compiler/brw/brw_compiler.c
+++ b/src/intel/compiler/brw/brw_compiler.c
@@ -199,6 +199,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
    nir_options->has_udot_4x8_sat = devinfo->ver >= 12;
    nir_options->has_sudot_4x8_sat = devinfo->ver >= 12;
 
+   nir_options->has_bitfield_select = devinfo->verx10 >= 125;
+
    nir_options->lower_int64_options = int64_options;
    nir_options->lower_doubles_options = fp64_options;
 
diff --git a/src/intel/compiler/brw/brw_from_nir.cpp b/src/intel/compiler/brw/brw_from_nir.cpp
index fd69d1eb0e1..ee543f4c010 100644
--- a/src/intel/compiler/brw/brw_from_nir.cpp
+++ b/src/intel/compiler/brw/brw_from_nir.cpp
@@ -31,6 +31,7 @@
 #include "dev/intel_debug.h"
 #include "util/u_math.h"
 #include "util/bitscan.h"
+#include "util/lut.h"
 #include "compiler/glsl_types.h"
 
 #include <optional>
@@ -1684,6 +1685,15 @@ brw_from_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
    case nir_op_bitfield_insert:
       UNREACHABLE("not reached: should have been lowered");
 
+   case nir_op_bitfield_select: {
+      /* The sources are rearranged because, due to the way opt_algebraic
+       * generates bitfield_select, op[0] will never be a constant. The only
+       * source of BFN that can't be immediate is src1.
+       */
+      bld.BFN(result, op[1], op[0], op[2], UTIL_LUT3((b & a) | (~b & c)));
+      break;
+   }
+
    /* With regards to implicit masking of the shift counts for 8- and 16-bit
     * types, the PRMs are **incorrect**. They falsely state that on Gen9+ only
     * the low bits of src1 matching the size of src0 (e.g., 4-bits for W or UW