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intel: factor out dispatch PS enabling logic

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
This commit is contained in:
Lionel Landwerlin 2022-12-05 19:26:40 +02:00
parent 71180004e0
commit b9403b1c47
7 changed files with 77 additions and 78 deletions
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8
src/gallium/drivers/crocus/crocus_state.c
View file

@ -6446,9 +6446,11 @@ crocus_upload_dirty_render_state(struct crocus_context *ice,
*/
ps.VectorMaskEnable = GFX_VER >= 8 && wm_prog_data->uses_vmask;
ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
brw_fs_get_dispatch_enables(&batch->screen->devinfo, wm_prog_data,
ice->state.framebuffer.samples,
&ps._8PixelDispatchEnable,
&ps._16PixelDispatchEnable,
&ps._32PixelDispatchEnable);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);

22
src/gallium/drivers/iris/iris_state.c
View file

@ -6224,23 +6224,11 @@ iris_upload_dirty_render_state(struct iris_context *ice,
uint32_t ps_state[GENX(3DSTATE_PS_length)] = {0};
_iris_pack_command(batch, GENX(3DSTATE_PS), ps_state, ps) {
ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
/* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
*
* "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
* SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
* mode."
*
* 16x MSAA only exists on Gfx9+, so we can skip this on Gfx8.
*/
if (GFX_VER >= 9 && cso_fb->samples == 16 &&
!wm_prog_data->persample_dispatch) {
assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable);
ps._32PixelDispatchEnable = false;
}
brw_fs_get_dispatch_enables(&screen->devinfo, wm_prog_data,
cso_fb->samples,
&ps._8PixelDispatchEnable,
&ps._16PixelDispatchEnable,
&ps._32PixelDispatchEnable);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);

24
src/intel/blorp/blorp_genX_exec.h
View file

@ -838,6 +838,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
*/
#if GFX_VER >= 8
const struct intel_device_info *devinfo = batch->blorp->compiler->devinfo;
blorp_emit(batch, GENX(3DSTATE_WM), wm);
@ -854,23 +855,11 @@ blorp_emit_ps_config(struct blorp_batch *batch,
ps.SamplerCount = 0;
if (prog_data) {
ps._8PixelDispatchEnable = prog_data->dispatch_8;
ps._16PixelDispatchEnable = prog_data->dispatch_16;
ps._32PixelDispatchEnable = prog_data->dispatch_32;
/* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
*
* "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
* Dispatch must not be enabled for PER_PIXEL dispatch mode."
*
* Since 16x MSAA is first introduced on SKL, we don't need to apply
* the workaround on any older hardware.
*/
if (GFX_VER >= 9 && !prog_data->persample_dispatch &&
params->num_samples == 16) {
assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable);
ps._32PixelDispatchEnable = false;
}
brw_fs_get_dispatch_enables(devinfo, prog_data,
params->num_samples,
&ps._8PixelDispatchEnable,
&ps._16PixelDispatchEnable,
&ps._32PixelDispatchEnable);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
@ -894,7 +883,6 @@ blorp_emit_ps_config(struct blorp_batch *batch,
*
* In Gfx8 the format is U8-2 whereas in Gfx9+ it is U9-1.
*/
const struct intel_device_info *devinfo = batch->blorp->compiler->devinfo;
ps.MaximumNumberofThreadsPerPSD =
devinfo->max_threads_per_psd - (GFX_VER == 8 ? 2 : 1);

51
src/intel/compiler/brw_compiler.h
View file

@ -984,6 +984,57 @@ brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
}
}
static inline void
brw_fs_get_dispatch_enables(const struct intel_device_info *devinfo,
const struct brw_wm_prog_data *prog_data,
unsigned rasterization_samples,
bool *enable_8,
bool *enable_16,
bool *enable_32)
{
assert(rasterization_samples != 0);
*enable_8 = prog_data->dispatch_8;
*enable_16 = prog_data->dispatch_16;
*enable_32 = prog_data->dispatch_32;
if (prog_data->persample_dispatch) {
/* Starting with SandyBridge (where we first get MSAA), the different
* pixel dispatch combinations are grouped into classifications A
* through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
* generations, the only configurations supporting persample dispatch
* are those in which only one dispatch width is enabled.
*
* The Gfx12 hardware spec has a similar dispatch grouping table, but
* the following conflicting restriction applies (from the page on
* "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
*
* "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
* enabled."
*/
if (*enable_32 || *enable_16)
*enable_8 = false;
if (devinfo->ver < 12 && *enable_32)
*enable_16 = false;
}
/* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
*
* "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
* SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
* mode."
*
* 16x MSAA only exists on Gfx9+, so we can skip this on Gfx8.
*/
if (devinfo->ver >= 9 && rasterization_samples == 16 &&
!prog_data->persample_dispatch) {
assert(*enable_8 || *enable_16);
*enable_32 = false;
}
assert(*enable_8 || *enable_16 || *enable_32);
}
#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
(wm_state)._16PixelDispatchEnable, \

20
src/intel/compiler/brw_fs.cpp
View file

@ -7607,26 +7607,6 @@ brw_compile_fs(const struct brw_compiler *compiler,
}
}
if (prog_data->persample_dispatch) {
/* Starting with SandyBridge (where we first get MSAA), the different
* pixel dispatch combinations are grouped into classifications A
* through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
* generations, the only configurations supporting persample dispatch
* are those in which only one dispatch width is enabled.
*
* The Gfx12 hardware spec has a similar dispatch grouping table, but
* the following conflicting restriction applies (from the page on
* "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
*
* "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
* enabled."
*/
if (simd32_cfg || simd16_cfg)
simd8_cfg = NULL;
if (simd32_cfg && devinfo->ver < 12)
simd16_cfg = NULL;
}
fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base,
v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT);

22
src/intel/vulkan/genX_pipeline.c
View file

@ -1488,23 +1488,11 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) {
ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
/* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
*
* "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
* Dispatch must not be enabled for PER_PIXEL dispatch mode."
*
* Since 16x MSAA is first introduced on SKL, we don't need to apply
* the workaround on any older hardware.
*/
if (!wm_prog_data->persample_dispatch &&
ms != NULL && ms->rasterization_samples == 16) {
assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable);
ps._32PixelDispatchEnable = false;
}
brw_fs_get_dispatch_enables(devinfo, wm_prog_data,
ms != NULL ? ms->rasterization_samples : 1,
&ps._8PixelDispatchEnable,
&ps._16PixelDispatchEnable,
&ps._32PixelDispatchEnable);
ps.KernelStartPointer0 = fs_bin->kernel.offset +
brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);

8
src/intel/vulkan_hasvk/genX_pipeline.c
View file

@ -1677,9 +1677,11 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
#endif
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) {
ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
brw_fs_get_dispatch_enables(devinfo, wm_prog_data,
ms != NULL ? ms->rasterization_samples : 1,
&ps._8PixelDispatchEnable,
&ps._16PixelDispatchEnable,
&ps._32PixelDispatchEnable);
ps.KernelStartPointer0 = fs_bin->kernel.offset +
brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);