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anv: fixup context initialization on DG2

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Fixing a typo :(

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 507a86e131 ("anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19922>
(cherry picked from commit f7d6c6e1ed)
This commit is contained in:
Lionel Landwerlin 2022-11-22 10:47:58 +02:00 • committed by Eric Engestrom
parent 17b00ea533
commit b92f135377
2 changed files with 4 additions and 2 deletions
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2
.pick_status.json
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@ -589,7 +589,7 @@
"description": "anv: fixup context initialization on DG2",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "507a86e131d648ecc85dc833f4821da6ac995cfe"
},

4
src/intel/vulkan/genX_state.c
View file

@ -181,7 +181,7 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
/* Emit STATE_BASE_ADDRESS on Gfx12+ because we set a default CPS_STATE and
* those are relative to STATE_BASE_ADDRESS::DynamicStateBaseAddress.
*/
#if GFX_VERx >= 12
#if GFX_VER >= 12
/* GEN:BUG:1607854226:
*
* Non-pipelined state has issues with not applying in MEDIA/GPGPU mode.
@ -233,7 +233,9 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
sba.BindlessSamplerStateBaseAddressModifyEnable = true;
sba.BindlessSamplerStateBufferSize = 0;
#if GFX_VERx10 >= 125
sba.L1CacheControl = L1CC_WB;
#endif
}
#endif