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tu: Rework emit_xs_config()

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Rework it to take all active/enabled shader stages in one shot, to
simplify things and drop the xs_configs table.

This lets us use the variant reg packers directly to better deal with
register changes across generations.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39029>
This commit is contained in:
Rob Clark 2025-12-18 13:00:31 -08:00 • committed by Marge Bot
parent dd489e2615
commit b91a614baf
4 changed files with 79 additions and 81 deletions
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16
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -875,16 +875,12 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
.cs_bindless = CHIP == A6XX ? 0x1f : 0xff, .cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
.gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,)); .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,));
tu_crb crb = cs->crb(2 * 5 + 2 * 11); with_crb (cs, 2 * 5 + 2 * 11) {
tu6_emit_xs_config<CHIP>(crb, MESA_SHADER_VERTEX, vs); tu6_emit_xs_config<CHIP>(crb, { .vs = vs, .fs = fs });
tu6_emit_xs_config<CHIP>(crb, MESA_SHADER_TESS_CTRL, NULL); struct tu_pvtmem_config pvtmem = {};
tu6_emit_xs_config<CHIP>(crb, MESA_SHADER_TESS_EVAL, NULL); tu6_emit_xs(crb, cs->device, MESA_SHADER_VERTEX, vs, &pvtmem, vs_iova);
tu6_emit_xs_config<CHIP>(crb, MESA_SHADER_GEOMETRY, NULL); tu6_emit_xs(crb, cs->device, MESA_SHADER_FRAGMENT, fs, &pvtmem, fs_iova);
tu6_emit_xs_config<CHIP>(crb, MESA_SHADER_FRAGMENT, fs); }
struct tu_pvtmem_config pvtmem = {};
tu6_emit_xs(crb, cs->device, MESA_SHADER_VERTEX, vs, &pvtmem, vs_iova);
tu6_emit_xs(crb, cs->device, MESA_SHADER_FRAGMENT, fs, &pvtmem, fs_iova);
crb.flush();
tu6_emit_xs_constants(cs, MESA_SHADER_VERTEX, vs, vs_iova); tu6_emit_xs_constants(cs, MESA_SHADER_VERTEX, vs, vs_iova);
tu6_emit_xs_constants(cs, MESA_SHADER_FRAGMENT, fs, fs_iova); tu6_emit_xs_constants(cs, MESA_SHADER_FRAGMENT, fs, fs_iova);

135
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -338,71 +338,72 @@ tu_push_consts_type(const struct tu_pipeline_layout *layout,
} }
} }
template <chip CHIP> static uint32_t
struct xs_config { sp_xs_config(const struct ir3_shader_variant *v)
uint16_t reg_sp_xs_config; {
uint16_t reg_hlsq_xs_ctrl; if (!v)
}; return 0;
template <chip CHIP> return A6XX_SP_VS_CONFIG_ENABLED |
static const xs_config<CHIP> xs_configs[] = { COND(v->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
[MESA_SHADER_VERTEX] = { COND(v->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
REG_A6XX_SP_VS_CONFIG, COND(v->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_UAV) |
CHIP == A6XX ? REG_A6XX_SP_VS_CONST_CONFIG : REG_A7XX_SP_VS_CONST_CONFIG, COND(v->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
}, A6XX_SP_VS_CONFIG_NUAV(ir3_shader_num_uavs(v)) |
[MESA_SHADER_TESS_CTRL] = { A6XX_SP_VS_CONFIG_NTEX(v->num_samp) |
REG_A6XX_SP_HS_CONFIG, A6XX_SP_VS_CONFIG_NSAMP(v->num_samp);
CHIP == A6XX ? REG_A6XX_SP_HS_CONST_CONFIG : REG_A7XX_SP_HS_CONST_CONFIG, }
},
[MESA_SHADER_TESS_EVAL] = { static bool
REG_A6XX_SP_DS_CONFIG, push_shared_consts(const struct ir3_shader_variant *v)
CHIP == A6XX ? REG_A6XX_SP_DS_CONST_CONFIG : REG_A7XX_SP_DS_CONST_CONFIG, {
}, return v && v->shader_options.push_consts_type == IR3_PUSH_CONSTS_SHARED_PREAMBLE;
[MESA_SHADER_GEOMETRY] = { }
REG_A6XX_SP_GS_CONFIG,
CHIP == A6XX ? REG_A6XX_SP_GS_CONST_CONFIG : REG_A7XX_SP_GS_CONST_CONFIG,
},
[MESA_SHADER_FRAGMENT] = {
REG_A6XX_SP_PS_CONFIG,
CHIP == A6XX ? REG_A6XX_SP_PS_CONST_CONFIG : REG_A7XX_SP_PS_CONST_CONFIG,
},
[MESA_SHADER_COMPUTE] = {
REG_A6XX_SP_CS_CONFIG,
CHIP == A6XX ? REG_A6XX_SP_CS_CONST_CONFIG : REG_A7XX_SP_CS_CONST_CONFIG,
},
};
template <chip CHIP> template <chip CHIP>
void void
tu6_emit_xs_config(struct tu_crb &crb, tu6_emit_xs_config(struct tu_crb &crb, struct tu_shader_stages stages)
mesa_shader_stage stage, /* xs->type, but xs may be NULL */
const struct ir3_shader_variant *xs)
{ {
const struct xs_config<CHIP> *cfg = &xs_configs<CHIP>[stage]; if (stages.cs) {
crb.add(SP_CS_CONST_CONFIG(CHIP,
.constlen = stages.cs->constlen,
.enabled = true,
.read_imm_shared_consts = push_shared_consts(stages.cs),
));
crb.add(A6XX_SP_CS_CONFIG(.dword = sp_xs_config(stages.cs)));
} else {
crb.add(SP_VS_CONST_CONFIG(CHIP,
.constlen = COND(stages.vs, stages.vs->constlen),
.enabled = stages.vs,
.read_imm_shared_consts = push_shared_consts(stages.vs),
));
crb.add(SP_HS_CONST_CONFIG(CHIP,
.constlen = COND(stages.hs, stages.hs->constlen),
.enabled = stages.hs,
.read_imm_shared_consts = push_shared_consts(stages.hs),
));
crb.add(SP_DS_CONST_CONFIG(CHIP,
.constlen = COND(stages.ds, stages.ds->constlen),
.enabled = stages.ds,
.read_imm_shared_consts = push_shared_consts(stages.ds),
));
crb.add(SP_GS_CONST_CONFIG(CHIP,
.constlen = COND(stages.gs, stages.gs->constlen),
.enabled = stages.gs,
.read_imm_shared_consts = push_shared_consts(stages.gs),
));
crb.add(SP_PS_CONST_CONFIG(CHIP,
.constlen = COND(stages.fs, stages.fs->constlen),
.enabled = stages.fs,
.read_imm_shared_consts = push_shared_consts(stages.fs),
));
if (!xs) { crb.add(A6XX_SP_VS_CONFIG(.dword = sp_xs_config(stages.vs)));
/* shader stage disabled */ crb.add(A6XX_SP_HS_CONFIG(.dword = sp_xs_config(stages.hs)));
crb.add(tu_reg_value { .reg = cfg->reg_sp_xs_config, .value = 0 }); crb.add(A6XX_SP_DS_CONFIG(.dword = sp_xs_config(stages.ds)));
crb.add(tu_reg_value { .reg = cfg->reg_hlsq_xs_ctrl, .value = 0 }); crb.add(A6XX_SP_GS_CONFIG(.dword = sp_xs_config(stages.gs)));
return; crb.add(A6XX_SP_PS_CONFIG(.dword = sp_xs_config(stages.fs)));
} }
crb.add(tu_reg_value {
.reg = cfg->reg_sp_xs_config,
.value = A6XX_SP_VS_CONFIG_ENABLED |
COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_UAV) |
COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp) });
crb.add(tu_reg_value {
.reg = cfg->reg_hlsq_xs_ctrl,
.value = A6XX_SP_VS_CONST_CONFIG_CONSTLEN(xs->constlen) |
A6XX_SP_VS_CONST_CONFIG_ENABLED |
COND(xs->shader_options.push_consts_type ==
IR3_PUSH_CONSTS_SHARED_PREAMBLE,
A7XX_SP_VS_CONST_CONFIG_READ_IMM_SHARED_CONSTS) });
} }
TU_GENX(tu6_emit_xs_config); TU_GENX(tu6_emit_xs_config);
@ -1266,11 +1267,14 @@ tu6_emit_program_config(struct tu_cs *cs,
.ds_state = true, .gs_state = true, .ds_state = true, .gs_state = true,
.fs_state = true, .gfx_uav = true, .fs_state = true, .gfx_uav = true,
.gfx_shared_const = shared_consts_enable)); .gfx_shared_const = shared_consts_enable));
for (size_t stage_idx = MESA_SHADER_VERTEX;
stage_idx <= MESA_SHADER_FRAGMENT; stage_idx++) { const struct ir3_shader_variant *vs = variants[MESA_SHADER_VERTEX];
mesa_shader_stage stage = (mesa_shader_stage) stage_idx; const struct ir3_shader_variant *hs = variants[MESA_SHADER_TESS_CTRL];
tu6_emit_xs_config<CHIP>(crb, stage, variants[stage]); const struct ir3_shader_variant *ds = variants[MESA_SHADER_TESS_EVAL];
} const struct ir3_shader_variant *gs = variants[MESA_SHADER_GEOMETRY];
const struct ir3_shader_variant *fs = variants[MESA_SHADER_FRAGMENT];
tu6_emit_xs_config<CHIP>(crb, { .vs = vs, .hs = hs, .ds = ds, .gs = gs, .fs = fs });
crb.flush(); crb.flush();
@ -1280,11 +1284,6 @@ tu6_emit_program_config(struct tu_cs *cs,
tu6_emit_dynamic_offset(cs, variants[stage], shaders[stage], prog); tu6_emit_dynamic_offset(cs, variants[stage], shaders[stage], prog);
} }
const struct ir3_shader_variant *vs = variants[MESA_SHADER_VERTEX];
const struct ir3_shader_variant *hs = variants[MESA_SHADER_TESS_CTRL];
const struct ir3_shader_variant *ds = variants[MESA_SHADER_TESS_EVAL];
const struct ir3_shader_variant *gs = variants[MESA_SHADER_GEOMETRY];
if (hs) { if (hs) {
tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER); tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER); tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);

7
src/freedreno/vulkan/tu_pipeline.h
View file

@ -301,11 +301,14 @@ struct tu_pvtmem_config {
bool per_wave; bool per_wave;
}; };
struct tu_shader_stages {
const struct ir3_shader_variant *vs, *hs, *ds, *gs, *fs, *cs;
};
template <chip CHIP> template <chip CHIP>
void void
tu6_emit_xs_config(struct tu_crb &crb, tu6_emit_xs_config(struct tu_crb &crb,
mesa_shader_stage stage, struct tu_shader_stages stages);
const struct ir3_shader_variant *xs);
template <chip CHIP> template <chip CHIP>
void void

2
src/freedreno/vulkan/tu_shader.cc
View file

@ -1781,7 +1781,7 @@ tu6_emit_cs_config(struct tu_cs *cs,
crb.add(SP_UPDATE_CNTL(CHIP, .cs_state = true, .cs_uav = true, crb.add(SP_UPDATE_CNTL(CHIP, .cs_state = true, .cs_uav = true,
.cs_shared_const = shared_consts_enable)); .cs_shared_const = shared_consts_enable));
tu6_emit_xs_config<CHIP>(crb, MESA_SHADER_COMPUTE, v); tu6_emit_xs_config<CHIP>(crb, { .cs = v });
tu6_emit_xs(crb, cs->device, MESA_SHADER_COMPUTE, v, pvtmem, binary_iova); tu6_emit_xs(crb, cs->device, MESA_SHADER_COMPUTE, v, pvtmem, binary_iova);
} }
tu6_emit_xs_constants(cs, MESA_SHADER_COMPUTE, v, binary_iova); tu6_emit_xs_constants(cs, MESA_SHADER_COMPUTE, v, binary_iova);