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radeonsi: remove slow code from si_msaa_resolve_blit_via_CB

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This is mainly a cleanup. It wasn't faster.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
This commit is contained in:
Marek Olšák 2024-04-14 18:54:59 -04:00 • committed by Marge Bot
parent b771d13557
commit b91220a825
3 changed files with 10 additions and 90 deletions
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63
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -1113,12 +1113,9 @@ bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_bli
struct si_texture *src = (struct si_texture *)info->src.resource;
struct si_texture *dst = (struct si_texture *)info->dst.resource;
ASSERTED struct si_texture *stmp;
unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
enum pipe_format format = info->src.format;
struct pipe_resource *tmp, templ;
struct pipe_blit_info blit;
/* Check basic requirements for hw resolve. */
if (!(info->src.resource->nr_samples > 1 && info->dst.resource->nr_samples <= 1 &&
@ -1150,33 +1147,30 @@ bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_bli
/* Check the remaining constraints. */
if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode ||
need_rgb_to_bgr) {
/* Changing the microtile mode is not possible with GFX10. */
if (sctx->gfx_level >= GFX10)
return false;
/* The next fast clear will switch to this mode to
* get direct hw resolve next time if the mode is
* different now.
*
* TODO-GFX10: This does not work in GFX10 because MSAA
* is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
* In some cases we could change the swizzle of the
* destination texture instead, but the more general
* solution is to implement compute shader resolve.
*/
if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode)
src->last_msaa_resolve_target_micro_mode = dst->surface.micro_tile_mode;
if (need_rgb_to_bgr)
src->swap_rgb_to_bgr_on_next_clear = true;
goto resolve_to_temp;
return false;
}
/* Resolving into a surface with DCC is unsupported. Since
* it's being overwritten anyway, clear it to uncompressed.
* This is still the fastest codepath even with this clear.
*/
if (vi_dcc_enabled(dst, info->dst.level)) {
struct si_clear_info clear_info;
if (!vi_dcc_get_clear_info(sctx, dst, info->dst.level, DCC_UNCOMPRESSED, &clear_info))
goto resolve_to_temp;
return false;
si_execute_clears(sctx, &clear_info, 1, SI_CLEAR_TYPE_DCC, info->render_condition_enable);
dst->dirty_level_mask &= ~(1 << info->dst.level);
@ -1187,50 +1181,7 @@ bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_bli
return true;
}
resolve_to_temp:
/* Shader-based resolve is VERY SLOW. Instead, resolve into
* a temporary texture and blit.
*/
memset(&templ, 0, sizeof(templ));
templ.target = PIPE_TEXTURE_2D;
templ.format = info->src.resource->format;
templ.width0 = info->src.resource->width0;
templ.height0 = info->src.resource->height0;
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING | SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE |
SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) |
SI_RESOURCE_FLAG_DISABLE_DCC | SI_RESOURCE_FLAG_DRIVER_INTERNAL;
/* The src and dst microtile modes must be the same. */
if (sctx->gfx_level <= GFX8 && src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
templ.bind = PIPE_BIND_SCANOUT;
else
templ.bind = 0;
tmp = ctx->screen->resource_create(ctx->screen, &templ);
if (!tmp)
return false;
stmp = (struct si_texture *)tmp;
/* Match the channel order of src. */
stmp->swap_rgb_to_bgr = src->swap_rgb_to_bgr;
assert(!stmp->surface.is_linear);
assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
/* resolve */
si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
/* blit */
blit = *info;
blit.src.resource = tmp;
blit.src.box.z = 0;
ctx->blit(ctx, &blit);
pipe_resource_reference(&tmp, NULL);
return true;
return false;
}
static void si_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)

14
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -100,23 +100,13 @@ struct ac_llvm_compiler;
#define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
#define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
#define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) /* Discard instead of evict. */
#define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
#define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
#define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
/* Set a micro tile mode: */
#define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
(((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
(((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
#define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
/* Discard instead of evict. */
#define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 13)
enum si_has_gs {
GS_OFF,

23
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -252,9 +252,6 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
/* Disable DCC? (it can't be disabled if modifiers are used) */
if (sscreen->info.gfx_level >= GFX8 && modifier == DRM_FORMAT_MOD_INVALID && !is_imported) {
/* Global options that disable DCC. */
if (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC)
flags |= RADEON_SURF_DISABLE_DCC;
if (ptex->nr_samples >= 2 && sscreen->debug_flags & DBG(NO_DCC_MSAA))
flags |= RADEON_SURF_DISABLE_DCC;
@ -341,23 +338,6 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
if (sscreen->debug_flags & DBG(NO_FMASK))
flags |= RADEON_SURF_NO_FMASK;
if (sscreen->info.gfx_level == GFX9 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) {
flags |= RADEON_SURF_FORCE_MICRO_TILE_MODE;
surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags);
}
if (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING) {
/* GFX11 shouldn't get here because the flag is only used by the CB MSAA resolving
* that GFX11 doesn't have.
*/
assert(sscreen->info.gfx_level <= GFX10_3);
flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
if (sscreen->info.gfx_level >= GFX10)
surface->u.gfx9.swizzle_mode = ADDR_SW_64KB_R_X;
}
if (ptex->flags & PIPE_RESOURCE_FLAG_SPARSE) {
flags |= RADEON_SURF_NO_FMASK |
RADEON_SURF_NO_HTILE |
@ -1279,7 +1259,6 @@ static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
bool tc_compatible_htile)
{
const struct util_format_description *desc = util_format_description(templ->format);
bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING;
bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
!(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);
@ -1300,7 +1279,7 @@ static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
/* Handle common candidates for the linear mode.
* Compressed textures and DB surfaces must always be tiled.
*/
if (!force_tiling && !is_depth_stencil && !util_format_is_compressed(templ->format)) {
if (!is_depth_stencil && !util_format_is_compressed(templ->format)) {
if (sscreen->debug_flags & DBG(NO_TILING) ||
(templ->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_TILING)))
return RADEON_SURF_MODE_LINEAR_ALIGNED;