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iris: Implement Gen12 workaround for non pipelined state
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
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1 changed files with 39 additions and 0 deletions
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@ -1014,12 +1014,24 @@ iris_init_compute_context(struct iris_batch *batch)
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{
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UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
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/* GEN:BUG:1607854226:
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*
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* Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
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*/
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#if GEN_GEN == 12
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emit_pipeline_select(batch, _3D);
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#else
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emit_pipeline_select(batch, GPGPU);
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#endif
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iris_emit_default_l3_config(batch, devinfo, true);
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init_state_base_address(batch);
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#if GEN_GEN == 12
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emit_pipeline_select(batch, GPGPU);
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#endif
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#if GEN_GEN == 9
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if (devinfo->is_geminilake)
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init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU);
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@ -5030,6 +5042,20 @@ iris_update_surface_base_address(struct iris_batch *batch,
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flush_before_state_base_change(batch);
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#if GEN_GEN == 12
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/* GEN:BUG:1607854226:
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*
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* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
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* mode by putting the pipeline temporarily in 3D mode..
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*/
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if (batch->name == IRIS_BATCH_COMPUTE) {
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iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
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sel.MaskBits = 3;
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sel.PipelineSelection = _3D;
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}
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}
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#endif
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iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
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sba.SurfaceStateBaseAddressModifyEnable = true;
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sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0);
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@ -5048,6 +5074,19 @@ iris_update_surface_base_address(struct iris_batch *batch,
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#endif
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}
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#if GEN_GEN == 12
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/* GEN:BUG:1607854226:
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*
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* Put the pipeline back into compute mode.
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*/
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if (batch->name == IRIS_BATCH_COMPUTE) {
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iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
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sel.MaskBits = 3;
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sel.PipelineSelection = GPGPU;
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}
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}
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#endif
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flush_after_state_base_change(batch);
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batch->last_surface_base_address = binder->bo->gtt_offset;
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