fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 15:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

iris: Implement Gen12 workaround for non pipelined state

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
This commit is contained in:
Lionel Landwerlin 2020-01-13 17:50:06 +02:00
parent 55b0aa436e
commit b8fbb39ab2
1 changed files with 39 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

39
src/gallium/drivers/iris/iris_state.c
View file

@ -1014,12 +1014,24 @@ iris_init_compute_context(struct iris_batch *batch)
{ {
UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo; UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
/* GEN:BUG:1607854226:
*
* Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
*/
#if GEN_GEN == 12
emit_pipeline_select(batch, _3D);
#else
emit_pipeline_select(batch, GPGPU); emit_pipeline_select(batch, GPGPU);
#endif
iris_emit_default_l3_config(batch, devinfo, true); iris_emit_default_l3_config(batch, devinfo, true);
init_state_base_address(batch); init_state_base_address(batch);
#if GEN_GEN == 12
emit_pipeline_select(batch, GPGPU);
#endif
#if GEN_GEN == 9 #if GEN_GEN == 9
if (devinfo->is_geminilake) if (devinfo->is_geminilake)
init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU); init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU);
@ -5030,6 +5042,20 @@ iris_update_surface_base_address(struct iris_batch *batch,
flush_before_state_base_change(batch); flush_before_state_base_change(batch);
#if GEN_GEN == 12
/* GEN:BUG:1607854226:
*
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode..
*/
if (batch->name == IRIS_BATCH_COMPUTE) {
iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
sel.MaskBits = 3;
sel.PipelineSelection = _3D;
}
}
#endif
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
sba.SurfaceStateBaseAddressModifyEnable = true; sba.SurfaceStateBaseAddressModifyEnable = true;
sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0); sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0);
@ -5048,6 +5074,19 @@ iris_update_surface_base_address(struct iris_batch *batch,
#endif #endif
} }
#if GEN_GEN == 12
/* GEN:BUG:1607854226:
*
* Put the pipeline back into compute mode.
*/
if (batch->name == IRIS_BATCH_COMPUTE) {
iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
sel.MaskBits = 3;
sel.PipelineSelection = GPGPU;
}
}
#endif
flush_after_state_base_change(batch); flush_after_state_base_change(batch);
batch->last_surface_base_address = binder->bo->gtt_offset; batch->last_surface_base_address = binder->bo->gtt_offset;