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i965/fs: Generate LOD sampler message from ir_lod.

Browse source 
v2: Support Ironlake as well.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2013-03-06 14:47:01 -08:00
parent 110ca8b1f3
commit b8aa9f7d3a
5 changed files with 20 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -711,6 +711,7 @@ enum opcode {
SHADER_OPCODE_TXS,
FS_OPCODE_TXB,
SHADER_OPCODE_TXF_MS,
SHADER_OPCODE_LOD,
SHADER_OPCODE_SHADER_TIME_ADD,
@ -896,6 +897,7 @@ enum brw_message_target {
#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
#define GEN5_SAMPLER_MESSAGE_LOD 9
#define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
#define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29

4
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -338,7 +338,8 @@ fs_inst::is_tex()
opcode == SHADER_OPCODE_TXF ||
opcode == SHADER_OPCODE_TXF_MS ||
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS);
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD);
}
bool
@ -732,6 +733,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
return 1;
case FS_OPCODE_FB_WRITE:
return 2;

4
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
View file

@ -404,6 +404,9 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_LOD:
msg_type = GEN5_SAMPLER_MESSAGE_LOD;
break;
default:
assert(!"not reached");
break;
@ -1276,6 +1279,7 @@ fs_generator::generate_code(exec_list *instructions)
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
generate_tex(inst, dst, src[0]);
break;
case FS_OPCODE_DDX:

6
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View file

@ -1084,6 +1084,9 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
mlen += reg_width;
inst = emit(SHADER_OPCODE_TXF_MS, dst);
break;
case ir_lod:
inst = emit(SHADER_OPCODE_LOD, dst);
break;
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
@ -1124,6 +1127,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
/* Set up the LOD info */
switch (ir->op) {
case ir_tex:
case ir_lod:
break;
case ir_txb:
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
@ -1237,6 +1241,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
@ -1388,6 +1393,7 @@ fs_visitor::visit(ir_texture *ir)
fs_reg lod, lod2, sample_index;
switch (ir->op) {
case ir_tex:
case ir_lod:
break;
case ir_txb:
ir->lod_info.bias->accept(this);

5
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -2127,6 +2127,7 @@ vec4_visitor::visit(ir_texture *ir)
lod_type = ir->lod_info.grad.dPdx->type;
break;
case ir_txb:
case ir_lod:
break;
}
@ -2150,6 +2151,10 @@ vec4_visitor::visit(ir_texture *ir)
break;
case ir_txb:
assert(!"TXB is not valid for vertex shaders.");
break;
case ir_lod:
assert(!"LOD is not valid for vertex shaders.");
break;
}
bool use_texture_offset = ir->offset != NULL && ir->op != ir_txf;