From b8865ad04643cd7e8faa8a863d81fedbc1e29231 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sun, 30 Oct 2022 23:29:53 +0100 Subject: [PATCH] radv: Fix compute scratch buffer emission. Copied wrong from radeonsi. The registers following the scratch buffer address are the shader rsrc1/rsrc2. Not the user SGPR0 containing the ring resource word 1. Fixes: 278e533ec9c ("radv: update scratch buffer registers on GFX11") Part-of: --- src/amd/vulkan/radv_device.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 02deaeb346c..f175a015b70 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -4443,13 +4443,12 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, radv_cs_add_buffer(device->ws, cs, compute_scratch_bo); if (info->gfx_level >= GFX11) { - radeon_set_sh_reg_seq(cs, R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4); + radeon_set_sh_reg_seq(cs, R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 2); radeon_emit(cs, scratch_va >> 8); radeon_emit(cs, scratch_va >> 40); - } else { - radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); } + radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); radeon_emit(cs, scratch_va); radeon_emit(cs, rsrc1);