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brw: Rename is_send_from_grf to is_send, replace other is_send() helper

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The is_send() helper is just a wrapper around inst->is_send_from_grf()
now, so we can combine the two.  Trim the name from is_send_from_grf()
to is_send(), as it's shorter, and also matches is_math().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34040>
This commit is contained in:
Kenneth Graunke 2025-01-31 02:47:53 -08:00 • committed by Marge Bot
parent e7d20bc86a
commit b848fa4595
7 changed files with 13 additions and 20 deletions
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2
src/intel/compiler/brw_analysis_performance.cpp
View file

@ -946,7 +946,7 @@ namespace {
execute_instruction(st, perf);
/* Mark any source dependencies. */
if (inst->is_send_from_grf()) {
if (inst->is_send()) {
for (unsigned i = 0; i < inst->sources; i++) {
if (inst->is_payload(i)) {
for (unsigned j = 0; j < regs_read(devinfo, inst, i); j++)

4
src/intel/compiler/brw_inst.cpp
View file

@ -168,7 +168,7 @@ brw_inst::resize_sources(uint8_t num_sources)
}
bool
brw_inst::is_send_from_grf() const
brw_inst::is_send() const
{
switch (opcode) {
case SHADER_OPCODE_SEND:
@ -259,7 +259,7 @@ brw_inst::is_payload(unsigned arg) const
bool
brw_inst::can_do_source_mods(const struct intel_device_info *devinfo) const
{
if (is_send_from_grf())
if (is_send())
return false;
/* From TGL PRM Vol 2a Pg. 1053 and Pg. 1069 MAD and MUL Instructions:

10
src/intel/compiler/brw_inst.h
View file

@ -64,7 +64,7 @@ public:
void resize_sources(uint8_t num_sources);
bool is_send_from_grf() const;
bool is_send() const;
bool is_payload(unsigned arg) const;
bool is_partial_write(unsigned grf_size = REG_SIZE) const;
unsigned components_read(unsigned i) const;
@ -330,12 +330,6 @@ get_exec_type_size(const brw_inst *inst)
return brw_type_size_bytes(get_exec_type(inst));
}
static inline bool
is_send(const brw_inst *inst)
{
return inst->is_send_from_grf();
}
/**
* Return whether the instruction isn't an ALU instruction and cannot be
* assumed to complete in-order.
@ -343,7 +337,7 @@ is_send(const brw_inst *inst)
static inline bool
is_unordered(const intel_device_info *devinfo, const brw_inst *inst)
{
return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) ||
return inst->is_send() || (devinfo->ver < 20 && inst->is_math()) ||
inst->opcode == BRW_OPCODE_DPAS ||
(devinfo->has_64bit_float_via_math_pipe &&
(get_exec_type(inst) == BRW_TYPE_DF ||

4
src/intel/compiler/brw_lower_regioning.cpp
View file

@ -316,7 +316,7 @@ namespace {
return true;
}
if (is_send(inst) || inst->is_control_source(i) ||
if (inst->is_send() || inst->is_control_source(i) ||
inst->opcode == BRW_OPCODE_DPAS) {
return false;
}
@ -360,7 +360,7 @@ namespace {
has_invalid_dst_region(const intel_device_info *devinfo,
const brw_inst *inst)
{
if (is_send(inst)) {
if (inst->is_send()) {
return false;
} else if (devinfo->has_bfloat16 && has_bfloat_operands(inst)) {

6
src/intel/compiler/brw_lower_scoreboard.cpp
View file

@ -75,7 +75,7 @@ namespace {
bool has_int_src = false, has_long_src = false;
const bool has_long_pipe = !devinfo->has_64bit_float_via_math_pipe;
if (is_send(inst))
if (inst->is_send())
return TGL_PIPE_NONE;
for (unsigned i = 0; i < inst->sources; i++) {
@ -992,7 +992,7 @@ namespace {
return find_unordered_dependency(deps, TGL_SBID_SET, exec_all);
else if (has_ordered && is_unordered(devinfo, inst))
return TGL_SBID_NULL;
else if (is_send(inst) && devinfo->ver >= 20)
else if (inst->is_send() && devinfo->ver >= 20)
return TGL_SBID_NULL;
else if (find_unordered_dependency(deps, TGL_SBID_DST, exec_all) &&
(!has_ordered || ordered_pipe == inferred_sync_pipe(devinfo, inst)))
@ -1030,7 +1030,7 @@ namespace {
return ordered_pipe == inferred_pipe &&
unordered_mode & (is_unordered(devinfo, inst) ? TGL_SBID_SET :
TGL_SBID_DST);
else if (is_send(inst))
else if (inst->is_send())
return unordered_mode & TGL_SBID_SET &&
(ordered_pipe == TGL_PIPE_FLOAT ||
ordered_pipe == TGL_PIPE_INT ||

5
src/intel/compiler/brw_opt_copy_propagation.cpp
View file

@ -759,8 +759,7 @@ try_copy_propagate(brw_shader &s, brw_inst *inst,
/* Reject cases that would violate register regioning restrictions. */
if ((entry->src.file == UNIFORM || !entry->src.is_contiguous()) &&
(inst->is_send_from_grf() ||
inst->uses_indirect_addressing())) {
(inst->is_send() || inst->uses_indirect_addressing())) {
return false;
}
@ -1655,7 +1654,7 @@ try_copy_propagate_def(brw_shader &s,
assert(inst->src[arg].stride == 0);
} else if ((val.file == UNIFORM || !val.is_contiguous()) &&
(inst->is_send_from_grf() || inst->uses_indirect_addressing())) {
(inst->is_send() || inst->uses_indirect_addressing())) {
return false;
}

2
src/intel/compiler/brw_workaround.cpp
View file

@ -228,7 +228,7 @@ brw_workaround_nomask_control_flow(brw_shader &s)
* safely omit the predication for.
*/
if (depth && inst->force_writemask_all &&
is_send(inst) && !inst->predicate &&
inst->is_send() && !inst->predicate &&
!inst->has_no_mask_send_params) {
/* We need to load the execution mask into the flag register by
* using a builder with channel group matching the whole shader