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anv/gen7: Add stall and flushes before switching pipelines

Browse source 
This is a port of 18c76551ee from OpenGL
to Vulkan.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Jordan Justen 2016-03-10 17:19:13 -08:00
parent c8ec65a1f5
commit b83785d86d
1 changed files with 24 additions and 0 deletions
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24
src/intel/vulkan/genX_cmd_buffer.c
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@ -780,6 +780,30 @@ flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer,
*/
if (pipeline == GPGPU)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS));
#elif GEN_GEN <= 7
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* Project: DEVSNB+
*
* Software must ensure all the write caches are flushed through a
* stalling PIPE_CONTROL command followed by another PIPE_CONTROL
* command to invalidate read only caches prior to programming
* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
.RenderTargetCacheFlushEnable = true,
.DepthCacheFlushEnable = true,
.DCFlushEnable = true,
.PostSyncOperation = NoWrite,
.CommandStreamerStallEnable = true);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
.TextureCacheInvalidationEnable = true,
.ConstantCacheInvalidationEnable = true,
.StateCacheInvalidationEnable = true,
.InstructionCacheInvalidateEnable = true,
.PostSyncOperation = NoWrite);
#endif
}