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radv: Invalidate L2 for TRANSFER_WRITE barriers

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CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write
through L2. Therefore, to make these writes visible to later accesses
we must invalidate L2 rather than just writing it back, to avoid the
possibility that stale data is read through L2.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
[Bas: patch is a backport for 17.0 of the cherry-pick below]
(cherry picked from commit bc5d587a80)
This commit is contained in:
Alex Smith 2017-03-30 21:03:58 +02:00 • committed by Emil Velikov
parent a6114f0c4e
commit b7d3c71d64
1 changed files with 2 additions and 1 deletions
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3
src/amd/vulkan/radv_cmd_buffer.c
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@ -2580,7 +2580,8 @@ void radv_CmdPipelineBarrier(
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
break;
case VK_ACCESS_TRANSFER_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_INV_GLOBAL_L2;
break;
default:
break;