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panfrost: Split command stream descriptor definitions per-gen
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
This commit is contained in:
Boris Brezillon
Marge Bot
parent
95b37fd21e
commit
b76420be1f
24 changed files with 3956 additions and 947 deletions
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@ -73,7 +73,7 @@ struct panfrost_zsa_state {
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struct panfrost_sampler_state {
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struct pipe_sampler_state base;
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struct mali_midgard_sampler_packed hw;
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struct mali_sampler_packed hw;
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};
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/* Misnomer: Sampler view corresponds to textures, not samplers */
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@ -81,7 +81,7 @@ struct panfrost_sampler_state {
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struct panfrost_sampler_view {
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struct pipe_sampler_view base;
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struct panfrost_pool_ref state;
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struct mali_bifrost_texture_packed bifrost_descriptor;
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struct mali_texture_packed bifrost_descriptor;
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mali_ptr texture_bo;
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uint64_t modifier;
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};
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@ -123,21 +123,26 @@ translate_tex_wrap(enum pipe_tex_wrap w, bool using_nearest)
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/* Bifrost doesn't support the GL_CLAMP wrap mode, so instead use
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* CLAMP_TO_EDGE and CLAMP_TO_BORDER. On Midgard, CLAMP is broken for
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* nearest filtering, so use CLAMP_TO_EDGE in that case. */
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bool supports_clamp = (PAN_ARCH <= 5);
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switch (w) {
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case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT;
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case PIPE_TEX_WRAP_CLAMP:
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return using_nearest ? MALI_WRAP_MODE_CLAMP_TO_EDGE :
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(supports_clamp ? MALI_WRAP_MODE_CLAMP :
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MALI_WRAP_MODE_CLAMP_TO_BORDER);
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#if PAN_ARCH <= 5
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MALI_WRAP_MODE_CLAMP;
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#else
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MALI_WRAP_MODE_CLAMP_TO_BORDER;
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#endif
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case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE;
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case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER;
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case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT;
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case PIPE_TEX_WRAP_MIRROR_CLAMP:
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return using_nearest ? MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE :
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(supports_clamp ? MALI_WRAP_MODE_MIRRORED_CLAMP :
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MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER);
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#if PAN_ARCH <= 5
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MALI_WRAP_MODE_MIRRORED_CLAMP;
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#else
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MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
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#endif
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case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE;
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case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
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default: unreachable("Invalid wrap");
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@ -279,7 +284,7 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_sha
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pan_pack(rts + i * pan_size(BLEND), BLEND, cfg) {
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cfg.enable = false;
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#if PAN_ARCH >= 6
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cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF;
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cfg.internal.mode = MALI_BLEND_MODE_OFF;
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#endif
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}
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@ -298,14 +303,14 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_sha
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cfg.round_to_fb_precision = !dithered;
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cfg.alpha_to_one = ctx->blend->base.alpha_to_one;
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#if PAN_ARCH >= 6
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cfg.bifrost.constant = pack_blend_constant(format, cons);
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cfg.constant = pack_blend_constant(format, cons);
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#else
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cfg.midgard.blend_shader = (blend_shaders[i] != 0);
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cfg.blend_shader = (blend_shaders[i] != 0);
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if (blend_shaders[i])
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cfg.midgard.shader_pc = blend_shaders[i];
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cfg.shader_pc = blend_shaders[i];
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else
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cfg.midgard.constant = cons;
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cfg.constant = cons;
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#endif
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}
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@ -333,17 +338,17 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_sha
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unsigned ret_offset = fs->info.bifrost.blend[i].return_offset;
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assert(!(ret_offset & 0x7));
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pan_pack(&packed->opaque[2], BIFROST_INTERNAL_BLEND, cfg) {
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cfg.mode = MALI_BIFROST_BLEND_MODE_SHADER;
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pan_pack(&packed->opaque[2], INTERNAL_BLEND, cfg) {
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cfg.mode = MALI_BLEND_MODE_SHADER;
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cfg.shader.pc = (u32) blend_shaders[i];
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cfg.shader.return_value = ret_offset ?
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fs->bin.gpu + ret_offset : 0;
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}
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} else {
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pan_pack(&packed->opaque[2], BIFROST_INTERNAL_BLEND, cfg) {
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pan_pack(&packed->opaque[2], INTERNAL_BLEND, cfg) {
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cfg.mode = info.opaque ?
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MALI_BIFROST_BLEND_MODE_OPAQUE :
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MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION;
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MALI_BLEND_MODE_OPAQUE :
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MALI_BLEND_MODE_FIXED_FUNCTION;
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/* If we want the conversion to work properly,
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* num_comps must be set to 4
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@ -378,15 +383,15 @@ pan_merge_empty_fs(struct mali_renderer_state_packed *rsd)
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pan_pack(&empty_rsd, RENDERER_STATE, cfg) {
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#if PAN_ARCH >= 6
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cfg.properties.bifrost.shader_modifies_coverage = true;
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cfg.properties.bifrost.allow_forward_pixel_to_kill = true;
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cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
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cfg.properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
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cfg.properties.shader_modifies_coverage = true;
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cfg.properties.allow_forward_pixel_to_kill = true;
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cfg.properties.allow_forward_pixel_to_be_killed = true;
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cfg.properties.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
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#else
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cfg.shader.shader = 0x1;
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cfg.properties.midgard.work_register_count = 1;
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cfg.properties.work_register_count = 1;
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cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
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cfg.properties.midgard.force_early_z = true;
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cfg.properties.force_early_z = true;
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#endif
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}
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@ -421,64 +426,64 @@ panfrost_prepare_fs_state(struct panfrost_context *ctx,
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uint64_t rt_written = (fs->info.outputs_written >> FRAG_RESULT_DATA0);
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bool blend_reads_dest = (so->load_dest_mask & rt_mask);
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cfg.properties.bifrost.allow_forward_pixel_to_kill =
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cfg.properties.allow_forward_pixel_to_kill =
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fs->info.fs.can_fpk &&
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!(rt_mask & ~rt_written) &&
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!alpha_to_coverage &&
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!blend_reads_dest;
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#else
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cfg.properties.midgard.force_early_z =
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cfg.properties.force_early_z =
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fs->info.fs.can_early_z && !alpha_to_coverage &&
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((enum mali_func) zsa->base.alpha_func == MALI_FUNC_ALWAYS);
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/* TODO: Reduce this limit? */
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if (has_blend_shader)
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cfg.properties.midgard.work_register_count = MAX2(fs->info.work_reg_count, 8);
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cfg.properties.work_register_count = MAX2(fs->info.work_reg_count, 8);
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else
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cfg.properties.midgard.work_register_count = fs->info.work_reg_count;
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cfg.properties.work_register_count = fs->info.work_reg_count;
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/* Hardware quirks around early-zs forcing without a
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* depth buffer. Note this breaks occlusion queries. */
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bool has_oq = ctx->occlusion_query && ctx->active_queries;
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bool force_ez_with_discard = !zsa->enabled && !has_oq;
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cfg.properties.midgard.shader_reads_tilebuffer =
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cfg.properties.shader_reads_tilebuffer =
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force_ez_with_discard && fs->info.fs.can_discard;
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cfg.properties.midgard.shader_contains_discard =
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cfg.properties.shader_contains_discard =
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!force_ez_with_discard && fs->info.fs.can_discard;
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#endif
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}
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#if PAN_ARCH == 4
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if (rt_count > 0) {
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cfg.multisample_misc.sfbd_load_destination = so->info[0].load_dest;
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cfg.multisample_misc.sfbd_blend_shader = (blend_shaders[0] != 0);
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cfg.stencil_mask_misc.sfbd_write_enable = !so->info[0].no_colour;
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cfg.stencil_mask_misc.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format);
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cfg.stencil_mask_misc.sfbd_dither_disable = !so->base.dither;
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cfg.stencil_mask_misc.sfbd_alpha_to_one = so->base.alpha_to_one;
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cfg.multisample_misc.load_destination = so->info[0].load_dest;
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cfg.multisample_misc.blend_shader = (blend_shaders[0] != 0);
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cfg.stencil_mask_misc.write_enable = !so->info[0].no_colour;
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cfg.stencil_mask_misc.srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format);
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cfg.stencil_mask_misc.dither_disable = !so->base.dither;
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cfg.stencil_mask_misc.alpha_to_one = so->base.alpha_to_one;
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if (blend_shaders[0]) {
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cfg.sfbd_blend_shader = blend_shaders[0];
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cfg.blend_shader = blend_shaders[0];
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} else {
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cfg.sfbd_blend_constant = pan_blend_get_constant(
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cfg.blend_constant = pan_blend_get_constant(
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so->info[0].constant_mask,
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ctx->blend_color.color);
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}
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} else {
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/* If there is no colour buffer, leaving fields default is
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* fine, except for blending which is nonnullable */
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cfg.sfbd_blend_equation.color_mask = 0xf;
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cfg.sfbd_blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
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cfg.sfbd_blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
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cfg.sfbd_blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
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cfg.sfbd_blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
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cfg.sfbd_blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
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cfg.sfbd_blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
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cfg.blend_equation.color_mask = 0xf;
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cfg.blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
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cfg.blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
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cfg.blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
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cfg.blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
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cfg.blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
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cfg.blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
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}
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#elif PAN_ARCH == 5
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/* Workaround */
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cfg.sfbd_blend_shader = panfrost_last_nonnull(blend_shaders, rt_count);
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cfg.legacy_blend_shader = panfrost_last_nonnull(blend_shaders, rt_count);
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#endif
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cfg.multisample_misc.sample_mask = msaa ? ctx->sample_mask : 0xFFFF;
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@ -921,7 +926,7 @@ panfrost_upload_rt_conversion_sysval(struct panfrost_batch *batch,
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uniform->u[0] =
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GENX(pan_blend_get_internal_desc)(dev, format, rt, size, false) >> 32;
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} else {
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pan_pack(&uniform->u[0], BIFROST_INTERNAL_CONVERSION, cfg)
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pan_pack(&uniform->u[0], INTERNAL_CONVERSION, cfg)
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cfg.memory_format = dev->formats[PIPE_FORMAT_NONE].hw;
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}
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}
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@ -1324,8 +1329,8 @@ panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
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void *tex = (PAN_ARCH >= 6) ? &so->bifrost_descriptor : payload.cpu;
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if (PAN_ARCH <= 5) {
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payload.cpu += pan_size(MIDGARD_TEXTURE);
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payload.gpu += pan_size(MIDGARD_TEXTURE);
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payload.cpu += pan_size(TEXTURE);
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payload.gpu += pan_size(TEXTURE);
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}
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GENX(panfrost_new_texture)(device, &iview, tex, &payload);
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@ -1356,9 +1361,9 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch,
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struct panfrost_ptr T =
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pan_pool_alloc_desc_array(&batch->pool.base,
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ctx->sampler_view_count[stage],
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BIFROST_TEXTURE);
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struct mali_bifrost_texture_packed *out =
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(struct mali_bifrost_texture_packed *) T.cpu;
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TEXTURE);
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struct mali_texture_packed *out =
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(struct mali_texture_packed *) T.cpu;
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for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
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struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
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@ -1400,14 +1405,11 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
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if (!ctx->sampler_count[stage])
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return 0;
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assert(pan_size(BIFROST_SAMPLER) == pan_size(MIDGARD_SAMPLER));
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assert(pan_alignment(BIFROST_SAMPLER) == pan_alignment(MIDGARD_SAMPLER));
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struct panfrost_ptr T =
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pan_pool_alloc_desc_array(&batch->pool.base,
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ctx->sampler_count[stage],
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MIDGARD_SAMPLER);
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struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu;
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SAMPLER);
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struct mali_sampler_packed *out = (struct mali_sampler_packed *) T.cpu;
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for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i)
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out[i] = ctx->samplers[stage][i]->hw;
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@ -2445,8 +2447,10 @@ pan_draw_mode(enum pipe_prim_type mode)
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DEFINE_CASE(TRIANGLE_STRIP);
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DEFINE_CASE(TRIANGLE_FAN);
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DEFINE_CASE(QUADS);
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DEFINE_CASE(QUAD_STRIP);
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DEFINE_CASE(POLYGON);
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#if PAN_ARCH <= 6
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DEFINE_CASE(QUAD_STRIP);
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#endif
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default:
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unreachable("Invalid draw mode");
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@ -2530,7 +2534,6 @@ panfrost_draw_emit_vertex(struct panfrost_batch *batch,
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pan_section_pack(job, COMPUTE_JOB, DRAW, cfg) {
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cfg.draw_descriptor_is_64b = true;
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cfg.texture_descriptor_is_64b = (PAN_ARCH <= 5);
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cfg.state = batch->rsd[PIPE_SHADER_VERTEX];
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cfg.attributes = attribs;
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cfg.attribute_buffers = attrib_bufs;
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@ -2539,8 +2542,6 @@ panfrost_draw_emit_vertex(struct panfrost_batch *batch,
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cfg.thread_storage = batch->tls.gpu;
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pan_emit_draw_descs(batch, &cfg, PIPE_SHADER_VERTEX);
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}
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pan_section_pack(job, COMPUTE_JOB, DRAW_PADDING, cfg);
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}
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static void
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@ -2723,14 +2724,12 @@ panfrost_draw_emit_tiler(struct panfrost_batch *batch,
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}
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pan_section_pack(job, TILER_JOB, PADDING, cfg);
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pan_section_pack(job, TILER_JOB, DRAW_PADDING, cfg);
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#endif
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section = pan_section_ptr(job, TILER_JOB, DRAW);
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pan_pack(section, DRAW, cfg) {
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cfg.four_components_per_vertex = true;
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cfg.draw_descriptor_is_64b = true;
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cfg.texture_descriptor_is_64b = (PAN_ARCH <= 5);
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cfg.front_face_ccw = rast->front_ccw;
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cfg.cull_front_face = rast->cull_face & PIPE_FACE_FRONT;
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cfg.cull_back_face = rast->cull_face & PIPE_FACE_BACK;
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@ -3160,7 +3159,6 @@ panfrost_launch_grid(struct pipe_context *pipe,
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pan_section_pack(t.cpu, COMPUTE_JOB, DRAW, cfg) {
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cfg.draw_descriptor_is_64b = true;
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cfg.texture_descriptor_is_64b = (PAN_ARCH <= 5);
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cfg.state = panfrost_emit_compute_shader_meta(batch, PIPE_SHADER_COMPUTE);
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cfg.attributes = panfrost_emit_image_attribs(batch, &cfg.attribute_buffers, PIPE_SHADER_COMPUTE);
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cfg.thread_storage = panfrost_emit_shared_memory(batch, info);
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@ -3172,8 +3170,6 @@ panfrost_launch_grid(struct pipe_context *pipe,
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PIPE_SHADER_COMPUTE);
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}
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pan_section_pack(t.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
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unsigned indirect_dep = 0;
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if (info->indirect) {
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struct pan_indirect_dispatch_info indirect = {
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@ -3543,10 +3539,10 @@ init_batch(struct panfrost_batch *batch)
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/* Reserve the framebuffer and local storage descriptors */
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batch->framebuffer =
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#if PAN_ARCH == 4
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pan_pool_alloc_desc(&batch->pool.base, SINGLE_TARGET_FRAMEBUFFER);
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pan_pool_alloc_desc(&batch->pool.base, FRAMEBUFFER);
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#else
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pan_pool_alloc_desc_aggregate(&batch->pool.base,
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PAN_DESC(MULTI_TARGET_FRAMEBUFFER),
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PAN_DESC(FRAMEBUFFER),
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PAN_DESC(ZS_CRC_EXTENSION),
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PAN_DESC_ARRAY(MAX2(batch->key.nr_cbufs, 1), RENDER_TARGET));
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@ -158,14 +158,14 @@ pandecode_validate_buffer(mali_ptr addr, size_t sz)
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static void
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pandecode_midgard_tiler_descriptor(
|
||||
const struct mali_midgard_tiler_packed *tp,
|
||||
const struct mali_midgard_tiler_weights_packed *wp)
|
||||
const struct mali_tiler_context_packed *tp,
|
||||
const struct mali_tiler_weights_packed *wp)
|
||||
{
|
||||
pan_unpack(tp, TILER_CONTEXT, t);
|
||||
DUMP_UNPACKED(TILER_CONTEXT, t, "Tiler:\n");
|
||||
|
||||
/* We've never seen weights used in practice, but they exist */
|
||||
pan_unpack(wp, MIDGARD_TILER_WEIGHTS, w);
|
||||
pan_unpack(wp, TILER_WEIGHTS, w);
|
||||
bool nonzero_weights = false;
|
||||
|
||||
nonzero_weights |= w.weight0 != 0x0;
|
||||
|
|
@ -178,7 +178,7 @@ pandecode_midgard_tiler_descriptor(
|
|||
nonzero_weights |= w.weight7 != 0x0;
|
||||
|
||||
if (nonzero_weights)
|
||||
DUMP_UNPACKED(MIDGARD_TILER_WEIGHTS, w, "Tiler Weights:\n");
|
||||
DUMP_UNPACKED(TILER_WEIGHTS, w, "Tiler Weights:\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -192,7 +192,7 @@ struct pandecode_fbd {
|
|||
bool has_extra;
|
||||
};
|
||||
|
||||
#if PAN_ARCH <= 5
|
||||
#if PAN_ARCH == 4
|
||||
static struct pandecode_fbd
|
||||
pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
|
||||
{
|
||||
|
|
@ -204,15 +204,15 @@ pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
|
|||
.rt_count = 1
|
||||
};
|
||||
|
||||
pandecode_log("Single-Target Framebuffer:\n");
|
||||
pandecode_log("Framebuffer:\n");
|
||||
pandecode_indent++;
|
||||
|
||||
DUMP_SECTION(SINGLE_TARGET_FRAMEBUFFER, LOCAL_STORAGE, s, "Local Storage:\n");
|
||||
pan_section_unpack(s, SINGLE_TARGET_FRAMEBUFFER, PARAMETERS, p);
|
||||
DUMP_UNPACKED(SINGLE_TARGET_FRAMEBUFFER_PARAMETERS, p, "Parameters:\n");
|
||||
DUMP_SECTION(FRAMEBUFFER, LOCAL_STORAGE, s, "Local Storage:\n");
|
||||
pan_section_unpack(s, FRAMEBUFFER, PARAMETERS, p);
|
||||
DUMP_UNPACKED(FRAMEBUFFER_PARAMETERS, p, "Parameters:\n");
|
||||
|
||||
const void *t = pan_section_ptr(s, SINGLE_TARGET_FRAMEBUFFER, TILER);
|
||||
const void *w = pan_section_ptr(s, SINGLE_TARGET_FRAMEBUFFER, TILER_WEIGHTS);
|
||||
const void *t = pan_section_ptr(s, FRAMEBUFFER, TILER);
|
||||
const void *w = pan_section_ptr(s, FRAMEBUFFER, TILER_WEIGHTS);
|
||||
|
||||
pandecode_midgard_tiler_descriptor(t, w);
|
||||
|
||||
|
|
@ -221,14 +221,15 @@ pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
|
|||
/* Dummy unpack of the padding section to make sure all words are 0.
|
||||
* No need to call print here since the section is supposed to be empty.
|
||||
*/
|
||||
pan_section_unpack(s, SINGLE_TARGET_FRAMEBUFFER, PADDING_1, padding1);
|
||||
pan_section_unpack(s, SINGLE_TARGET_FRAMEBUFFER, PADDING_2, padding2);
|
||||
pan_section_unpack(s, FRAMEBUFFER, PADDING_1, padding1);
|
||||
pan_section_unpack(s, FRAMEBUFFER, PADDING_2, padding2);
|
||||
pandecode_log("\n");
|
||||
|
||||
return info;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
static void
|
||||
pandecode_local_storage(uint64_t gpu_va, int job_no)
|
||||
{
|
||||
|
|
@ -239,7 +240,7 @@ pandecode_local_storage(uint64_t gpu_va, int job_no)
|
|||
|
||||
static void
|
||||
pandecode_render_target(uint64_t gpu_va, unsigned job_no, unsigned gpu_id,
|
||||
const struct MALI_MULTI_TARGET_FRAMEBUFFER_PARAMETERS *fb)
|
||||
const struct MALI_FRAMEBUFFER_PARAMETERS *fb)
|
||||
{
|
||||
pandecode_log("Color Render Targets:\n");
|
||||
pandecode_indent++;
|
||||
|
|
@ -255,12 +256,13 @@ pandecode_render_target(uint64_t gpu_va, unsigned job_no, unsigned gpu_id,
|
|||
pandecode_indent--;
|
||||
pandecode_log("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
static void
|
||||
pandecode_sample_locations(const void *fb, int job_no)
|
||||
{
|
||||
pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, params);
|
||||
pan_section_unpack(fb, FRAMEBUFFER, PARAMETERS, params);
|
||||
|
||||
struct pandecode_mapped_memory *smem =
|
||||
pandecode_find_mapped_gpu_mem_containing(params.sample_locations);
|
||||
|
|
@ -281,20 +283,21 @@ pandecode_dcd(const struct MALI_DRAW *p,
|
|||
int job_no, enum mali_job_type job_type,
|
||||
char *suffix, unsigned gpu_id);
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
static struct pandecode_fbd
|
||||
pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
|
||||
{
|
||||
struct pandecode_mapped_memory *mem = pandecode_find_mapped_gpu_mem_containing(gpu_va);
|
||||
const void *PANDECODE_PTR_VAR(fb, mem, (mali_ptr) gpu_va);
|
||||
pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, PARAMETERS, params);
|
||||
pan_section_unpack(fb, FRAMEBUFFER, PARAMETERS, params);
|
||||
|
||||
struct pandecode_fbd info;
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
pandecode_sample_locations(fb, job_no);
|
||||
|
||||
pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, bparams);
|
||||
unsigned dcd_size = pan_size(DRAW) + pan_size(DRAW_PADDING);
|
||||
pan_section_unpack(fb, FRAMEBUFFER, PARAMETERS, bparams);
|
||||
unsigned dcd_size = pan_size(DRAW);
|
||||
struct pandecode_mapped_memory *dcdmem =
|
||||
pandecode_find_mapped_gpu_mem_containing(bparams.frame_shader_dcds);
|
||||
|
||||
|
|
@ -324,27 +327,24 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_i
|
|||
pandecode_indent++;
|
||||
|
||||
#if PAN_ARCH <= 5
|
||||
DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, LOCAL_STORAGE, fb, "Local Storage:\n");
|
||||
DUMP_SECTION(FRAMEBUFFER, LOCAL_STORAGE, fb, "Local Storage:\n");
|
||||
#endif
|
||||
|
||||
info.width = params.width;
|
||||
info.height = params.height;
|
||||
info.rt_count = params.render_target_count;
|
||||
DUMP_UNPACKED(MULTI_TARGET_FRAMEBUFFER_PARAMETERS, params, "Parameters:\n");
|
||||
DUMP_UNPACKED(FRAMEBUFFER_PARAMETERS, params, "Parameters:\n");
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, BIFROST_TILER_POINTER, fb, "Tiler Pointer");
|
||||
pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PADDING, padding);
|
||||
#else
|
||||
const void *t = pan_section_ptr(fb, MULTI_TARGET_FRAMEBUFFER, TILER);
|
||||
const void *w = pan_section_ptr(fb, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS);
|
||||
#if PAN_ARCH <= 5
|
||||
const void *t = pan_section_ptr(fb, FRAMEBUFFER, TILER);
|
||||
const void *w = pan_section_ptr(fb, FRAMEBUFFER, TILER_WEIGHTS);
|
||||
pandecode_midgard_tiler_descriptor(t, w);
|
||||
#endif
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("\n");
|
||||
|
||||
gpu_va += pan_size(MULTI_TARGET_FRAMEBUFFER);
|
||||
gpu_va += pan_size(FRAMEBUFFER);
|
||||
|
||||
info.has_extra = params.has_zs_crc_extension;
|
||||
|
||||
|
|
@ -363,6 +363,7 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_i
|
|||
|
||||
return info;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void
|
||||
pandecode_attributes(const struct pandecode_mapped_memory *mem,
|
||||
|
|
@ -417,18 +418,18 @@ pandecode_bifrost_blend(void *descs, int job_no, int rt_no, mali_ptr frag_shader
|
|||
{
|
||||
pan_unpack(descs + (rt_no * pan_size(BLEND)), BLEND, b);
|
||||
DUMP_UNPACKED(BLEND, b, "Blend RT %d:\n", rt_no);
|
||||
if (b.bifrost.internal.mode != MALI_BIFROST_BLEND_MODE_SHADER)
|
||||
if (b.internal.mode != MALI_BLEND_MODE_SHADER)
|
||||
return 0;
|
||||
|
||||
return (frag_shader & 0xFFFFFFFF00000000ULL) | b.bifrost.internal.shader.pc;
|
||||
return (frag_shader & 0xFFFFFFFF00000000ULL) | b.internal.shader.pc;
|
||||
}
|
||||
#else
|
||||
#elif PAN_ARCH == 5
|
||||
static mali_ptr
|
||||
pandecode_midgard_blend_mrt(void *descs, int job_no, int rt_no)
|
||||
{
|
||||
pan_unpack(descs + (rt_no * pan_size(BLEND)), BLEND, b);
|
||||
DUMP_UNPACKED(BLEND, b, "Blend RT %d:\n", rt_no);
|
||||
return b.midgard.blend_shader ? (b.midgard.shader_pc & ~0xf) : 0;
|
||||
return b.blend_shader ? (b.shader_pc & ~0xf) : 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -795,21 +796,25 @@ pandecode_dcd(const struct MALI_DRAW *p,
|
|||
{
|
||||
struct pandecode_mapped_memory *attr_mem;
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
struct pandecode_fbd fbd_info = {
|
||||
/* Default for Bifrost */
|
||||
.rt_count = 1
|
||||
};
|
||||
#endif
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
pandecode_local_storage(p->thread_storage & ~1, job_no);
|
||||
#else
|
||||
if (job_type != MALI_JOB_TYPE_TILER)
|
||||
#elif PAN_ARCH == 5
|
||||
if (job_type != MALI_JOB_TYPE_TILER) {
|
||||
pandecode_local_storage(p->thread_storage & ~1, job_no);
|
||||
else if (p->fbd & MALI_FBD_TAG_IS_MFBD)
|
||||
} else {
|
||||
assert(p->fbd & MALI_FBD_TAG_IS_MFBD);
|
||||
fbd_info = pandecode_mfbd_bfr((u64) ((uintptr_t) p->fbd) & ~MALI_FBD_TAG_MASK,
|
||||
job_no, false, gpu_id);
|
||||
else
|
||||
fbd_info = pandecode_sfbd((u64) (uintptr_t) p->fbd, job_no, false, gpu_id);
|
||||
}
|
||||
#else
|
||||
pandecode_sfbd((u64) (uintptr_t) p->fbd, job_no, false, gpu_id);
|
||||
#endif
|
||||
|
||||
int varying_count = 0, attribute_count = 0, uniform_count = 0, uniform_buffer_count = 0;
|
||||
|
|
@ -843,14 +848,14 @@ pandecode_dcd(const struct MALI_DRAW *p,
|
|||
#if PAN_ARCH >= 6
|
||||
uniform_count = state.preload.uniform_count;
|
||||
#else
|
||||
uniform_count = state.properties.midgard.uniform_count;
|
||||
uniform_count = state.properties.uniform_count;
|
||||
#endif
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
DUMP_UNPACKED(PRELOAD, state.preload, "Preload:\n");
|
||||
#else
|
||||
mali_ptr shader = state.sfbd_blend_shader & ~0xF;
|
||||
if (state.multisample_misc.sfbd_blend_shader && shader)
|
||||
#elif PAN_ARCH == 4
|
||||
mali_ptr shader = state.blend_shader & ~0xF;
|
||||
if (state.multisample_misc.blend_shader && shader)
|
||||
pandecode_blend_shader_disassemble(shader, job_no, job_type, gpu_id);
|
||||
#endif
|
||||
pandecode_indent--;
|
||||
|
|
@ -859,6 +864,7 @@ pandecode_dcd(const struct MALI_DRAW *p,
|
|||
/* MRT blend fields are used whenever MFBD is used, with
|
||||
* per-RT descriptors */
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
if ((job_type == MALI_JOB_TYPE_TILER || job_type == MALI_JOB_TYPE_FRAGMENT) &&
|
||||
(PAN_ARCH >= 6 || p->thread_storage & MALI_FBD_TAG_IS_MFBD)) {
|
||||
void* blend_base = ((void *) cl) + pan_size(RENDERER_STATE);
|
||||
|
|
@ -877,6 +883,7 @@ pandecode_dcd(const struct MALI_DRAW *p,
|
|||
gpu_id);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
} else
|
||||
pandecode_msg("XXX: missing shader descriptor\n");
|
||||
|
||||
|
|
@ -992,33 +999,31 @@ pandecode_indexed_vertex_job(const struct MALI_JOB_HEADER *h,
|
|||
const struct pandecode_mapped_memory *mem,
|
||||
mali_ptr job, int job_no, unsigned gpu_id)
|
||||
{
|
||||
struct mali_bifrost_indexed_vertex_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
struct mali_indexed_vertex_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
|
||||
pandecode_log("Vertex:\n");
|
||||
pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, VERTEX_DRAW, vert_draw);
|
||||
pan_section_unpack(p, INDEXED_VERTEX_JOB, VERTEX_DRAW, vert_draw);
|
||||
pandecode_dcd(&vert_draw, job_no, h->type, "", gpu_id);
|
||||
DUMP_UNPACKED(DRAW, vert_draw, "Vertex Draw:\n");
|
||||
|
||||
pandecode_log("Fragment:\n");
|
||||
pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, FRAGMENT_DRAW, frag_draw);
|
||||
pan_section_unpack(p, INDEXED_VERTEX_JOB, FRAGMENT_DRAW, frag_draw);
|
||||
pandecode_dcd(&frag_draw, job_no, MALI_JOB_TYPE_FRAGMENT, "", gpu_id);
|
||||
DUMP_UNPACKED(DRAW, frag_draw, "Fragment Draw:\n");
|
||||
|
||||
pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, TILER, tiler_ptr);
|
||||
pan_section_unpack(p, INDEXED_VERTEX_JOB, TILER, tiler_ptr);
|
||||
pandecode_log("Tiler Job Payload:\n");
|
||||
pandecode_indent++;
|
||||
pandecode_bifrost_tiler(tiler_ptr.address, job_no);
|
||||
pandecode_indent--;
|
||||
|
||||
pandecode_invocation(pan_section_ptr(p, BIFROST_INDEXED_VERTEX_JOB, INVOCATION));
|
||||
pandecode_primitive(pan_section_ptr(p, BIFROST_INDEXED_VERTEX_JOB, PRIMITIVE));
|
||||
pandecode_invocation(pan_section_ptr(p, INDEXED_VERTEX_JOB, INVOCATION));
|
||||
pandecode_primitive(pan_section_ptr(p, INDEXED_VERTEX_JOB, PRIMITIVE));
|
||||
|
||||
/* TODO: gl_PointSize on Bifrost */
|
||||
pandecode_primitive_size(pan_section_ptr(p, BIFROST_INDEXED_VERTEX_JOB, PRIMITIVE_SIZE), true);
|
||||
pandecode_primitive_size(pan_section_ptr(p, INDEXED_VERTEX_JOB, PRIMITIVE_SIZE), true);
|
||||
|
||||
pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, PADDING, padding);
|
||||
pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, FRAGMENT_DRAW_PADDING, f_padding);
|
||||
pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, VERTEX_DRAW_PADDING, v_padding);
|
||||
pan_section_unpack(p, INDEXED_VERTEX_JOB, PADDING, padding);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -1026,7 +1031,7 @@ pandecode_tiler_job_bfr(const struct MALI_JOB_HEADER *h,
|
|||
const struct pandecode_mapped_memory *mem,
|
||||
mali_ptr job, int job_no, unsigned gpu_id)
|
||||
{
|
||||
struct mali_bifrost_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
struct mali_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
pan_section_unpack(p, TILER_JOB, DRAW, draw);
|
||||
pan_section_unpack(p, TILER_JOB, TILER, tiler_ptr);
|
||||
pandecode_dcd(&draw, job_no, h->type, "", gpu_id);
|
||||
|
|
@ -1051,7 +1056,7 @@ pandecode_tiler_job_mdg(const struct MALI_JOB_HEADER *h,
|
|||
const struct pandecode_mapped_memory *mem,
|
||||
mali_ptr job, int job_no, unsigned gpu_id)
|
||||
{
|
||||
struct mali_midgard_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
struct mali_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
pan_section_unpack(p, TILER_JOB, DRAW, draw);
|
||||
pandecode_dcd(&draw, job_no, h->type, "", gpu_id);
|
||||
|
||||
|
|
@ -1076,47 +1081,43 @@ pandecode_fragment_job(const struct pandecode_mapped_memory *mem,
|
|||
struct mali_fragment_job_packed *PANDECODE_PTR_VAR(p, mem, job);
|
||||
pan_section_unpack(p, FRAGMENT_JOB, PAYLOAD, s);
|
||||
|
||||
bool is_mfbd = s.framebuffer & MALI_FBD_TAG_IS_MFBD;
|
||||
|
||||
if (!is_mfbd && PAN_ARCH >= 6)
|
||||
pandecode_msg("XXX: Bifrost fragment must use MFBD\n");
|
||||
#if PAN_ARCH == 4
|
||||
pandecode_sfbd(s.framebuffer, job_no, true, gpu_id);
|
||||
#else
|
||||
assert(s.framebuffer & MALI_FBD_TAG_IS_MFBD);
|
||||
|
||||
struct pandecode_fbd info;
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
info = pandecode_mfbd_bfr(s.framebuffer & ~MALI_FBD_TAG_MASK, job_no,
|
||||
true, gpu_id);
|
||||
#else
|
||||
if (is_mfbd)
|
||||
info = pandecode_mfbd_bfr(s.framebuffer & ~MALI_FBD_TAG_MASK, job_no,
|
||||
true, gpu_id);
|
||||
else
|
||||
info = pandecode_sfbd(s.framebuffer & ~MALI_FBD_TAG_MASK, job_no,
|
||||
true, gpu_id);
|
||||
#endif
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
unsigned expected_tag = 0;
|
||||
|
||||
/* Compute the tag for the tagged pointer. This contains the type of
|
||||
* FBD (MFBD/SFBD), and in the case of an MFBD, information about which
|
||||
* additional structures follow the MFBD header (an extra payload or
|
||||
* not, as well as a count of render targets) */
|
||||
|
||||
unsigned expected_tag = is_mfbd ? MALI_FBD_TAG_IS_MFBD : 0;
|
||||
expected_tag = MALI_FBD_TAG_IS_MFBD;
|
||||
if (info.has_extra)
|
||||
expected_tag |= MALI_FBD_TAG_HAS_ZS_RT;
|
||||
|
||||
if (is_mfbd) {
|
||||
if (info.has_extra)
|
||||
expected_tag |= MALI_FBD_TAG_HAS_ZS_RT;
|
||||
|
||||
expected_tag |= (MALI_POSITIVE(info.rt_count) << 2);
|
||||
}
|
||||
expected_tag |= MALI_FBD_TAG_IS_MFBD | (MALI_POSITIVE(info.rt_count) << 2);
|
||||
#endif
|
||||
|
||||
DUMP_UNPACKED(FRAGMENT_JOB_PAYLOAD, s, "Fragment Job Payload:\n");
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
/* The FBD is a tagged pointer */
|
||||
|
||||
unsigned tag = (s.framebuffer & MALI_FBD_TAG_MASK);
|
||||
|
||||
if (tag != expected_tag)
|
||||
pandecode_msg("XXX: expected FBD tag %X but got %X\n", expected_tag, tag);
|
||||
#endif
|
||||
|
||||
pandecode_log("\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,38 +74,22 @@ pan_arch(unsigned gpu_id)
|
|||
|
||||
/* Base macro defined on the command line. */
|
||||
#ifndef PAN_ARCH
|
||||
/* This will be replaced by a minimal definition header as soon as the
|
||||
* per-gen transition is complete.
|
||||
*/
|
||||
# include "midgard_pack.h"
|
||||
# include "common_pack.h"
|
||||
#else
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
#define TILER_JOB BIFROST_TILER_JOB
|
||||
#define TEXTURE BIFROST_TEXTURE
|
||||
#define SAMPLER BIFROST_SAMPLER
|
||||
#define TILER_HEAP BIFROST_TILER_HEAP
|
||||
#define TILER_CONTEXT BIFROST_TILER
|
||||
#else
|
||||
#define TILER_JOB MIDGARD_TILER_JOB
|
||||
#define TEXTURE MIDGARD_TEXTURE
|
||||
#define SAMPLER MIDGARD_SAMPLER
|
||||
#define TILER_CONTEXT MIDGARD_TILER
|
||||
#endif
|
||||
|
||||
/* Suffixing macros */
|
||||
#if (PAN_ARCH == 4)
|
||||
# define GENX(X) X##_v4
|
||||
# include "midgard_pack.h"
|
||||
# include "v4_pack.h"
|
||||
#elif (PAN_ARCH == 5)
|
||||
# define GENX(X) X##_v5
|
||||
# include "midgard_pack.h"
|
||||
# include "v5_pack.h"
|
||||
#elif (PAN_ARCH == 6)
|
||||
# define GENX(X) X##_v6
|
||||
# include "midgard_pack.h"
|
||||
# include "v6_pack.h"
|
||||
#elif (PAN_ARCH == 7)
|
||||
# define GENX(X) X##_v7
|
||||
# include "midgard_pack.h"
|
||||
# include "v7_pack.h"
|
||||
#else
|
||||
# error "Need to add suffixing macro for this architecture"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -182,7 +182,17 @@ __gen_unpack_padded(const uint8_t *restrict cl, uint32_t start, uint32_t end)
|
|||
(packed1).opaque[i] |= (packed2).opaque[i]; \
|
||||
} while(0)
|
||||
|
||||
#define mali_pixel_format_print_v6(fp, format) \\
|
||||
/* From presentations, 16x16 tiles externally. Use shift for fast computation
|
||||
* of tile numbers. */
|
||||
|
||||
#define MALI_TILE_SHIFT 4
|
||||
#define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
|
||||
|
||||
"""
|
||||
|
||||
v6_format_printer = """
|
||||
|
||||
#define mali_pixel_format_print(fp, format) \\
|
||||
fprintf(fp, "%*sFormat (v6): %s%s%s %s%s%s%s\\n", indent, "", \\
|
||||
mali_format_as_str((enum mali_format)((format >> 12) & 0xFF)), \\
|
||||
(format & (1 << 20)) ? " sRGB" : "", \\
|
||||
|
|
@ -192,20 +202,17 @@ __gen_unpack_padded(const uint8_t *restrict cl, uint32_t start, uint32_t end)
|
|||
mali_channel_as_str((enum mali_channel)((format >> 6) & 0x7)), \\
|
||||
mali_channel_as_str((enum mali_channel)((format >> 9) & 0x7)));
|
||||
|
||||
#define mali_pixel_format_print_v7(fp, format) \\
|
||||
"""
|
||||
|
||||
v7_format_printer = """
|
||||
|
||||
#define mali_pixel_format_print(fp, format) \\
|
||||
fprintf(fp, "%*sFormat (v7): %s%s %s%s\\n", indent, "", \\
|
||||
mali_format_as_str((enum mali_format)((format >> 12) & 0xFF)), \\
|
||||
(format & (1 << 20)) ? " sRGB" : "", \\
|
||||
mali_rgb_component_order_as_str((enum mali_rgb_component_order)(format & ((1 << 12) - 1))), \\
|
||||
(format & (1 << 21)) ? " XXX BAD BIT" : "");
|
||||
|
||||
|
||||
/* From presentations, 16x16 tiles externally. Use shift for fast computation
|
||||
* of tile numbers. */
|
||||
|
||||
#define MALI_TILE_SHIFT 4
|
||||
#define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
|
||||
|
||||
"""
|
||||
|
||||
def to_alphanum(name):
|
||||
|
|
@ -654,8 +661,7 @@ class Group(object):
|
|||
elif field.type == "uint/float":
|
||||
print(' fprintf(fp, "%*s{}: 0x%X (%f)\\n", indent, "", {}, uif({}));'.format(name, val, val))
|
||||
elif field.type == "Pixel Format":
|
||||
print(' mali_pixel_format_print_v6(fp, {});'.format(val))
|
||||
print(' mali_pixel_format_print_v7(fp, {});'.format(val))
|
||||
print(' mali_pixel_format_print(fp, {});'.format(val))
|
||||
else:
|
||||
print(' fprintf(fp, "%*s{}: %u\\n", indent, "", {});'.format(name, val))
|
||||
|
||||
|
|
@ -683,6 +689,12 @@ class Parser(object):
|
|||
def start_element(self, name, attrs):
|
||||
if name == "panxml":
|
||||
print(pack_header)
|
||||
if "arch" in attrs:
|
||||
arch = int(attrs["arch"])
|
||||
if arch <= 6:
|
||||
print(v6_format_printer)
|
||||
else:
|
||||
print(v7_format_printer)
|
||||
elif name == "struct":
|
||||
name = attrs["name"]
|
||||
self.no_direct_packing = attrs.get("no-direct-packing", False)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
# SOFTWARE.
|
||||
|
||||
pan_packers = []
|
||||
foreach packer : ['common', 'midgard']
|
||||
foreach packer : ['common', 'v4', 'v5', 'v6', 'v7']
|
||||
pan_packers += custom_target(
|
||||
packer + '_pack.h',
|
||||
input : ['gen_pack.py', packer + '.xml'],
|
||||
|
|
|
|||
|
|
@ -23,7 +23,11 @@
|
|||
*/
|
||||
|
||||
#include "pan_blend.h"
|
||||
|
||||
#ifdef PAN_ARCH
|
||||
#include "pan_shader.h"
|
||||
#endif
|
||||
|
||||
#include "pan_texture.h"
|
||||
#include "panfrost/util/pan_lower_framebuffer.h"
|
||||
#include "util/format/u_format.h"
|
||||
|
|
@ -623,8 +627,8 @@ GENX(pan_blend_get_internal_desc)(const struct panfrost_device *dev,
|
|||
const struct util_format_description *desc = util_format_description(fmt);
|
||||
uint64_t res;
|
||||
|
||||
pan_pack(&res, BIFROST_INTERNAL_BLEND, cfg) {
|
||||
cfg.mode = MALI_BIFROST_BLEND_MODE_OPAQUE;
|
||||
pan_pack(&res, INTERNAL_BLEND, cfg) {
|
||||
cfg.mode = MALI_BLEND_MODE_OPAQUE;
|
||||
cfg.fixed_function.num_comps = desc->nr_channels;
|
||||
cfg.fixed_function.rt = rt;
|
||||
|
||||
|
|
@ -636,29 +640,29 @@ GENX(pan_blend_get_internal_desc)(const struct panfrost_device *dev,
|
|||
switch (T) {
|
||||
case nir_type_float16:
|
||||
cfg.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_F16;
|
||||
MALI_REGISTER_FILE_FORMAT_F16;
|
||||
break;
|
||||
case nir_type_float32:
|
||||
cfg.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
|
||||
MALI_REGISTER_FILE_FORMAT_F32;
|
||||
break;
|
||||
case nir_type_int8:
|
||||
case nir_type_int16:
|
||||
cfg.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_I16;
|
||||
MALI_REGISTER_FILE_FORMAT_I16;
|
||||
break;
|
||||
case nir_type_int32:
|
||||
cfg.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
|
||||
MALI_REGISTER_FILE_FORMAT_I32;
|
||||
break;
|
||||
case nir_type_uint8:
|
||||
case nir_type_uint16:
|
||||
cfg.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U16;
|
||||
MALI_REGISTER_FILE_FORMAT_U16;
|
||||
break;
|
||||
case nir_type_uint32:
|
||||
cfg.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
MALI_REGISTER_FILE_FORMAT_U32;
|
||||
break;
|
||||
default:
|
||||
unreachable("Invalid format");
|
||||
|
|
|
|||
|
|
@ -48,16 +48,16 @@
|
|||
* This is primarily designed as a fallback for preloads but could be extended
|
||||
* for other clears/blits if needed in the future. */
|
||||
|
||||
static enum mali_bifrost_register_file_format
|
||||
static enum mali_register_file_format
|
||||
blit_type_to_reg_fmt(nir_alu_type in)
|
||||
{
|
||||
switch (in) {
|
||||
case nir_type_float32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
|
||||
return MALI_REGISTER_FILE_FORMAT_F32;
|
||||
case nir_type_int32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
|
||||
return MALI_REGISTER_FILE_FORMAT_I32;
|
||||
case nir_type_uint32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
return MALI_REGISTER_FILE_FORMAT_U32;
|
||||
default:
|
||||
unreachable("Invalid blit type");
|
||||
}
|
||||
|
|
@ -126,7 +126,7 @@ pan_blitter_emit_blend(const struct panfrost_device *dev,
|
|||
if (!iview) {
|
||||
cfg.enable = false;
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF;
|
||||
cfg.internal.mode = MALI_BLEND_MODE_OFF;
|
||||
#endif
|
||||
continue;
|
||||
}
|
||||
|
|
@ -135,49 +135,42 @@ pan_blitter_emit_blend(const struct panfrost_device *dev,
|
|||
cfg.srgb = util_format_is_srgb(iview->format);
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.bifrost.internal.mode = blend_shader ?
|
||||
MALI_BIFROST_BLEND_MODE_SHADER :
|
||||
MALI_BIFROST_BLEND_MODE_OPAQUE;
|
||||
cfg.internal.mode = blend_shader ?
|
||||
MALI_BLEND_MODE_SHADER :
|
||||
MALI_BLEND_MODE_OPAQUE;
|
||||
#endif
|
||||
|
||||
if (!blend_shader) {
|
||||
cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.equation.color_mask = 0xf;
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
nir_alu_type type = blit_shader->key.surfaces[rt].type;
|
||||
|
||||
cfg.bifrost.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.bifrost.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.bifrost.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.bifrost.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.bifrost.equation.color_mask = 0xf;
|
||||
cfg.bifrost.internal.fixed_function.num_comps = 4;
|
||||
cfg.bifrost.internal.fixed_function.conversion.memory_format =
|
||||
cfg.internal.fixed_function.num_comps = 4;
|
||||
cfg.internal.fixed_function.conversion.memory_format =
|
||||
panfrost_format_to_bifrost_blend(dev, iview->format, false);
|
||||
cfg.bifrost.internal.fixed_function.conversion.register_format =
|
||||
cfg.internal.fixed_function.conversion.register_format =
|
||||
blit_type_to_reg_fmt(type);
|
||||
|
||||
cfg.bifrost.internal.fixed_function.rt = rt;
|
||||
#else
|
||||
cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.midgard.equation.color_mask = 0xf;
|
||||
cfg.internal.fixed_function.rt = rt;
|
||||
#endif
|
||||
} else {
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.bifrost.internal.shader.pc = blend_shader;
|
||||
cfg.internal.shader.pc = blend_shader;
|
||||
if (blit_shader->blend_ret_offsets[rt]) {
|
||||
cfg.bifrost.internal.shader.return_value =
|
||||
cfg.internal.shader.return_value =
|
||||
blit_shader->address +
|
||||
blit_shader->blend_ret_offsets[rt];
|
||||
}
|
||||
#else
|
||||
cfg.midgard.blend_shader = true;
|
||||
cfg.midgard.shader_pc = blend_shader;
|
||||
cfg.blend_shader = true;
|
||||
cfg.shader_pc = blend_shader;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -249,14 +242,14 @@ pan_blitter_emit_rsd(const struct panfrost_device *dev,
|
|||
|
||||
#if PAN_ARCH >= 6
|
||||
if (zs) {
|
||||
cfg.properties.bifrost.zs_update_operation =
|
||||
cfg.properties.zs_update_operation =
|
||||
MALI_PIXEL_KILL_FORCE_LATE;
|
||||
cfg.properties.bifrost.pixel_kill_operation =
|
||||
cfg.properties.pixel_kill_operation =
|
||||
MALI_PIXEL_KILL_FORCE_LATE;
|
||||
} else {
|
||||
cfg.properties.bifrost.zs_update_operation =
|
||||
cfg.properties.zs_update_operation =
|
||||
MALI_PIXEL_KILL_STRONG_EARLY;
|
||||
cfg.properties.bifrost.pixel_kill_operation =
|
||||
cfg.properties.pixel_kill_operation =
|
||||
MALI_PIXEL_KILL_FORCE_EARLY;
|
||||
}
|
||||
|
||||
|
|
@ -268,8 +261,8 @@ pan_blitter_emit_rsd(const struct panfrost_device *dev,
|
|||
* for frame shaders it can cause GPU timeouts, so only allow colour
|
||||
* blit shaders to be killed. */
|
||||
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_kill = !zs;
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_be_killed = (dev->arch >= 7) || !zs;
|
||||
cfg.properties.allow_forward_pixel_to_kill = !zs;
|
||||
cfg.properties.allow_forward_pixel_to_be_killed = (dev->arch >= 7) || !zs;
|
||||
|
||||
cfg.preload.fragment.coverage = true;
|
||||
cfg.preload.fragment.sample_mask_id = ms;
|
||||
|
|
@ -277,30 +270,32 @@ pan_blitter_emit_rsd(const struct panfrost_device *dev,
|
|||
mali_ptr blend_shader = blend_shaders ?
|
||||
panfrost_last_nonnull(blend_shaders, rt_count) : 0;
|
||||
|
||||
cfg.properties.midgard.work_register_count = 4;
|
||||
cfg.properties.midgard.force_early_z = !zs;
|
||||
cfg.properties.work_register_count = 4;
|
||||
cfg.properties.force_early_z = !zs;
|
||||
cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS;
|
||||
|
||||
/* Set even on v5 for erratum workaround */
|
||||
cfg.sfbd_blend_shader = blend_shader;
|
||||
#if PAN_ARCH == 4
|
||||
cfg.stencil_mask_misc.sfbd_write_enable = true;
|
||||
cfg.stencil_mask_misc.sfbd_dither_disable = true;
|
||||
cfg.multisample_misc.sfbd_blend_shader = !!blend_shader;
|
||||
cfg.sfbd_blend_shader = blend_shader;
|
||||
if (!cfg.multisample_misc.sfbd_blend_shader) {
|
||||
cfg.sfbd_blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.sfbd_blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.sfbd_blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.sfbd_blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.sfbd_blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.sfbd_blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.sfbd_blend_constant = 0;
|
||||
#if PAN_ARCH == 5
|
||||
cfg.legacy_blend_shader = blend_shader;
|
||||
#else
|
||||
cfg.blend_shader = blend_shader;
|
||||
cfg.stencil_mask_misc.write_enable = true;
|
||||
cfg.stencil_mask_misc.dither_disable = true;
|
||||
cfg.multisample_misc.blend_shader = !!blend_shader;
|
||||
cfg.blend_shader = blend_shader;
|
||||
if (!cfg.multisample_misc.blend_shader) {
|
||||
cfg.blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.blend_constant = 0;
|
||||
|
||||
if (rts && rts[0]) {
|
||||
cfg.stencil_mask_misc.sfbd_srgb =
|
||||
cfg.stencil_mask_misc.srgb =
|
||||
util_format_is_srgb(rts[0]->format);
|
||||
cfg.sfbd_blend_equation.color_mask = 0xf;
|
||||
cfg.blend_equation.color_mask = 0xf;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1007,7 +1002,6 @@ pan_preload_emit_dcd(struct pan_pool *pool,
|
|||
pan_preload_emit_textures(pool, fb, zs, &cfg);
|
||||
|
||||
cfg.samplers = pan_blitter_emit_sampler(pool, true);
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
/* Tiles updated by blit shaders are still considered
|
||||
|
|
@ -1034,7 +1028,6 @@ pan_blit_emit_dcd(struct pan_pool *pool,
|
|||
cfg.position = dst_coords;
|
||||
pan_blitter_emit_varying(pool, src_coords, &cfg);
|
||||
cfg.viewport = vpd;
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
cfg.textures = textures;
|
||||
cfg.samplers = samplers;
|
||||
}
|
||||
|
|
@ -1093,13 +1086,7 @@ pan_preload_fb_alloc_pre_post_dcds(struct pan_pool *desc_pool,
|
|||
return;
|
||||
|
||||
fb->bifrost.pre_post.dcds =
|
||||
pan_pool_alloc_desc_aggregate(desc_pool,
|
||||
PAN_DESC(DRAW),
|
||||
PAN_DESC(DRAW_PADDING),
|
||||
PAN_DESC(DRAW),
|
||||
PAN_DESC(DRAW_PADDING),
|
||||
PAN_DESC(DRAW),
|
||||
PAN_DESC(DRAW_PADDING));
|
||||
pan_pool_alloc_desc_array(desc_pool, 3, DRAW);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -1112,7 +1099,7 @@ pan_preload_emit_pre_frame_dcd(struct pan_pool *desc_pool,
|
|||
pan_preload_fb_alloc_pre_post_dcds(desc_pool, fb);
|
||||
assert(fb->bifrost.pre_post.dcds.cpu);
|
||||
void *dcd = fb->bifrost.pre_post.dcds.cpu +
|
||||
(dcd_idx * (pan_size(DRAW) + pan_size(DRAW_PADDING)));
|
||||
(dcd_idx * pan_size(DRAW));
|
||||
|
||||
int crc_rt = GENX(pan_select_crc_rt)(fb);
|
||||
|
||||
|
|
|
|||
|
|
@ -38,14 +38,14 @@ mod_to_block_fmt(uint64_t mod)
|
|||
{
|
||||
switch (mod) {
|
||||
case DRM_FORMAT_MOD_LINEAR:
|
||||
return PAN_ARCH >= 7 ?
|
||||
MALI_BLOCK_FORMAT_V7_LINEAR : MALI_BLOCK_FORMAT_LINEAR;
|
||||
return MALI_BLOCK_FORMAT_LINEAR;
|
||||
case DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED:
|
||||
return PAN_ARCH >= 7 ?
|
||||
MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED : MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
|
||||
return MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
|
||||
default:
|
||||
#if PAN_ARCH >= 5
|
||||
if (drm_is_afbc(mod))
|
||||
return PAN_ARCH >= 7 ? MALI_BLOCK_FORMAT_V7_AFBC : MALI_BLOCK_FORMAT_AFBC;
|
||||
return MALI_BLOCK_FORMAT_AFBC;
|
||||
#endif
|
||||
|
||||
unreachable("Unsupported modifer");
|
||||
}
|
||||
|
|
@ -164,11 +164,7 @@ pan_prepare_s(const struct pan_fb_info *fb,
|
|||
|
||||
unsigned level = s->first_level;
|
||||
|
||||
#if PAN_ARCH <= 6
|
||||
ext->s_msaa = mali_sampling_mode(s);
|
||||
#else
|
||||
ext->s_msaa_v7 = mali_sampling_mode(s);
|
||||
#endif
|
||||
|
||||
struct pan_surface surf;
|
||||
pan_iview_get_surface(s, 0, 0, 0, &surf);
|
||||
|
|
@ -180,13 +176,7 @@ pan_prepare_s(const struct pan_fb_info *fb,
|
|||
ext->s_writeback_surface_stride =
|
||||
(s->image->layout.nr_samples > 1) ?
|
||||
s->image->layout.slices[level].surface_stride : 0;
|
||||
|
||||
#if PAN_ARCH <= 6
|
||||
ext->s_block_format = mod_to_block_fmt(s->image->layout.modifier);
|
||||
#else
|
||||
ext->s_block_format_v7 = mod_to_block_fmt(s->image->layout.modifier);
|
||||
#endif
|
||||
|
||||
ext->s_write_format = translate_s_format(s->format);
|
||||
}
|
||||
|
||||
|
|
@ -201,11 +191,7 @@ pan_prepare_zs(const struct pan_fb_info *fb,
|
|||
|
||||
unsigned level = zs->first_level;
|
||||
|
||||
#if PAN_ARCH <= 6
|
||||
ext->zs_msaa = mali_sampling_mode(zs);
|
||||
#else
|
||||
ext->zs_msaa_v7 = mali_sampling_mode(zs);
|
||||
#endif
|
||||
|
||||
struct pan_surface surf;
|
||||
pan_iview_get_surface(zs, 0, 0, 0, &surf);
|
||||
|
|
@ -239,12 +225,7 @@ pan_prepare_zs(const struct pan_fb_info *fb,
|
|||
zs->image->layout.slices[level].surface_stride : 0;
|
||||
}
|
||||
|
||||
#if PAN_ARCH <= 6
|
||||
ext->zs_block_format = mod_to_block_fmt(zs->image->layout.modifier);
|
||||
#else
|
||||
ext->zs_block_format_v7 = mod_to_block_fmt(zs->image->layout.modifier);
|
||||
#endif
|
||||
|
||||
ext->zs_write_format = translate_zs_format(zs->format);
|
||||
if (ext->zs_write_format == MALI_ZS_FORMAT_D24S8)
|
||||
ext->s_writeback_base = ext->zs_writeback_base;
|
||||
|
|
@ -269,13 +250,13 @@ pan_prepare_crc(const struct pan_fb_info *fb, int rt_crc,
|
|||
|
||||
#if PAN_ARCH >= 7
|
||||
ext->crc_render_target = rt_crc;
|
||||
#endif
|
||||
|
||||
if (fb->rts[rt_crc].clear) {
|
||||
uint32_t clear_val = fb->rts[rt_crc].clear_value[0];
|
||||
ext->crc_clear_color = clear_val | 0xc000000000000000 |
|
||||
(((uint64_t)clear_val & 0xffff) << 32);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -338,26 +319,26 @@ pan_internal_cbuf_size(const struct pan_fb_info *fb,
|
|||
return total_size;
|
||||
}
|
||||
|
||||
static enum mali_mfbd_color_format
|
||||
static enum mali_color_format
|
||||
pan_mfbd_raw_format(unsigned bits)
|
||||
{
|
||||
switch (bits) {
|
||||
case 8: return MALI_MFBD_COLOR_FORMAT_RAW8;
|
||||
case 16: return MALI_MFBD_COLOR_FORMAT_RAW16;
|
||||
case 24: return MALI_MFBD_COLOR_FORMAT_RAW24;
|
||||
case 32: return MALI_MFBD_COLOR_FORMAT_RAW32;
|
||||
case 48: return MALI_MFBD_COLOR_FORMAT_RAW48;
|
||||
case 64: return MALI_MFBD_COLOR_FORMAT_RAW64;
|
||||
case 96: return MALI_MFBD_COLOR_FORMAT_RAW96;
|
||||
case 128: return MALI_MFBD_COLOR_FORMAT_RAW128;
|
||||
case 192: return MALI_MFBD_COLOR_FORMAT_RAW192;
|
||||
case 256: return MALI_MFBD_COLOR_FORMAT_RAW256;
|
||||
case 384: return MALI_MFBD_COLOR_FORMAT_RAW384;
|
||||
case 512: return MALI_MFBD_COLOR_FORMAT_RAW512;
|
||||
case 768: return MALI_MFBD_COLOR_FORMAT_RAW768;
|
||||
case 1024: return MALI_MFBD_COLOR_FORMAT_RAW1024;
|
||||
case 1536: return MALI_MFBD_COLOR_FORMAT_RAW1536;
|
||||
case 2048: return MALI_MFBD_COLOR_FORMAT_RAW2048;
|
||||
case 8: return MALI_COLOR_FORMAT_RAW8;
|
||||
case 16: return MALI_COLOR_FORMAT_RAW16;
|
||||
case 24: return MALI_COLOR_FORMAT_RAW24;
|
||||
case 32: return MALI_COLOR_FORMAT_RAW32;
|
||||
case 48: return MALI_COLOR_FORMAT_RAW48;
|
||||
case 64: return MALI_COLOR_FORMAT_RAW64;
|
||||
case 96: return MALI_COLOR_FORMAT_RAW96;
|
||||
case 128: return MALI_COLOR_FORMAT_RAW128;
|
||||
case 192: return MALI_COLOR_FORMAT_RAW192;
|
||||
case 256: return MALI_COLOR_FORMAT_RAW256;
|
||||
case 384: return MALI_COLOR_FORMAT_RAW384;
|
||||
case 512: return MALI_COLOR_FORMAT_RAW512;
|
||||
case 768: return MALI_COLOR_FORMAT_RAW768;
|
||||
case 1024: return MALI_COLOR_FORMAT_RAW1024;
|
||||
case 1536: return MALI_COLOR_FORMAT_RAW1536;
|
||||
case 2048: return MALI_COLOR_FORMAT_RAW2048;
|
||||
default: unreachable("invalid raw bpp");
|
||||
}
|
||||
}
|
||||
|
|
@ -425,7 +406,7 @@ pan_prepare_rt(const struct pan_fb_info *fb, unsigned idx,
|
|||
cfg->internal_format = MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8;
|
||||
cfg->internal_buffer_offset = cbuf_offset;
|
||||
#if PAN_ARCH >= 7
|
||||
cfg->bifrost_v7.writeback_block_format = MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED;
|
||||
cfg->writeback_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
|
||||
cfg->dithering_enable = true;
|
||||
#endif
|
||||
return;
|
||||
|
|
@ -450,10 +431,10 @@ pan_prepare_rt(const struct pan_fb_info *fb, unsigned idx,
|
|||
|
||||
pan_rt_init_format(rt, cfg);
|
||||
|
||||
#if PAN_ARCH <= 6
|
||||
cfg->midgard.writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
|
||||
#if PAN_ARCH <= 5
|
||||
cfg->writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
|
||||
#else
|
||||
cfg->bifrost_v7.writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
|
||||
cfg->writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
|
||||
#endif
|
||||
|
||||
struct pan_surface surf;
|
||||
|
|
@ -465,11 +446,11 @@ pan_prepare_rt(const struct pan_fb_info *fb, unsigned idx,
|
|||
#if PAN_ARCH >= 6
|
||||
cfg->afbc.row_stride = slice->afbc.row_stride /
|
||||
AFBC_HEADER_BYTES_PER_TILE;
|
||||
cfg->bifrost_afbc.afbc_wide_block_enable =
|
||||
cfg->afbc.afbc_wide_block_enable =
|
||||
panfrost_block_dim(rt->image->layout.modifier, true, 0) > 16;
|
||||
#else
|
||||
cfg->afbc.chunk_size = 9;
|
||||
cfg->midgard_afbc.sparse = true;
|
||||
cfg->afbc.sparse = true;
|
||||
cfg->afbc.body_size = slice->afbc.body_size;
|
||||
#endif
|
||||
|
||||
|
|
@ -525,7 +506,7 @@ pan_emit_midgard_tiler(const struct panfrost_device *dev,
|
|||
|
||||
assert(tiler_ctx->midgard.polygon_list->ptr.gpu);
|
||||
|
||||
pan_pack(out, MIDGARD_TILER, cfg) {
|
||||
pan_pack(out, TILER_CONTEXT, cfg) {
|
||||
unsigned header_size;
|
||||
|
||||
if (tiler_ctx->midgard.disable) {
|
||||
|
|
@ -579,21 +560,11 @@ pan_emit_mfbd(const struct panfrost_device *dev,
|
|||
{
|
||||
unsigned tags = MALI_FBD_TAG_IS_MFBD;
|
||||
void *fbd = out;
|
||||
void *rtd = out + pan_size(MULTI_TARGET_FRAMEBUFFER);
|
||||
void *rtd = out + pan_size(FRAMEBUFFER);
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, params) {
|
||||
params.sample_locations =
|
||||
panfrost_sample_positions(dev, pan_sample_pattern(fb->nr_samples));
|
||||
params.pre_frame_0 = fb->bifrost.pre_post.modes[0];
|
||||
params.pre_frame_1 = fb->bifrost.pre_post.modes[1];
|
||||
params.post_frame = fb->bifrost.pre_post.modes[2];
|
||||
params.frame_shader_dcds = fb->bifrost.pre_post.dcds.gpu;
|
||||
}
|
||||
#else
|
||||
#if PAN_ARCH <= 5
|
||||
GENX(pan_emit_tls)(tls,
|
||||
pan_section_ptr(fbd, MULTI_TARGET_FRAMEBUFFER,
|
||||
LOCAL_STORAGE));
|
||||
pan_section_ptr(fbd, FRAMEBUFFER, LOCAL_STORAGE));
|
||||
#endif
|
||||
|
||||
unsigned tile_size;
|
||||
|
|
@ -601,7 +572,16 @@ pan_emit_mfbd(const struct panfrost_device *dev,
|
|||
int crc_rt = GENX(pan_select_crc_rt)(fb);
|
||||
bool has_zs_crc_ext = pan_fbd_has_zs_crc_ext(fb);
|
||||
|
||||
pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, PARAMETERS, cfg) {
|
||||
pan_section_pack(fbd, FRAMEBUFFER, PARAMETERS, cfg) {
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.sample_locations =
|
||||
panfrost_sample_positions(dev, pan_sample_pattern(fb->nr_samples));
|
||||
cfg.pre_frame_0 = fb->bifrost.pre_post.modes[0];
|
||||
cfg.pre_frame_1 = fb->bifrost.pre_post.modes[1];
|
||||
cfg.post_frame = fb->bifrost.pre_post.modes[2];
|
||||
cfg.frame_shader_dcds = fb->bifrost.pre_post.dcds.gpu;
|
||||
cfg.tiler = tiler_ctx->bifrost;
|
||||
#endif
|
||||
cfg.width = fb->width;
|
||||
cfg.height = fb->height;
|
||||
cfg.bound_max_x = fb->width - 1;
|
||||
|
|
@ -644,21 +624,18 @@ pan_emit_mfbd(const struct panfrost_device *dev,
|
|||
}
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, BIFROST_TILER_POINTER, cfg) {
|
||||
cfg.address = tiler_ctx->bifrost;
|
||||
}
|
||||
pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, BIFROST_PADDING, padding);
|
||||
pan_section_pack(fbd, FRAMEBUFFER, PADDING, padding);
|
||||
#else
|
||||
pan_emit_midgard_tiler(dev, fb, tiler_ctx,
|
||||
pan_section_ptr(fbd, MULTI_TARGET_FRAMEBUFFER, TILER));
|
||||
pan_section_ptr(fbd, FRAMEBUFFER, TILER));
|
||||
|
||||
/* All weights set to 0, nothing to do here */
|
||||
pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS, w);
|
||||
pan_section_pack(fbd, FRAMEBUFFER, TILER_WEIGHTS, w);
|
||||
#endif
|
||||
|
||||
if (has_zs_crc_ext) {
|
||||
pan_emit_zs_crc_ext(fb, crc_rt,
|
||||
out + pan_size(MULTI_TARGET_FRAMEBUFFER));
|
||||
out + pan_size(FRAMEBUFFER));
|
||||
rtd += pan_size(ZS_CRC_EXTENSION);
|
||||
tags |= MALI_FBD_TAG_HAS_ZS_RT;
|
||||
}
|
||||
|
|
@ -689,11 +666,11 @@ pan_emit_sfbd_tiler(const struct panfrost_device *dev,
|
|||
void *fbd)
|
||||
{
|
||||
pan_emit_midgard_tiler(dev, fb, ctx,
|
||||
pan_section_ptr(fbd, SINGLE_TARGET_FRAMEBUFFER, TILER));
|
||||
pan_section_ptr(fbd, FRAMEBUFFER, TILER));
|
||||
|
||||
/* All weights set to 0, nothing to do here */
|
||||
pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, PADDING_1, padding);
|
||||
pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, TILER_WEIGHTS, w);
|
||||
pan_section_pack(fbd, FRAMEBUFFER, PADDING_1, padding);
|
||||
pan_section_pack(fbd, FRAMEBUFFER, TILER_WEIGHTS, w);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -704,9 +681,9 @@ pan_emit_sfbd(const struct panfrost_device *dev,
|
|||
void *fbd)
|
||||
{
|
||||
GENX(pan_emit_tls)(tls,
|
||||
pan_section_ptr(fbd, SINGLE_TARGET_FRAMEBUFFER,
|
||||
pan_section_ptr(fbd, FRAMEBUFFER,
|
||||
LOCAL_STORAGE));
|
||||
pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, PARAMETERS, cfg) {
|
||||
pan_section_pack(fbd, FRAMEBUFFER, PARAMETERS, cfg) {
|
||||
cfg.bound_max_x = fb->width - 1;
|
||||
cfg.bound_max_y = fb->height - 1;
|
||||
cfg.dithering_enable = true;
|
||||
|
|
@ -799,7 +776,7 @@ pan_emit_sfbd(const struct panfrost_device *dev,
|
|||
cfg.msaa = mali_sampling_mode(fb->rts[0].view);
|
||||
}
|
||||
pan_emit_sfbd_tiler(dev, fb, tiler_ctx, fbd);
|
||||
pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, PADDING_2, padding);
|
||||
pan_section_pack(fbd, FRAMEBUFFER, PADDING_2, padding);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -824,7 +801,7 @@ void
|
|||
GENX(pan_emit_tiler_heap)(const struct panfrost_device *dev,
|
||||
void *out)
|
||||
{
|
||||
pan_pack(out, BIFROST_TILER_HEAP, heap) {
|
||||
pan_pack(out, TILER_HEAP, heap) {
|
||||
heap.size = dev->tiler_heap->size;
|
||||
heap.base = dev->tiler_heap->ptr.gpu;
|
||||
heap.bottom = dev->tiler_heap->ptr.gpu;
|
||||
|
|
@ -842,7 +819,7 @@ GENX(pan_emit_tiler_ctx)(const struct panfrost_device *dev,
|
|||
unsigned max_levels = dev->tiler_features.max_levels;
|
||||
assert(max_levels >= 2);
|
||||
|
||||
pan_pack(out, BIFROST_TILER, tiler) {
|
||||
pan_pack(out, TILER_CONTEXT, tiler) {
|
||||
/* TODO: Select hierarchy mask more effectively */
|
||||
tiler.hierarchy_mask = (max_levels >= 8) ? 0xFF : 0x28;
|
||||
tiler.fb_width = fb_width;
|
||||
|
|
@ -870,10 +847,12 @@ GENX(pan_emit_fragment_job)(const struct pan_fb_info *fb,
|
|||
payload.bound_max_y = fb->extent.maxy >> MALI_TILE_SHIFT;
|
||||
payload.framebuffer = fbd;
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
if (fb->tile_map.base) {
|
||||
payload.has_tile_enable_map = true;
|
||||
payload.tile_enable_map = fb->tile_map.base;
|
||||
payload.tile_enable_map_row_stride = fb->tile_map.stride;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -233,6 +233,7 @@ panfrost_pack_work_groups_compute(
|
|||
}
|
||||
}
|
||||
|
||||
#if PAN_ARCH >= 5
|
||||
/* Format conversion */
|
||||
static inline enum mali_z_internal_format
|
||||
panfrost_get_z_internal_format(enum pipe_format fmt)
|
||||
|
|
@ -251,6 +252,7 @@ panfrost_get_z_internal_format(enum pipe_format fmt)
|
|||
unreachable("Unsupported depth/stencil format.");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PAN_ARCH */
|
||||
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
#define BFMT2(pipe, internal, writeback, srgb) \
|
||||
[PIPE_FORMAT_##pipe] = { \
|
||||
MALI_COLOR_BUFFER_INTERNAL_FORMAT_## internal, \
|
||||
MALI_MFBD_COLOR_FORMAT_## writeback, \
|
||||
MALI_COLOR_FORMAT_## writeback, \
|
||||
{ MALI_BLEND_PU_ ## internal | (srgb ? (1 << 20) : 0) | \
|
||||
PAN_V6_SWIZZLE(R, G, B, A), \
|
||||
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0) | \
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
#define BFMT2(pipe, internal, writeback, srgb) \
|
||||
[PIPE_FORMAT_##pipe] = { \
|
||||
MALI_COLOR_BUFFER_INTERNAL_FORMAT_## internal, \
|
||||
MALI_MFBD_COLOR_FORMAT_## writeback, \
|
||||
MALI_COLOR_FORMAT_## writeback, \
|
||||
{ MALI_BLEND_PU_ ## internal | (srgb ? (1 << 20) : 0), \
|
||||
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0) } \
|
||||
}
|
||||
|
|
@ -439,13 +439,13 @@ const struct panfrost_format GENX(panfrost_pipe_format)[PIPE_FORMAT_COUNT] = {
|
|||
FMT(A16_FLOAT, R16F, 000R, L, VTR_),
|
||||
|
||||
#else
|
||||
FMT(Z16_UNORM, RGB332_UNORM /* XXX: Deduplicate enum */, RGBA, L, _T_Z),
|
||||
FMT(Z16_UNORM, Z16_UNORM, RGBA, L, _T_Z),
|
||||
FMT(Z24_UNORM_S8_UINT, Z24X8_UNORM, RGBA, L, _T_Z),
|
||||
FMT(Z24X8_UNORM, Z24X8_UNORM, RGBA, L, _T_Z),
|
||||
FMT(Z32_FLOAT, R32F, RGBA, L, _T_Z),
|
||||
FMT(Z32_FLOAT_S8X24_UINT, Z32_X32, RGBA, L, _T_Z),
|
||||
FMT(X32_S8X24_UINT, X32_S8X24, GRBA, L, _T_Z),
|
||||
FMT(X24S8_UINT, TILEBUFFER_NATIVE /* XXX: Deduplicate enum */, GRBA, L, _T_Z),
|
||||
FMT(X32_S8X24_UINT, X32_S8X24, GRBA, L, _T__),
|
||||
FMT(X24S8_UINT, X24S8, GRBA, L, _T_Z),
|
||||
FMT(S8_UINT, S8, GRBA, L, _T__),
|
||||
|
||||
FMT(A8_UNORM, A8_UNORM, 000A, L, VTR_),
|
||||
|
|
|
|||
|
|
@ -141,15 +141,12 @@ GENX(pan_indirect_dispatch_emit)(struct pan_pool *pool,
|
|||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW, cfg) {
|
||||
cfg.draw_descriptor_is_64b = true;
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
cfg.state = get_rsd(dev);
|
||||
cfg.thread_storage = get_tls(pool->dev);
|
||||
cfg.uniform_buffers = get_ubos(pool, &inputs);
|
||||
cfg.push_uniforms = get_push_uniforms(pool, &inputs);
|
||||
}
|
||||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
|
||||
|
||||
return panfrost_add_job(pool, scoreboard, MALI_JOB_TYPE_COMPUTE,
|
||||
false, true, 0, 0, &job, false);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1277,15 +1277,12 @@ panfrost_emit_index_min_max_search(struct pan_pool *pool,
|
|||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW, cfg) {
|
||||
cfg.draw_descriptor_is_64b = true;
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
cfg.state = rsd;
|
||||
cfg.thread_storage = get_tls(pool->dev);
|
||||
cfg.uniform_buffers = ubos;
|
||||
cfg.push_uniforms = get_push_uniforms(pool, shader, inputs);
|
||||
}
|
||||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
|
||||
|
||||
return panfrost_add_job(pool, scoreboard, MALI_JOB_TYPE_COMPUTE,
|
||||
false, false, 0, 0, &job, false);
|
||||
}
|
||||
|
|
@ -1369,15 +1366,12 @@ GENX(panfrost_emit_indirect_draw)(struct pan_pool *pool,
|
|||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW, cfg) {
|
||||
cfg.draw_descriptor_is_64b = true;
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
cfg.state = rsd;
|
||||
cfg.thread_storage = get_tls(pool->dev);
|
||||
cfg.uniform_buffers = ubos;
|
||||
cfg.push_uniforms = get_push_uniforms(pool, shader, &inputs);
|
||||
}
|
||||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
|
||||
|
||||
unsigned global_dep = draw_info->last_indirect_draw;
|
||||
unsigned local_dep =
|
||||
panfrost_emit_index_min_max_search(pool, scoreboard, draw_info,
|
||||
|
|
|
|||
|
|
@ -151,24 +151,24 @@ collect_varyings(nir_shader *s, nir_variable_mode varying_mode,
|
|||
}
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
static enum mali_bifrost_register_file_format
|
||||
static enum mali_register_file_format
|
||||
bifrost_blend_type_from_nir(nir_alu_type nir_type)
|
||||
{
|
||||
switch(nir_type) {
|
||||
case 0: /* Render target not in use */
|
||||
return 0;
|
||||
case nir_type_float16:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_F16;
|
||||
return MALI_REGISTER_FILE_FORMAT_F16;
|
||||
case nir_type_float32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
|
||||
return MALI_REGISTER_FILE_FORMAT_F32;
|
||||
case nir_type_int32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
|
||||
return MALI_REGISTER_FILE_FORMAT_I32;
|
||||
case nir_type_uint32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
return MALI_REGISTER_FILE_FORMAT_U32;
|
||||
case nir_type_int16:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_I16;
|
||||
return MALI_REGISTER_FILE_FORMAT_I16;
|
||||
case nir_type_uint16:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_U16;
|
||||
return MALI_REGISTER_FILE_FORMAT_U16;
|
||||
default:
|
||||
unreachable("Unsupported blend shader type for NIR alu type");
|
||||
return 0;
|
||||
|
|
@ -191,7 +191,7 @@ GENX(pan_shader_compile)(nir_shader *s,
|
|||
enum pipe_format fmt = inputs->rt_formats[i];
|
||||
unsigned wb_fmt = panfrost_blendable_formats_v6[fmt].writeback;
|
||||
|
||||
if (wb_fmt <= MALI_MFBD_COLOR_FORMAT_RAW2048)
|
||||
if (wb_fmt < MALI_COLOR_FORMAT_R8)
|
||||
inputs->raw_fmt_mask |= BITFIELD_BIT(i);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -50,20 +50,20 @@ pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
|
|||
{
|
||||
assert((info->push.count & 3) == 0);
|
||||
|
||||
rsd->properties.midgard.uniform_count = info->push.count / 4;
|
||||
rsd->properties.midgard.shader_has_side_effects = info->writes_global;
|
||||
rsd->properties.midgard.fp_mode = MALI_FP_MODE_GL_INF_NAN_ALLOWED;
|
||||
rsd->properties.uniform_count = info->push.count / 4;
|
||||
rsd->properties.shader_has_side_effects = info->writes_global;
|
||||
rsd->properties.fp_mode = MALI_FP_MODE_GL_INF_NAN_ALLOWED;
|
||||
|
||||
/* For fragment shaders, work register count, early-z, reads at draw-time */
|
||||
|
||||
if (info->stage != MESA_SHADER_FRAGMENT) {
|
||||
rsd->properties.midgard.work_register_count = info->work_reg_count;
|
||||
rsd->properties.work_register_count = info->work_reg_count;
|
||||
} else {
|
||||
rsd->properties.midgard.shader_reads_tilebuffer =
|
||||
rsd->properties.shader_reads_tilebuffer =
|
||||
info->fs.outputs_read;
|
||||
|
||||
/* However, forcing early-z in the shader overrides draw-time */
|
||||
rsd->properties.midgard.force_early_z =
|
||||
rsd->properties.force_early_z =
|
||||
info->fs.early_fragment_tests;
|
||||
}
|
||||
}
|
||||
|
|
@ -84,8 +84,8 @@ pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
|
|||
* */
|
||||
|
||||
#define SET_PIXEL_KILL(kill, update) do { \
|
||||
rsd->properties.bifrost.pixel_kill_operation = MALI_PIXEL_KILL_## kill; \
|
||||
rsd->properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_## update; \
|
||||
rsd->properties.pixel_kill_operation = MALI_PIXEL_KILL_## kill; \
|
||||
rsd->properties.zs_update_operation = MALI_PIXEL_KILL_## update; \
|
||||
} while(0)
|
||||
|
||||
static inline void
|
||||
|
|
@ -98,7 +98,7 @@ pan_shader_classify_pixel_kill_coverage(const struct pan_shader_info *info,
|
|||
bool depth = info->fs.writes_depth;
|
||||
bool stencil = info->fs.writes_stencil;
|
||||
|
||||
rsd->properties.bifrost.shader_modifies_coverage = coverage;
|
||||
rsd->properties.shader_modifies_coverage = coverage;
|
||||
|
||||
if (force_early)
|
||||
SET_PIXEL_KILL(FORCE_EARLY, STRONG_EARLY);
|
||||
|
|
@ -122,7 +122,7 @@ pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
|
|||
rsd->preload.uniform_count = fau_count;
|
||||
|
||||
#if PAN_ARCH >= 7
|
||||
rsd->properties.bifrost.shader_register_allocation =
|
||||
rsd->properties.shader_register_allocation =
|
||||
(info->work_reg_count <= 32) ?
|
||||
MALI_SHADER_REGISTER_ALLOCATION_32_PER_THREAD :
|
||||
MALI_SHADER_REGISTER_ALLOCATION_64_PER_THREAD;
|
||||
|
|
@ -138,11 +138,11 @@ pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
|
|||
pan_shader_classify_pixel_kill_coverage(info, rsd);
|
||||
|
||||
#if PAN_ARCH >= 7
|
||||
rsd->properties.bifrost.shader_wait_dependency_6 = info->bifrost.wait_6;
|
||||
rsd->properties.bifrost.shader_wait_dependency_7 = info->bifrost.wait_7;
|
||||
rsd->properties.shader_wait_dependency_6 = info->bifrost.wait_6;
|
||||
rsd->properties.shader_wait_dependency_7 = info->bifrost.wait_7;
|
||||
#endif
|
||||
|
||||
rsd->properties.bifrost.allow_forward_pixel_to_be_killed =
|
||||
rsd->properties.allow_forward_pixel_to_be_killed =
|
||||
!info->fs.sidefx;
|
||||
|
||||
rsd->preload.fragment.fragment_position = info->fs.reads_frag_coord;
|
||||
|
|
@ -159,8 +159,10 @@ pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
|
|||
info->fs.reads_helper_invocation |
|
||||
info->fs.sample_shading;
|
||||
|
||||
#if PAN_ARCH >= 7
|
||||
rsd->message_preload_1 = info->bifrost.messages[0];
|
||||
rsd->message_preload_2 = info->bifrost.messages[1];
|
||||
#endif
|
||||
break;
|
||||
|
||||
case MESA_SHADER_COMPUTE:
|
||||
|
|
|
|||
999
src/panfrost/lib/v4.xml
Normal file
999
src/panfrost/lib/v4.xml
Normal file
|
|
@ -0,0 +1,999 @@
|
|||
<panxml arch="4">
|
||||
<enum name="Attribute Type">
|
||||
<value name="1D" value="1"/>
|
||||
<value name="1D POT Divisor" value="2"/>
|
||||
<value name="1D Modulus" value="3"/>
|
||||
<value name="1D NPOT Divisor" value="4"/>
|
||||
<value name="3D Linear" value="5"/>
|
||||
<value name="3D Interleaved" value="6"/>
|
||||
<value name="1D Primitive Index Buffer" value="7"/>
|
||||
<value name="1D POT Divisor Write Reduction" value="10"/>
|
||||
<value name="1D Modulus Write Reduction" value="11"/>
|
||||
<value name="1D NPOT Divisor Write Reduction" value="12"/>
|
||||
<value name="Continuation" value="32"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Attribute Special">
|
||||
<value name="Vertex ID" value="34"/>
|
||||
<value name="Instance ID" value="36"/>
|
||||
<value name="Frag Coord" value="37"/>
|
||||
<value name="Front Facing" value="38"/>
|
||||
<value name="Point Coord" value="97"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Channel">
|
||||
<value name="R" value="0"/>
|
||||
<value name="G" value="1"/>
|
||||
<value name="B" value="2"/>
|
||||
<value name="A" value="3"/>
|
||||
<value name="0" value="4"/>
|
||||
<value name="1" value="5"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Depth Source">
|
||||
<value name="Minimum" value="0"/>
|
||||
<value name="Maximum" value="1"/>
|
||||
<value name="Fixed function" value="2"/>
|
||||
<value name="Shader" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Job Type">
|
||||
<value name="Not started" value="0"/>
|
||||
<value name="Null" value="1"/>
|
||||
<value name="Write value" value="2"/>
|
||||
<value name="Cache flush" value="3"/>
|
||||
<value name="Compute" value="4"/>
|
||||
<value name="Vertex" value="5"/>
|
||||
<value name="Geometry" value="6"/>
|
||||
<value name="Tiler" value="7"/>
|
||||
<value name="Fused" value="8"/>
|
||||
<value name="Fragment" value="9"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Draw Mode">
|
||||
<value name="Points" value="1"/>
|
||||
<value name="Lines" value="2"/>
|
||||
<value name="Lines with adjacency" value="3"/>
|
||||
<value name="Line strip" value="4"/>
|
||||
<value name="Line strip with adjacency" value="5"/>
|
||||
<value name="Line loop" value="6"/>
|
||||
<value name="Triangles" value="8"/>
|
||||
<value name="Triangles with adjacency" value="9"/>
|
||||
<value name="Triangle strip" value="10"/>
|
||||
<value name="Triangle strip with adjacency" value="11"/>
|
||||
<value name="Triangle fan" value="12"/>
|
||||
<value name="Polygon" value="13"/>
|
||||
<value name="Quads" value="14"/>
|
||||
<value name="Quad strip" value="15"/>
|
||||
<value name="Parallelogram" value="16"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Exception Access">
|
||||
<value name="None" value="0"/>
|
||||
<value name="Execute" value="2"/>
|
||||
<value name="Read" value="1"/>
|
||||
<value name="Write" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Func">
|
||||
<value name="Never" value="0"/>
|
||||
<value name="Less" value="1"/>
|
||||
<value name="Equal" value="2"/>
|
||||
<value name="Lequal" value="3"/>
|
||||
<value name="Greater" value="4"/>
|
||||
<value name="Not Equal" value="5"/>
|
||||
<value name="Gequal" value="6"/>
|
||||
<value name="Always" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Format">
|
||||
<value name="ETC2 RGB8" value="1"/>
|
||||
<value name="ETC2 R11 UNORM" value="2"/>
|
||||
<value name="ETC2 RGBA8" value="3"/>
|
||||
<value name="ETC2 RG11 UNORM" value="4"/>
|
||||
<!--- 5 reserved *-->
|
||||
<value name="NXR" value="6"/>
|
||||
<value name="BC1 UNORM" value="7"/>
|
||||
<value name="BC2 UNORM" value="8"/>
|
||||
<value name="BC3 UNORM" value="9"/>
|
||||
<value name="BC4 UNORM" value="10"/>
|
||||
<value name="BC4 SNORM" value="11"/>
|
||||
<value name="BC5 UNORM" value="12"/>
|
||||
<value name="BC5 SNORM" value="13"/>
|
||||
<value name="BC6H UF16" value="14"/>
|
||||
<value name="BC6H SF16" value="15"/>
|
||||
<value name="BC7 UNORM" value="16"/>
|
||||
<value name="ETC2 R11 SNORM" value="17"/>
|
||||
<value name="ETC2 RG11 SNORM" value="18"/>
|
||||
<value name="ETC2 RGB8A1" value="19"/>
|
||||
<!--- 20-31 reserved *-->
|
||||
<value name="RGB565" value="64"/>
|
||||
<value name="RGB5 A1 UNORM" value="65"/>
|
||||
<value name="A1 BGR5 UNORM" value="66"/>
|
||||
<value name="RGB10 A2 UNORM" value="67"/>
|
||||
<value name="A2 BGR10 UNORM" value="68"/>
|
||||
<value name="RGB10 A2 SNORM" value="69"/>
|
||||
<value name="A2 BGR10 SNORM" value="70"/>
|
||||
<value name="RGB10 A2UI" value="71"/>
|
||||
<value name="A2 BGR10UI" value="72"/>
|
||||
<value name="RGB10 A2I" value="73"/>
|
||||
<value name="A2 BGR10I" value="74"/>
|
||||
<value name="RGB332 UNORM" value="75"/>
|
||||
<value name="BGR233 UNORM" value="76"/>
|
||||
<value name="Z24X8 UNORM" value="77"/>
|
||||
<value name="X8Z24" value="78"/>
|
||||
<value name="X32 S8X24" value="79"/>
|
||||
<value name="X24S8 X32" value="80"/>
|
||||
<value name="R32 FIXED" value="81"/>
|
||||
<value name="RG32 FIXED" value="82"/>
|
||||
<value name="RGB32 FIXED" value="83"/>
|
||||
<value name="RGBA32 FIXED" value="84"/>
|
||||
<value name="Tilebuffer Native" value="85"/>
|
||||
<!--- 86-88 reserved *-->
|
||||
<value name="R11F G11F B10F" value="89"/>
|
||||
<value name="B10F G11F R11F" value="90"/>
|
||||
<value name="R9F G9F B9F E5F" value="91"/>
|
||||
<value name="E5F B9F G9F R9F" value="92"/>
|
||||
<value name="Snap 2" value="93"/>
|
||||
<!--- RGBA32F + snap to 2^-8, used for vertex writes -->
|
||||
<value name="Snap 4" value="94"/>
|
||||
<value name="Constant" value="95"/>
|
||||
<value name="R1 SNORM" value="96"/>
|
||||
<value name="R2 SNORM" value="97"/>
|
||||
<value name="R4 SNORM" value="98"/>
|
||||
<value name="R8 SNORM" value="99"/>
|
||||
<value name="R16 SNORM" value="100"/>
|
||||
<value name="R32 SNORM" value="101"/>
|
||||
<value name="R64 SNORM" value="102"/>
|
||||
<!--- 103 reserved -->
|
||||
<value name="RG1 SNORM" value="104"/>
|
||||
<value name="RG2 SNORM" value="105"/>
|
||||
<value name="RG4 SNORM" value="106"/>
|
||||
<value name="RG8 SNORM" value="107"/>
|
||||
<value name="RG16 SNORM" value="108"/>
|
||||
<value name="RG32 SNORM" value="109"/>
|
||||
<value name="RG64 SNORM" value="110"/>
|
||||
<!-- 111 reserved -->
|
||||
<value name="RGB1 SNORM" value="112"/>
|
||||
<value name="RGB2 SNORM" value="113"/>
|
||||
<value name="RGB4 SNORM" value="114"/>
|
||||
<value name="RGB8 SNORM" value="115"/>
|
||||
<value name="RGB16 SNORM" value="116"/>
|
||||
<value name="RGB32 SNORM" value="117"/>
|
||||
<value name="RGB64 SNORM" value="118"/>
|
||||
<!-- 119 reserved -->
|
||||
<value name="RGBA1 SNORM" value="120"/>
|
||||
<value name="RGBA2 SNORM" value="121"/>
|
||||
<value name="RGBA4 SNORM" value="122"/>
|
||||
<value name="RGBA8 SNORM" value="123"/>
|
||||
<value name="RGBA16 SNORM" value="124"/>
|
||||
<value name="RGBA32 SNORM" value="125"/>
|
||||
<value name="RGBA64 SNORM" value="126"/>
|
||||
<!-- 127 reserved -->
|
||||
<value name="R1UI" value="128"/>
|
||||
<value name="R2UI" value="129"/>
|
||||
<value name="R4UI" value="130"/>
|
||||
<value name="R8UI" value="131"/>
|
||||
<value name="R16UI" value="132"/>
|
||||
<value name="R32UI" value="133"/>
|
||||
<value name="R64UI" value="134"/>
|
||||
<value name="R64F" value="135"/>
|
||||
<value name="RG1UI" value="136"/>
|
||||
<value name="RG2UI" value="137"/>
|
||||
<value name="RG4UI" value="138"/>
|
||||
<value name="RG8UI" value="139"/>
|
||||
<value name="RG16UI" value="140"/>
|
||||
<value name="RG32UI" value="141"/>
|
||||
<value name="RG64UI" value="142"/>
|
||||
<value name="RG64F" value="143"/>
|
||||
<value name="RGB1UI" value="144"/>
|
||||
<value name="RGB2UI" value="145"/>
|
||||
<value name="RGB4UI" value="146"/>
|
||||
<value name="RGB8UI" value="147"/>
|
||||
<value name="RGB16UI" value="148"/>
|
||||
<value name="RGB32UI" value="149"/>
|
||||
<value name="RGB64UI" value="150"/>
|
||||
<value name="RGB64F" value="151"/>
|
||||
<value name="RGBA1UI" value="152"/>
|
||||
<value name="RGBA2UI" value="153"/>
|
||||
<value name="RGBA4UI" value="154"/>
|
||||
<value name="RGBA8UI" value="155"/>
|
||||
<value name="RGBA16UI" value="156"/>
|
||||
<value name="RGBA32UI" value="157"/>
|
||||
<value name="RGBA64UI" value="158"/>
|
||||
<value name="RGBA64F" value="159"/>
|
||||
<value name="R1 UNORM" value="160"/>
|
||||
<value name="R2 UNORM" value="161"/>
|
||||
<value name="R4 UNORM" value="162"/>
|
||||
<value name="R8 UNORM" value="163"/>
|
||||
<value name="R16 UNORM" value="164"/>
|
||||
<value name="R32 UNORM" value="165"/>
|
||||
<value name="R64 UNORM" value="166"/>
|
||||
<value name="R32F" value="167"/>
|
||||
<value name="RG1 UNORM" value="168"/>
|
||||
<value name="RG2 UNORM" value="169"/>
|
||||
<value name="RG4 UNORM" value="170"/>
|
||||
<value name="RG8 UNORM" value="171"/>
|
||||
<value name="RG16 UNORM" value="172"/>
|
||||
<value name="RG32 UNORM" value="173"/>
|
||||
<value name="RG64 UNORM" value="174"/>
|
||||
<value name="RG32F" value="175"/>
|
||||
<value name="RGB1 UNORM" value="176"/>
|
||||
<value name="RGB2 UNORM" value="177"/>
|
||||
<value name="RGB4 UNORM" value="178"/>
|
||||
<value name="RGB8 UNORM" value="179"/>
|
||||
<value name="RGB16 UNORM" value="180"/>
|
||||
<value name="RGB32 UNORM" value="181"/>
|
||||
<value name="RGB64 UNORM" value="182"/>
|
||||
<value name="RGB32F" value="183"/>
|
||||
<value name="RGBA1 UNORM" value="184"/>
|
||||
<value name="RGBA2 UNORM" value="185"/>
|
||||
<value name="RGBA4 UNORM" value="186"/>
|
||||
<value name="RGBA8 UNORM" value="187"/>
|
||||
<value name="RGBA16 UNORM" value="188"/>
|
||||
<value name="RGBA32 UNORM" value="189"/>
|
||||
<value name="RGBA64 UNORM" value="190"/>
|
||||
<value name="RGBA32F" value="191"/>
|
||||
<value name="R1I" value="192"/>
|
||||
<value name="R2I" value="193"/>
|
||||
<value name="R4I" value="194"/>
|
||||
<value name="R8I" value="195"/>
|
||||
<value name="R16I" value="196"/>
|
||||
<value name="R32I" value="197"/>
|
||||
<value name="R64I" value="198"/>
|
||||
<value name="R16F" value="199"/>
|
||||
<value name="RG1I" value="200"/>
|
||||
<value name="RG2I" value="201"/>
|
||||
<value name="RG4I" value="202"/>
|
||||
<value name="RG8I" value="203"/>
|
||||
<value name="RG16I" value="204"/>
|
||||
<value name="RG32I" value="205"/>
|
||||
<value name="RG64I" value="206"/>
|
||||
<value name="RG16F" value="207"/>
|
||||
<value name="RGB1I" value="208"/>
|
||||
<value name="RGB2I" value="209"/>
|
||||
<value name="RGB4I" value="210"/>
|
||||
<value name="RGB8I" value="211"/>
|
||||
<value name="RGB16I" value="212"/>
|
||||
<value name="RGB32I" value="213"/>
|
||||
<value name="RGB64I" value="214"/>
|
||||
<value name="RGB16F" value="215"/>
|
||||
<value name="RGBA1I" value="216"/>
|
||||
<value name="RGBA2I" value="217"/>
|
||||
<value name="RGBA4I" value="218"/>
|
||||
<value name="RGBA8I" value="219"/>
|
||||
<value name="RGBA16I" value="220"/>
|
||||
<value name="RGBA32I" value="221"/>
|
||||
<value name="RGBA64I" value="222"/>
|
||||
<value name="RGBA16F" value="223"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Swizzle">
|
||||
<value name="YUVA" value="0"/>
|
||||
<value name="YVUA" value="1"/>
|
||||
<value name="UYVA" value="2"/>
|
||||
<value name="UVYA" value="3"/>
|
||||
<value name="VUYA" value="4"/>
|
||||
<value name="VYUA" value="5"/>
|
||||
<value name="Y00A" value="6"/>
|
||||
<value name="YXXA" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Conversion Mode">
|
||||
<value name="No Conversion" value="0"/>
|
||||
<value name="BT 601" value="3"/>
|
||||
<value name="BT 709" value="4"/>
|
||||
<value name="BT 2020" value="6"/>
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Cr Siting">
|
||||
<value name="Co-Sited" value="0"/>
|
||||
<value name="Center Y" value="1"/>
|
||||
<value name="Center X" value="2"/>
|
||||
<value name="Center" value="3"/>
|
||||
<value name="One Quarter" value="4"/>
|
||||
<value name="Three Quarters" value="5"/>
|
||||
<value name="Replicated" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Block Format">
|
||||
<!--- 16x16 block u-interleaved -->
|
||||
<value name="Tiled U-Interleaved" value="0"/>
|
||||
<value name="Tiled Linear" value="1"/>
|
||||
<value name="Linear" value="2"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Mipmap Mode">
|
||||
<value name="Nearest" value="0"/>
|
||||
<value name="Performance Trilinear" value="2"/>
|
||||
<value name="Trilinear" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="MSAA">
|
||||
<value name="Single" value="0"/>
|
||||
<!-- N samples, 1 surface, resolved -->
|
||||
<value name="Average" value="1"/>
|
||||
<!-- N samples, 1 surface, unresolved -->
|
||||
<value name="Multiple" value="2"/>
|
||||
<!-- N samples, N surfaces -->
|
||||
<value name="Layered" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Index Type">
|
||||
<value name="None" value="0"/>
|
||||
<value name="UINT8" value="1"/>
|
||||
<value name="UINT16" value="2"/>
|
||||
<value name="UINT32" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Occlusion Mode">
|
||||
<value name="Disabled" value="0"/>
|
||||
<value name="Predicate" value="1"/>
|
||||
<value name="Counter" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Stencil Op">
|
||||
<value name="Keep" value="0"/>
|
||||
<value name="Replace" value="1"/>
|
||||
<value name="Zero" value="2"/>
|
||||
<value name="Invert" value="3"/>
|
||||
<value name="Incr Wrap" value="4"/>
|
||||
<value name="Decr Wrap" value="5"/>
|
||||
<value name="Incr Sat" value="6"/>
|
||||
<value name="Decr Sat" value="7"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Texture Dimension">
|
||||
<value name="Cube" value="0"/>
|
||||
<value name="1D" value="1"/>
|
||||
<value name="2D" value="2"/>
|
||||
<value name="3D" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Texture Layout">
|
||||
<!--- 16x16 block u-interleaved -->
|
||||
<value name="Tiled" value="1"/>
|
||||
<value name="Linear" value="2"/>
|
||||
<value name="AFBC" value="12"/>
|
||||
</enum>
|
||||
|
||||
<enum name="AFBC Surface Flag">
|
||||
<value name="YTR" value="1"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Wrap Mode">
|
||||
<value name="Repeat" value="8"/>
|
||||
<value name="Clamp to Edge" value="9"/>
|
||||
<value name="Clamp" value="10"/>
|
||||
<value name="Clamp to Border" value="11"/>
|
||||
<value name="Mirrored Repeat" value="12"/>
|
||||
<value name="Mirrored Clamp to Edge" value="13"/>
|
||||
<value name="Mirrored Clamp" value="14"/>
|
||||
<value name="Mirrored Clamp to Border" value="15"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Attribute" align="8">
|
||||
<field name="Buffer index" size="9" start="0" type="uint"/>
|
||||
<field name="Offset enable" size="1" start="9" type="bool" default="true"/>
|
||||
<field name="Format" size="22" start="10" type="Pixel Format"/>
|
||||
<field name="Offset" size="32" start="32" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Vertex ID" align="32">
|
||||
<field name="Type" size="8" start="0" type="Attribute Special" default="Vertex ID"/>
|
||||
<field name="Divisor R" size="5" start="56" type="uint"/>
|
||||
<field name="Divisor P" size="3" start="61" type="uint"/>
|
||||
<field name="Offset" size="32" start="96" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Instance ID" align="32">
|
||||
<field name="Type" size="8" start="0" type="Attribute Special" default="Instance ID"/>
|
||||
<field name="Divisor R" size="5" start="56" type="uint"/>
|
||||
<field name="Divisor E" size="1" start="61" type="uint"/>
|
||||
<field name="Divisor P" size="32" start="64" type="uint"/>
|
||||
<field name="Offset" size="32" start="96" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Buffer" align="32">
|
||||
<field name="Special" size="8" start="0" type="Attribute Special"/>
|
||||
<field name="Type" size="6" start="0" type="Attribute Type" default="1D"/>
|
||||
<field name="Pointer" size="50" start="6" type="address" modifier="shr(6)"/>
|
||||
<field name="Stride" size="32" start="64" type="uint"/>
|
||||
<field name="Size" size="32" start="96" type="uint"/>
|
||||
|
||||
<field name="Divisor" size="8" start="56" type="padded" default="1"/>
|
||||
<field name="Divisor R" size="5" start="56" type="uint"/>
|
||||
<field name="Divisor P" size="3" start="61" type="uint"/>
|
||||
<field name="Divisor E" size="1" start="61" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Buffer Continuation NPOT">
|
||||
<field name="Type" size="6" start="0:0" type="Attribute Type" default="Continuation"/>
|
||||
<field name="Divisor Numerator" size="32" start="1:0" type="uint"/>
|
||||
<field name="Divisor" size="32" start="3:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Buffer Continuation 3D" size="4">
|
||||
<field name="Type" size="6" start="0:0" type="Attribute Type" default="Continuation"/>
|
||||
<field name="S dimension" size="16" start="0:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="T dimension" size="16" start="1:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="R dimension" size="16" start="1:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Row Stride" size="32" start="2:0" type="uint"/>
|
||||
<field name="Slice Stride" size="32" start="3:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Blend Operand A">
|
||||
<value name="Zero" value="1"/>
|
||||
<value name="Src" value="2"/>
|
||||
<value name="Dest" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Blend Operand B">
|
||||
<value name="Src Minus Dest" value="0"/>
|
||||
<value name="Src Plus Dest" value="1"/>
|
||||
<value name="Src" value="2"/>
|
||||
<value name="Dest" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Blend Operand C">
|
||||
<value name="Zero" value="1"/>
|
||||
<value name="Src" value="2"/>
|
||||
<value name="Dest" value="3"/>
|
||||
<value name="Src x 2" value="4"/>
|
||||
<value name="Src Alpha" value="5"/>
|
||||
<value name="Dest Alpha" value="6"/>
|
||||
<value name="Constant" value="7"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Blend Function" no-direct-packing="true">
|
||||
<!-- Blend equation: A + (B * C) -->
|
||||
<field name="A" size="2" start="0" type="Blend Operand A"/>
|
||||
<field name="Negate A" size="1" start="3" type="bool"/>
|
||||
<field name="B" size="2" start="4" type="Blend Operand B"/>
|
||||
<field name="Negate B" size="1" start="7" type="bool"/>
|
||||
<field name="C" size="3" start="8" type="Blend Operand C"/>
|
||||
<field name="Invert C" size="1" start="11" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Blend Equation" size="1">
|
||||
<field name="RGB" size="12" start="0:0" type="Blend Function"/>
|
||||
<field name="Alpha" size="12" start="0:12" type="Blend Function"/>
|
||||
<field name="Color Mask" size="4" start="0:28" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Blend" size="4" align="16">
|
||||
<field name="Load Destination" size="1" start="0:0" type="bool" default="false"/>
|
||||
<field name="Blend Shader" size="1" start="0:1" type="bool" default="false"/>
|
||||
<field name="Blend Shader Contains Discard" size="1" start="0:2" type="bool" default="false"/>
|
||||
<field name="Alpha To One" size="1" start="0:8" type="bool"/>
|
||||
<field name="Enable" size="1" start="0:9" type="bool" default="true"/>
|
||||
<field name="sRGB" size="1" start="0:10" type="bool" default="false"/>
|
||||
<field name="Round to FB precision" size="1" start="0:11" type="bool" default="false"/>
|
||||
<field name="Shader PC" size="64" start="2:0" type="address"/>
|
||||
<field name="Equation" size="32" start="2:0" type="Blend Equation"/>
|
||||
<field name="Constant" size="32" start="3:0" type="float"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Invocation">
|
||||
<!-- Dynamic bitfield containing WorkGroupSize.xyz, NumWorkGroups.xyz
|
||||
The number of bits allocated for each number is based on the *_shift
|
||||
fields. For example, workgroups_y_shift gives the bit that
|
||||
gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
|
||||
that gl_NumWorkGroups.z starts at (and therefore one after the bit
|
||||
that gl_NumWorkGroups.y ends at). The actual value for each
|
||||
is one more than the stored value, since if any of the values
|
||||
are zero, then there would be no invocations (and hence no job). -->
|
||||
<field name="Invocations" size="32" start="0:0" type="uint"/>
|
||||
<field name="Size Y shift" size="5" start="1:0" type="uint"/>
|
||||
<field name="Size Z shift" size="5" start="1:5" type="uint"/>
|
||||
<field name="Workgroups X shift" size="6" start="1:10" type="uint"/>
|
||||
<field name="Workgroups Y shift" size="6" start="1:16" type="uint"/>
|
||||
<field name="Workgroups Z shift" size="6" start="1:22" type="uint"/>
|
||||
<field name="Thread group split" size="4" start="1:28" type="uint" prefix="MALI_SPLIT">
|
||||
<value name="Min efficient" value="2"/>
|
||||
</field>
|
||||
</struct>
|
||||
|
||||
<enum name="Point Size Array Format">
|
||||
<value name="None" value="0"/>
|
||||
<value name="FP16" value="2"/>
|
||||
<value name="FP32" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Primitive Restart">
|
||||
<value name="None" value="0"/>
|
||||
<value name="Implicit" value="2"/>
|
||||
<value name="Explicit" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Primitive">
|
||||
<field name="Draw mode" size="8" start="0:0" type="Draw Mode"/>
|
||||
<field name="Index type" size="3" start="0:8" type="Index Type" default="None"/>
|
||||
<field name="Point size array format" size="2" start="0:11" type="Point Size Array Format"/>
|
||||
<field name="Primitive Index Enable" size="1" start="0:13" type="bool"/>
|
||||
<field name="Primitive Index Writeback" size="1" start="0:14" type="bool"/>
|
||||
<field name="First provoking vertex" size="1" start="0:15" type="bool" default="true"/>
|
||||
<field name="Low Depth Cull" size="1" start="0:16" type="bool" default="true"/>
|
||||
<field name="High Depth Cull" size="1" start="0:17" type="bool" default="true"/>
|
||||
<field name="Primitive restart" size="2" start="0:19" type="Primitive Restart"/>
|
||||
<field name="Job Task Split" size="6" start="0:26" type="uint"/>
|
||||
<field name="Base vertex offset" size="32" start="1:0" type="uint"/>
|
||||
<field name="Primitive Restart Index" size="32" start="2:0" type="uint"/>
|
||||
<field name="Index count" size="32" start="3:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Indices" size="64" start="4:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Draw" size="30" align="64">
|
||||
<field name="Four Components Per Vertex" size="1" start="0:0" type="bool"/>
|
||||
<field name="Draw Descriptor Is 64b" size="1" start="0:1" type="bool"/>
|
||||
<field name="Texture Descriptor Is 64b" size="1" start="0:2" type="bool" default="true"/>
|
||||
<field name="Occlusion query" size="2" start="0:3" type="Occlusion Mode" default="Disabled"/>
|
||||
<field name="Front face CCW" size="1" start="0:5" type="bool"/>
|
||||
<field name="Cull front face" size="1" start="0:6" type="bool"/>
|
||||
<field name="Cull back face" size="1" start="0:7" type="bool"/>
|
||||
<field name="Flat Shading Vertex" size="1" start="0:8" type="uint"/>
|
||||
<field name="Primitive Barrier" size="1" start="0:10" type="bool"/>
|
||||
<field name="Clean Fragment Write" size="1" start="0:11" type="bool"/>
|
||||
<field name="Instance Size" size="8" start="0:16" type="padded" default="1"/>
|
||||
<field name="Instance Primitive Size" size="8" start="0:24" type="padded" default="1"/>
|
||||
<field name="Offset start" size="32" start="1:0" type="uint"/>
|
||||
<field name="Primitive Index Base" size="32" start="2:0" type="uint"/>
|
||||
<field name="Position" size="64" start="4:0" type="address"/>
|
||||
<field name="Uniform buffers" size="64" start="6:0" type="address"/>
|
||||
<field name="Textures" size="64" start="8:0" type="address"/>
|
||||
<field name="Samplers" size="64" start="10:0" type="address"/>
|
||||
<field name="Push uniforms" size="64" start="12:0" type="address"/>
|
||||
<field name="State" size="64" start="14:0" type="address"/>
|
||||
<field name="Attribute buffers" size="64" start="16:0" type="address"/>
|
||||
<field name="Attributes" size="64" start="18:0" type="address"/>
|
||||
<field name="Varying buffers" size="64" start="20:0" type="address"/>
|
||||
<field name="Varyings" size="64" start="22:0" type="address"/>
|
||||
<field name="Viewport" size="64" start="24:0" type="address"/>
|
||||
<field name="Occlusion" size="64" start="26:0" type="address"/>
|
||||
<field name="Thread Storage" size="64" start="28:0" type="address"/>
|
||||
<field name="FBD" size="64" start="28:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Surface" align="8">
|
||||
<field name="Pointer" size="64" start="0:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Surface With Stride" align="8">
|
||||
<field name="Pointer" size="64" start="0:0" type="address"/>
|
||||
<field name="Row stride" size="32" start="2:0" type="int"/>
|
||||
<field name="Surface stride" size="32" start="3:0" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Sampler" align="32">
|
||||
<field name="Magnify Nearest" size="1" start="0" type="bool" default="true"/>
|
||||
<field name="Minify Nearest" size="1" start="1" type="bool" default="true"/>
|
||||
<field name="Mipmap Mode" size="2" start="3" type="Mipmap Mode" default="Nearest"/>
|
||||
<field name="Normalized Coordinates" size="1" start="5" type="bool" default="true"/>
|
||||
<field name="Isotropic LOD" size="1" start="6" type="bool"/>
|
||||
<field name="LOD Bias" size="16" start="0:16" type="int" default="0"/>
|
||||
<field name="Minimum LOD" size="16" start="1:0" type="uint" default="0"/>
|
||||
<field name="Maximum LOD" size="16" start="1:16" type="uint" default="1"/>
|
||||
<field name="Wrap Mode S" size="4" start="2:0" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Wrap Mode T" size="4" start="2:4" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Wrap Mode R" size="4" start="2:8" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Compare Function" size="3" start="2:12" type="Func" default="Never"/>
|
||||
<field name="Seamless Cube Map" size="1" start="2:15" type="bool" default="true"/>
|
||||
<field name="Border Color R" size="32" start="4:0" type="uint/float" default="0.0"/>
|
||||
<field name="Border Color G" size="32" start="5:0" type="uint/float" default="0.0"/>
|
||||
<field name="Border Color B" size="32" start="6:0" type="uint/float" default="0.0"/>
|
||||
<field name="Border Color A" size="32" start="7:0" type="uint/float" default="0.0"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Texture" size="8" align="64">
|
||||
<field name="Width" size="16" start="0:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Height" size="16" start="0:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Depth" size="16" start="1:0" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Sample count" size="16" start="1:0" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Array size" size="16" start="1:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Format" size="22" start="2:0" type="Pixel Format"/>
|
||||
<field name="Dimension" size="2" start="2:22" type="Texture Dimension"/>
|
||||
<field name="Texel ordering" size="4" start="2:24" type="Texture Layout"/>
|
||||
<field name="Surface pointer is 64b" size="1" start="2:28" type="bool" default="true"/>
|
||||
<field name="Manual stride" size="1" start="2:29" type="bool" default="false"/>
|
||||
<field name="Levels" size="8" start="3:24" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Swizzle" size="12" start="4:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="FP Mode">
|
||||
<value name="GL Inf/NaN Allowed" value="0"/>
|
||||
<value name="GL Inf/NaN Suppressed" value="1"/>
|
||||
<value name="CL" value="2"/>
|
||||
<value name="D3D11" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Renderer Properties" size="1">
|
||||
<field name="Uniform buffer count" size="8" start="0" type="uint"/>
|
||||
<field name="Depth source" size="2" start="8" type="Depth Source" default="Minimum"/>
|
||||
<field name="Shader contains barrier" size="1" start="11" type="bool"/>
|
||||
<field name="Force early-z" size="1" start="10" type="bool"/>
|
||||
<field name="Shader contains discard" size="1" start="12" type="bool"/>
|
||||
<field name="Shader has side-effects" size="1" start="13" type="bool"/>
|
||||
<field name="Shader reads tilebuffer" size="1" start="14" type="bool"/>
|
||||
<field name="Forward pixel kill" size="1" start="15" type="bool"/>
|
||||
<field name="Work register count" size="5" start="16" type="uint"/>
|
||||
<field name="Uniform count" size="5" start="21" type="uint"/>
|
||||
<field name="Stencil from shader" size="1" start="28" type="bool"/>
|
||||
<field name="FP mode" size="3" start="29" type="FP Mode"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Shader" size="4">
|
||||
<field name="Shader" size="64" start="0:0" type="address"/>
|
||||
<field name="Sampler count" size="16" start="2:0" type="uint"/>
|
||||
<field name="Texture count" size="16" start="2:16" type="uint"/>
|
||||
<field name="Attribute count" size="16" start="3:0" type="uint"/>
|
||||
<field name="Varying count" size="16" start="3:16" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Multisample, Misc" size="1">
|
||||
<field name="Sample mask" size="16" start="0" type="uint"/>
|
||||
<field name="Multisample enable" size="1" start="16" type="bool"/>
|
||||
<field name="Multisample late coverage" size="1" start="17" type="bool"/>
|
||||
<field name="Evaluate per-sample" size="1" start="18" type="bool"/>
|
||||
<field name="Fixed-function depth range fixed" size="1" start="19" type="bool"/>
|
||||
<field name="Shader depth range fixed" size="1" start="20" type="bool"/>
|
||||
<field name="Load destination" size="1" start="21" type="bool"/>
|
||||
<field name="Blend shader" size="1" start="22" type="bool"/>
|
||||
<field name="Blend shader discard" size="1" start="23" type="bool"/>
|
||||
<field name="Depth function" size="3" start="24" type="Func"/>
|
||||
<field name="Depth write mask" size="1" start="27" type="bool"/>
|
||||
<field name="Fixed-function near discard" size="1" start="28" type="bool"/>
|
||||
<field name="Fixed-function far discard" size="1" start="29" type="bool"/>
|
||||
<field name="Fragment near discard" size="1" start="30" type="bool"/>
|
||||
<field name="Fragment far discard" size="1" start="31" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Stencil Mask, Misc" size="1">
|
||||
<field name="Stencil mask front" size="8" start="0" type="uint"/>
|
||||
<field name="Stencil mask back" size="8" start="8" type="uint"/>
|
||||
<field name="Stencil enable" size="1" start="16" type="bool"/>
|
||||
<field name="Alpha-to-coverage" size="1" start="17" type="bool"/>
|
||||
<field name="Alpha-to-coverage Invert" size="1" start="18" type="bool"/>
|
||||
<field name="Alpha to one" size="1" start="19" type="bool"/>
|
||||
<field name="Write enable" size="1" start="20" type="bool"/>
|
||||
<field name="Alpha test compare function" size="3" start="21" type="Func"/>
|
||||
<field name="sRGB" size="1" start="24" type="bool"/>
|
||||
<field name="Dither disable" size="1" start="25" type="bool"/>
|
||||
<field name="Force seamless cubemaps" size="1" start="26" type="bool"/>
|
||||
<field name="Depth Range 1" size="1" start="28" type="bool"/>
|
||||
<field name="Depth Range 2" size="1" start="29" type="bool"/>
|
||||
<field name="Single-sampled lines" size="1" start="30" type="bool"/>
|
||||
<field name="Point snap" size="1" start="31" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Stencil">
|
||||
<field name="Reference Value" size="8" start="0" type="uint"/>
|
||||
<field name="Mask" size="8" start="8" type="uint"/>
|
||||
<field name="Compare Function" size="3" start="16" type="Func"/>
|
||||
<field name="Stencil Fail" size="3" start="19" type="Stencil Op"/>
|
||||
<field name="Depth Fail" size="3" start="22" type="Stencil Op"/>
|
||||
<field name="Depth Pass" size="3" start="25" type="Stencil Op"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Renderer State" align="64">
|
||||
<field name="Shader" size="128" start="0:0" type="Shader"/>
|
||||
<field name="Properties" size="32" start="4:0" type="Renderer Properties"/>
|
||||
<field name="Depth units" size="32" start="5:0" type="float"/>
|
||||
<field name="Depth factor" size="32" start="6:0" type="float"/>
|
||||
<field name="Depth bias clamp" size="32" start="7:0" type="float"/>
|
||||
<field name="Multisample, Misc" size="32" start="8:0" type="Multisample, Misc"/>
|
||||
<field name="Stencil Mask, Misc" size="32" start="9:0" type="Stencil Mask, Misc"/>
|
||||
<field name="Stencil front" size="32" start="10:0" type="Stencil"/>
|
||||
<field name="Stencil back" size="32" start="11:0" type="Stencil"/>
|
||||
<field name="Alpha reference" size="32" start="12:0" type="float"/>
|
||||
<field name="Thread Balancing" size="16" start="13:0" type="uint"/>
|
||||
<field name="Blend Shader" size="64" start="14:0" type="address"/>
|
||||
<field name="Blend Equation" size="32" start="14:0" type="Blend Equation"/>
|
||||
<field name="Blend Constant" size="32" start="15:0" type="float"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Uniform Buffer" align="8">
|
||||
<field name="Entries" size="12" start="0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Pointer" size="52" start="12" type="address" modifier="shr(4)" element="16" count="Entries"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Viewport" align="32">
|
||||
<field name="Minimum X" size="32" start="0:0" default="-INFINITY" type="float"/>
|
||||
<field name="Minimum Y" size="32" start="1:0" default="-INFINITY" type="float"/>
|
||||
<field name="Maximum X" size="32" start="2:0" default="+INFINITY" type="float"/>
|
||||
<field name="Maximum Y" size="32" start="3:0" default="+INFINITY" type="float"/>
|
||||
<field name="Minimum Z" size="32" start="4:0" default="0.0" type="float"/>
|
||||
<field name="Maximum Z" size="32" start="5:0" default="1.0" type="float"/>
|
||||
<field name="Scissor Minimum X" size="16" start="6:0" default="0" type="uint"/>
|
||||
<field name="Scissor Minimum Y" size="16" start="6:16" default="0" type="uint"/>
|
||||
<field name="Scissor Maximum X" size="16" start="7:0" type="uint"/>
|
||||
<field name="Scissor Maximum Y" size="16" start="7:16" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Local Storage" size="8" align="64">
|
||||
<field name="TLS Size" size="5" start="0:0" type="uint"/>
|
||||
<field name="TLS Initial Stack Pointer Offset" size="27" start="0:5" type="uint"/>
|
||||
<field name="WLS Instances" size="5" start="1:0" type="uint" modifier="log2" prefix="MALI_LOCAL_STORAGE" default="MALI_LOCAL_STORAGE_NO_WORKGROUP_MEM">
|
||||
<value name="No Workgroup Mem" value="0x80000000"/>
|
||||
</field>
|
||||
<field name="WLS Size Base" size="2" start="1:5" type="uint"/>
|
||||
<field name="WLS Size Scale" size="5" start="1:8" type="uint"/>
|
||||
<field name="TLS Base Pointer" size="64" start="2:0" type="address"/>
|
||||
<field name="WLS Base Pointer" size="64" start="4:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Tiler Context" size="10">
|
||||
<field name="Polygon List Size" size="32" start="0:0" type="uint" prefix="MALI_MIDGARD_TILER">
|
||||
<value name="Minimum Header Size" value="512"/>
|
||||
</field>
|
||||
<field name="Hierarchy Mask" size="16" start="1:0" type="uint" prefix="MALI_MIDGARD_TILER">
|
||||
<value name="Disabled" value="4096"/>
|
||||
<value name="User" value="4095"/>
|
||||
<value name="Hierarchy Mask" value="511"/>
|
||||
</field>
|
||||
<field name="Polygon List" size="64" start="2:0" type="address"/>
|
||||
<field name="Polygon List Body" size="64" start="4:0" type="address"/>
|
||||
<field name="Heap Start" size="64" start="6:0" type="address"/>
|
||||
<field name="Heap End" size="64" start="8:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Tiler Weights">
|
||||
<field name="Weight0" size="32" start="0:0" type="uint"/>
|
||||
<field name="Weight1" size="32" start="1:0" type="uint"/>
|
||||
<field name="Weight2" size="32" start="2:0" type="uint"/>
|
||||
<field name="Weight3" size="32" start="3:0" type="uint"/>
|
||||
<field name="Weight4" size="32" start="4:0" type="uint"/>
|
||||
<field name="Weight5" size="32" start="5:0" type="uint"/>
|
||||
<field name="Weight6" size="32" start="6:0" type="uint"/>
|
||||
<field name="Weight7" size="32" start="7:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Color Buffer Internal Format">
|
||||
<value name="Raw Value" value="0"/>
|
||||
<value name="R8G8B8A8" value="1"/>
|
||||
<value name="R10G10B10A2" value="2"/>
|
||||
<value name="R8G8B8A2" value="3"/>
|
||||
<value name="R4G4B4A4" value="4"/>
|
||||
<value name="R5G6B5A0" value="5"/>
|
||||
<value name="R5G5B5A1" value="6"/>
|
||||
<value name="RAW8" value="32"/>
|
||||
<value name="RAW16" value="33"/>
|
||||
<value name="RAW32" value="34"/>
|
||||
<value name="RAW64" value="35"/>
|
||||
<value name="RAW128" value="36"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Color Format">
|
||||
<value name="4_32B_CHANNELS" value="0"/>
|
||||
<value name="3_32B_CHANNELS" value="1"/>
|
||||
<value name="2_32B_CHANNELS" value="2"/>
|
||||
<value name="1_32B_CHANNEL" value="3"/>
|
||||
<value name="4_16B_CHANNELS" value="4"/>
|
||||
<value name="3_16B_CHANNELS" value="5"/>
|
||||
<value name="2_16B_CHANNELS" value="6"/>
|
||||
<value name="1_16B_CHANNEL" value="7"/>
|
||||
<value name="R8" value="16"/>
|
||||
<value name="R8G8" value="17"/>
|
||||
<value name="R8G8B8" value="18"/>
|
||||
<value name="R8G8B8A8" value="19"/>
|
||||
<value name="R4G4B4A4" value="20"/>
|
||||
<value name="R5G6B5" value="21"/>
|
||||
<value name="R8G8B8_FROM_R8G8B8A2" value="22"/>
|
||||
<value name="R10G10B10A2" value="24"/>
|
||||
<value name="A2B10G10R10" value="25"/>
|
||||
<value name="R5G5B5A1" value="28"/>
|
||||
<value name="A1B5G5R5" value="29"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Downsampling Accumulation Mode">
|
||||
<value name="Unsigned normalized integer" value="0"/>
|
||||
<value name="Signed normalized integer" value="1"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Sample Layout">
|
||||
<value name="Ordered 4x Grid" value="0"/>
|
||||
<value name="Rotated 4x Grid" value="1"/>
|
||||
<value name="D3D 8x Grid" value="2"/>
|
||||
<value name="D3D 16x Grid" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="ZS Format">
|
||||
<value name="D16" value="1"/>
|
||||
<value name="D24" value="2"/>
|
||||
<value name="D24X8" value="4"/>
|
||||
<value name="D24S8" value="5"/>
|
||||
<value name="X8D24" value="6"/>
|
||||
<value name="S8D24" value="7"/>
|
||||
<value name="D32" value="14"/>
|
||||
<value name="D32_S8X24" value="15"/>
|
||||
</enum>
|
||||
|
||||
<enum name="ZS Preload Format">
|
||||
<value name="D32_S8X24" value="4"/>
|
||||
</enum>
|
||||
|
||||
<enum name="S Format">
|
||||
<value name="S8" value="1"/>
|
||||
<value name="S8X8" value="2"/>
|
||||
<value name="S8X24" value="3"/>
|
||||
<value name="X24S8" value="4"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Tie-Break Rule">
|
||||
<value name="0_IN_180_OUT" value="0"/>
|
||||
<value name="0_OUT_180_IN" value="1"/>
|
||||
<value name="MINUS_180_IN_0_OUT" value="2"/>
|
||||
<value name="MINUS_180_OUT_0_IN" value="3"/>
|
||||
<value name="90_IN_270_OUT" value="4"/>
|
||||
<value name="90_OUT_270_IN" value="5"/>
|
||||
<value name="MINUS_90_IN_90_OUT" value="6"/>
|
||||
<value name="MINUS_90_OUT_90_IN" value="7"/>
|
||||
</enum>
|
||||
|
||||
<struct name="RT Buffer">
|
||||
<field name="Base" size="64" start="0:0" type="address"/>
|
||||
<field name="Row Stride" size="32" start="2:0" type="uint"/>
|
||||
<field name="Surface Stride" size="32" start="3:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Framebuffer Parameters" size="40">
|
||||
<field name="Internal Format" size="3" start="0:0" default="Raw Value" type="Color Buffer Internal Format"/>
|
||||
<field name="Sample Count" size="3" start="0:3" type="uint" default="1" modifier="log2"/>
|
||||
<field name="Swizzle" size="12" start="0:6" type="uint"/>
|
||||
<field name="Color Writeback Format" size="5" start="0:18" default="4_32B_CHANNELS" type="Color Format"/>
|
||||
<field name="MSAA" size="2" start="0:23" default="Single" type="MSAA"/>
|
||||
<field name="sRGB" size="1" start="0:25" type="bool"/>
|
||||
<field name="Color Block Format" size="2" start="0:26" type="Block Format"/>
|
||||
<field name="Dithering Enable" size="1" start="0:28" type="bool"/>
|
||||
<field name="Clean Pixel Write Enable" size="1" start="0:29" type="bool"/>
|
||||
<field name="Color Preload Enable" size="1" start="0:30" type="bool"/>
|
||||
<field name="Color Write Enable" size="1" start="0:31" type="bool"/>
|
||||
<field name="X Downsampling Scale" size="3" start="1:0" type="uint"/>
|
||||
<field name="Y Downsampling Scale" size="3" start="1:3" type="uint"/>
|
||||
<field name="Downsampling Accumulation Mode" size="2" start="1:6" type="Downsampling Accumulation Mode"/>
|
||||
<field name="Sample Layout" size="2" start="1:8" type="Sample Layout"/>
|
||||
<field name="Big Endian" size="1" start="1:10" type="bool"/>
|
||||
<field name="Tie-Break Rule" size="3" start="1:11" type="Tie-Break Rule"/>
|
||||
<field name="CRC Read Enable" size="1" start="1:14" type="bool"/>
|
||||
<field name="CRC Write Enable" size="1" start="1:15" type="bool"/>
|
||||
<field name="ZS Block Format" size="2" start="1:16" type="Block Format"/>
|
||||
<field name="ZS Format" size="4" start="1:18" type="ZS Format" default="D24S8"/>
|
||||
<field name="ZS Preload Enable" size="1" start="1:22" type="bool"/>
|
||||
<field name="ZS Write Enable" size="1" start="1:23" type="bool"/>
|
||||
<field name="S Block Format" size="2" start="1:24" type="Block Format"/>
|
||||
<field name="S Format" size="4" start="1:26" type="S Format"/>
|
||||
<field name="S Write Enable" size="1" start="1:31" type="bool"/>
|
||||
<field name="Bound Min X" size="16" start="2:0" type="uint"/>
|
||||
<field name="Bound Min Y" size="16" start="2:16" type="uint"/>
|
||||
<field name="Bound Max X" size="16" start="3:0" type="uint"/>
|
||||
<field name="Bound Max Y" size="16" start="3:16" type="uint"/>
|
||||
<field name="DCD Offset" size="32" start="4:0" type="uint"/>
|
||||
<field name="CRC Buffer" size="128" start="8:0" type="RT Buffer"/>
|
||||
<field name="Color Writeback" size="128" start="12:0" type="RT Buffer"/>
|
||||
<field name="ZS Writeback" size="128" start="16:0" type="RT Buffer"/>
|
||||
<field name="S Writeback" size="128" start="20:0" type="RT Buffer"/>
|
||||
<field name="Color Load Address" size="64" start="24:0" type="address"/>
|
||||
<field name="Color Load Row Stride" size="32" start="26:0" type="uint"/>
|
||||
<field name="Color Load Surface Stride" size="32" start="27:0" type="uint"/>
|
||||
<field name="Clear Color 0" size="32" start="24:0" type="uint"/>
|
||||
<field name="Clear Color 1" size="32" start="25:0" type="uint"/>
|
||||
<field name="Clear Color 2" size="32" start="26:0" type="uint"/>
|
||||
<field name="Clear Color 3" size="32" start="27:0" type="uint"/>
|
||||
<field name="ZS Load Address" size="64" start="28:0" type="address"/>
|
||||
<field name="ZS Load Row Stride" size="32" start="30:0" type="uint"/>
|
||||
<field name="ZS Load Surface Stride" size="32" start="31:0" type="uint"/>
|
||||
<field name="Z Clear" size="32" start="28:0" type="float"/>
|
||||
<field name="S Clear" size="8" start="32:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Framebuffer Padding 1" size="6">
|
||||
</struct>
|
||||
|
||||
<struct name="Framebuffer Padding 2" size="8">
|
||||
</struct>
|
||||
|
||||
<aggregate name="Framebuffer" size="320" align="64">
|
||||
<section name="Local Storage" offset="0" type="Local Storage"/>
|
||||
<section name="Parameters" offset="32" type="Framebuffer Parameters"/>
|
||||
<section name="Tiler" offset="192" type="Tiler Context"/>
|
||||
<section name="Padding 1" offset="232" type="Framebuffer Padding 1"/>
|
||||
<section name="Tiler Weights" offset="256" type="Tiler Weights"/>
|
||||
<section name="Padding 2" offset="288" type="Framebuffer Padding 2"/>
|
||||
</aggregate>
|
||||
|
||||
<enum name="Sample Pattern">
|
||||
<value name="Single-sampled" value="0"/>
|
||||
<value name="Ordered 4x Grid" value="1"/>
|
||||
<value name="Rotated 4x Grid" value="2"/>
|
||||
<value name="D3D 8x Grid" value="3"/>
|
||||
<value name="D3D 16x Grid" value="4"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Job Header" align="64">
|
||||
<field name="Exception Status" size="32" start="0:0" type="uint"/>
|
||||
<field name="First Incomplete Task" size="32" start="1:0" type="uint"/>
|
||||
<field name="Fault Pointer" size="64" start="2:0" type="address"/>
|
||||
<field name="Is 64b" size="1" start="4:0" type="bool" default="true"/>
|
||||
<field name="Type" size="7" start="4:1" type="Job Type"/>
|
||||
<field name="Barrier" size="1" start="4:8" type="bool"/>
|
||||
<field name="Invalidate Cache" size="1" start="4:9" type="bool"/>
|
||||
<field name="Suppress Prefetch" size="1" start="4:11" type="bool"/>
|
||||
<field name="Enable Texture Mapper" size="1" start="4:12" type="bool"/>
|
||||
<field name="Relax Dependency 1" size="1" start="4:14" type="bool"/>
|
||||
<field name="Relax Dependency 2" size="1" start="4:15" type="bool"/>
|
||||
<field name="Index" size="16" start="4:16" type="uint"/>
|
||||
<field name="Dependency 1" size="16" start="5:0" type="uint"/>
|
||||
<field name="Dependency 2" size="16" start="5:16" type="uint"/>
|
||||
<field name="Next" size="64" start="6:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Fragment Job Payload" size="4">
|
||||
<field name="Bound Min X" size="12" start="0:0" type="uint"/>
|
||||
<field name="Bound Min Y" size="12" start="0:16" type="uint"/>
|
||||
<field name="Bound Max X" size="12" start="1:0" type="uint"/>
|
||||
<field name="Bound Max Y" size="12" start="1:16" type="uint"/>
|
||||
<field name="Framebuffer" size="64" start="2:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<aggregate name="Fragment Job" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Payload" offset="32" type="Fragment Job Payload"/>
|
||||
</aggregate>
|
||||
|
||||
<enum name="Write Value Type">
|
||||
<value name="Cycle Counter" value="1"/>
|
||||
<value name="System Timestamp" value="2"/>
|
||||
<value name="Zero" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Write Value Job Payload">
|
||||
<field name="Address" size="64" start="0:0" type="address"/>
|
||||
<field name="Type" size="32" start="2:0" type="Write Value Type"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Cache Flush Job Payload" size="2">
|
||||
<field name="Clean Shader Core LS" size="1" start="0:0" type="bool"/>
|
||||
<field name="Invalidate Shader Core LS" size="1" start="0:1" type="bool"/>
|
||||
<field name="Invalidate Shader Core Other" size="1" start="0:2" type="bool"/>
|
||||
<field name="Job Manager Clean" size="1" start="0:16" type="bool"/>
|
||||
<field name="Job Manager Invalidate" size="1" start="0:17" type="bool"/>
|
||||
<field name="Tiler Clean" size="1" start="0:24" type="bool"/>
|
||||
<field name="Tiler Invalidate" size="1" start="0:25" type="bool"/>
|
||||
<field name="L2 Clean" size="1" start="1:0" type="bool"/>
|
||||
<field name="L2 Invalidate" size="1" start="1:1" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<aggregate name="Write Value Job" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Payload" offset="32" type="Write Value Job Payload"/>
|
||||
</aggregate>
|
||||
|
||||
<aggregate name="Cache Flush Job" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Payload" offset="32" type="Cache Flush Job Payload"/>
|
||||
</aggregate>
|
||||
|
||||
<struct name="Compute Job Parameters" size="6">
|
||||
<field name="Job Task Split" size="4" start="0:26" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<!-- Compute job also covers vertex and geometry operations -->
|
||||
<aggregate name="Compute Job" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Invocation" offset="32" type="Invocation"/>
|
||||
<section name="Parameters" offset="40" type="Compute Job Parameters"/>
|
||||
<section name="Draw" offset="64" type="Draw"/>
|
||||
</aggregate>
|
||||
|
||||
<struct name="Primitive Size">
|
||||
<field name="Constant" size="32" start="0:0" type="float"/>
|
||||
<field name="Size Array" size="64" start="0:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<aggregate name="Tiler Job" size="192" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Invocation" offset="32" type="Invocation"/>
|
||||
<section name="Primitive" offset="40" type="Primitive"/>
|
||||
<section name="Draw" offset="64" type="Draw"/>
|
||||
<section name="Primitive Size" offset="184" type="Primitive Size"/>
|
||||
</aggregate>
|
||||
</panxml>
|
||||
1108
src/panfrost/lib/v5.xml
Normal file
1108
src/panfrost/lib/v5.xml
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,4 @@
|
|||
<panxml>
|
||||
|
||||
<panxml arch="6">
|
||||
<enum name="Attribute Type">
|
||||
<value name="1D" value="1"/>
|
||||
<value name="1D POT Divisor" value="2"/>
|
||||
|
|
@ -14,14 +13,6 @@
|
|||
<value name="Continuation" value="32"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Attribute Special">
|
||||
<value name="Vertex ID" value="34"/>
|
||||
<value name="Instance ID" value="36"/>
|
||||
<value name="Frag Coord" value="37"/>
|
||||
<value name="Front Facing" value="38"/>
|
||||
<value name="Point Coord" value="97"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Channel">
|
||||
<value name="R" value="0"/>
|
||||
<value name="G" value="1"/>
|
||||
|
|
@ -32,11 +23,12 @@
|
|||
</enum>
|
||||
|
||||
<enum name="Depth Source">
|
||||
<value name="None" value="0"/>
|
||||
<value name="Minimum" value="0"/>
|
||||
<value name="Maximum" value="1"/>
|
||||
<value name="Fixed function" value="2"/>
|
||||
<value name="Shader" value="3"/>
|
||||
</enum>
|
||||
|
||||
|
||||
<enum name="Job Type">
|
||||
<value name="Not started" value="0"/>
|
||||
<value name="Null" value="1"/>
|
||||
|
|
@ -88,9 +80,7 @@
|
|||
<value name="ETC2 R11 UNORM" value="2"/>
|
||||
<value name="ETC2 RGBA8" value="3"/>
|
||||
<value name="ETC2 RG11 UNORM" value="4"/>
|
||||
<!--- Formats 5-6 new in v7 *-->
|
||||
<value name="R4A4 UNORM" value="5"/>
|
||||
<value name="A4R4 UNORM" value="6"/>
|
||||
<!--- 5-6 reserved *-->
|
||||
<value name="BC1 UNORM" value="7"/>
|
||||
<value name="BC2 UNORM" value="8"/>
|
||||
<value name="BC3 UNORM" value="9"/>
|
||||
|
|
@ -108,14 +98,7 @@
|
|||
<value name="ASTC 3D HDR" value="21"/>
|
||||
<value name="ASTC 2D LDR" value="22"/>
|
||||
<value name="ASTC 2D HDR" value="23"/>
|
||||
<!--- Formats 24-31 new in v7 * *-->
|
||||
<value name="R8A8 UNORM" value="24"/>
|
||||
<value name="A8R8 UNORM" value="25"/>
|
||||
<value name="A8 UNORM" value="26"/>
|
||||
<value name="RAW10" value="28"/>
|
||||
<value name="RAW12" value="29"/>
|
||||
<value name="R8G8B8G8" value="30"/>
|
||||
<value name="G8R8G8B8" value="31"/>
|
||||
<!--- 24-63 reserved *-->
|
||||
<value name="RGB565" value="64"/>
|
||||
<value name="RGB5 A1 UNORM" value="65"/>
|
||||
<value name="A1 BGR5 UNORM" value="66"/>
|
||||
|
|
@ -127,8 +110,7 @@
|
|||
<value name="A2 BGR10UI" value="72"/>
|
||||
<value name="RGB10 A2I" value="73"/>
|
||||
<value name="A2 BGR10I" value="74"/>
|
||||
<value name="RGB332 UNORM" value="75"/>
|
||||
<value name="BGR233 UNORM" value="76"/>
|
||||
<!--- 75-76 reserved *-->
|
||||
<value name="Z24X8 UNORM" value="77"/>
|
||||
<value name="X8Z24" value="78"/>
|
||||
<value name="X32 S8X24" value="79"/>
|
||||
|
|
@ -137,17 +119,12 @@
|
|||
<value name="RG32 FIXED" value="82"/>
|
||||
<value name="RGB32 FIXED" value="83"/>
|
||||
<value name="RGBA32 FIXED" value="84"/>
|
||||
<!--- On v7, X24S8 -->
|
||||
<value name="Tilebuffer Native" value="85"/>
|
||||
<value name="S8X24" value="86"/>
|
||||
<value name="Z32 X32" value="87"/>
|
||||
<value name="X32 Z32" value="88"/>
|
||||
<!--- 85-88 reserved *-->
|
||||
<value name="R11F G11F B10F" value="89"/>
|
||||
<value name="B10F G11F R11F" value="90"/>
|
||||
<value name="R9F G9F B9F E5F" value="91"/>
|
||||
<value name="E5F B9F G9F R9F" value="92"/>
|
||||
<!--- Format 93 avaible v7+. On Midgard, acts as a RG16F + snap -->
|
||||
<value name="S8" value="93"/>
|
||||
<value name="Snap 2" value="93"/>
|
||||
<!--- RGBA32F + snap to 2^-8, used for vertex writes -->
|
||||
<value name="Snap 4" value="94"/>
|
||||
<value name="Constant" value="95"/>
|
||||
|
|
@ -283,50 +260,19 @@
|
|||
<value name="RGB5 A1 PU" value="225"/>
|
||||
<value name="R5G6B5 AU" value="226"/>
|
||||
<value name="R5G6B5 PU" value="227"/>
|
||||
<!--- 228-229 reserved *-->
|
||||
<value name="Snap4 V" value="230"/>
|
||||
<value name="R32F RTZ" value="231"/>
|
||||
<!--- 231 reserved *-->
|
||||
<value name="RGBA4 AU" value="232"/>
|
||||
<value name="RGBA4 PU" value="233"/>
|
||||
<!--- 234-236 reserved *-->
|
||||
<value name="RGBA8 TB" value="237"/>
|
||||
<value name="RGB10 A2 TB" value="238"/>
|
||||
<value name="RG32F RTZ" value="239"/>
|
||||
<!--- 239 reserved *-->
|
||||
<value name="Tess Vertex Pack" value="240"/>
|
||||
<value name="RGB8 A2 AU" value="241"/>
|
||||
<value name="RGB8 A2 PU" value="242"/>
|
||||
<value name="RGB32F RTZ" value="247"/>
|
||||
<value name="RGBA32F RTZ" value="255"/>
|
||||
</enum>
|
||||
|
||||
<enum name="RGB Component Order">
|
||||
<value name="RGBA" value="0"/>
|
||||
<value name="GRBA" value="2"/>
|
||||
<value name="BGRA" value="4"/>
|
||||
<value name="ARGB" value="8"/>
|
||||
<value name="AGRB" value="10"/>
|
||||
<value name="ABGR" value="12"/>
|
||||
<value name="RGB1" value="16"/>
|
||||
<value name="GRB1" value="18"/>
|
||||
<value name="BGR1" value="20"/>
|
||||
<value name="1RGB" value="24"/>
|
||||
<value name="1GRB" value="26"/>
|
||||
<value name="1BGR" value="28"/>
|
||||
<value name="RRRR" value="226"/>
|
||||
<value name="RRR1" value="227"/>
|
||||
<value name="RRRA" value="228"/>
|
||||
<value name="000A" value="229"/>
|
||||
<value name="0001" value="230"/>
|
||||
<value name="0000" value="231"/>
|
||||
<value name="Snap4 v9" value="232"/>
|
||||
<value name="Snap4 v10" value="233"/>
|
||||
<value name="Snap4 v11" value="234"/>
|
||||
<value name="Snap4 v12" value="235"/>
|
||||
<value name="Snap4 v13" value="236"/>
|
||||
<value name="Snap4 v14" value="237"/>
|
||||
<value name="Snap4 v15" value="238"/>
|
||||
<value name="Snap4 v16" value="239"/>
|
||||
<!-- Internal only, do not use -->
|
||||
<value name="R000" value="240"/>
|
||||
<value name="RBGA" value="242"/>
|
||||
<!--- 243-255 reserved *-->
|
||||
</enum>
|
||||
|
||||
<enum name="YUV Swizzle">
|
||||
|
|
@ -372,14 +318,6 @@
|
|||
<value name="AFBC" value="3"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Block Format v7">
|
||||
<value name="No Write" value="0"/>
|
||||
<value name="Tiled U-Interleaved" value="1"/>
|
||||
<value name="Linear" value="2"/>
|
||||
<value name="AFBC" value="12"/>
|
||||
<value name="AFBC Tiled" value="13"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Mipmap Mode">
|
||||
<value name="Nearest" value="0"/>
|
||||
<value name="None" value="1"/>
|
||||
|
|
@ -398,7 +336,7 @@
|
|||
<value name="Average" value="1"/>
|
||||
<!-- N samples, 1 surface, unresolved -->
|
||||
<value name="Multiple" value="2"/>
|
||||
<!-- N samples, N surfaces -->
|
||||
<!-- N samples, N surfaces -->
|
||||
<value name="Layered" value="3"/>
|
||||
</enum>
|
||||
|
||||
|
|
@ -452,11 +390,9 @@
|
|||
<enum name="Wrap Mode">
|
||||
<value name="Repeat" value="8"/>
|
||||
<value name="Clamp to Edge" value="9"/>
|
||||
<value name="Clamp" value="10"/>
|
||||
<value name="Clamp to Border" value="11"/>
|
||||
<value name="Mirrored Repeat" value="12"/>
|
||||
<value name="Mirrored Clamp to Edge" value="13"/>
|
||||
<value name="Mirrored Clamp" value="14"/>
|
||||
<value name="Mirrored Clamp to Border" value="15"/>
|
||||
</enum>
|
||||
|
||||
|
|
@ -467,23 +403,7 @@
|
|||
<field name="Offset" size="32" start="32" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Vertex ID" align="32">
|
||||
<field name="Type" size="8" start="0" type="Attribute Special" default="Vertex ID"/>
|
||||
<field name="Divisor R" size="5" start="56" type="uint"/>
|
||||
<field name="Divisor P" size="3" start="61" type="uint"/>
|
||||
<field name="Offset" size="32" start="96" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Instance ID" align="32">
|
||||
<field name="Type" size="8" start="0" type="Attribute Special" default="Instance ID"/>
|
||||
<field name="Divisor R" size="5" start="56" type="uint"/>
|
||||
<field name="Divisor E" size="1" start="61" type="uint"/>
|
||||
<field name="Divisor P" size="32" start="64" type="uint"/>
|
||||
<field name="Offset" size="32" start="96" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Attribute Buffer" align="32">
|
||||
<field name="Special" size="8" start="0" type="Attribute Special"/>
|
||||
<field name="Type" size="6" start="0" type="Attribute Type" default="1D"/>
|
||||
<field name="Pointer" size="50" start="6" type="address" modifier="shr(6)"/>
|
||||
<field name="Stride" size="32" start="64" type="uint"/>
|
||||
|
|
@ -549,15 +469,7 @@
|
|||
<field name="Color Mask" size="4" start="0:28" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Midgard Blend Overlay" size="4" no-direct-packing="true">
|
||||
<field name="Blend Shader" size="1" start="0:1" type="bool" default="false"/>
|
||||
<field name="Blend Shader Contains Discard" size="1" start="0:2" type="bool" default="false"/>
|
||||
<field name="Shader PC" size="64" start="2:0" type="address"/>
|
||||
<field name="Equation" size="32" start="2:0" type="Blend Equation"/>
|
||||
<field name="Constant" size="32" start="3:0" type="float"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Bifrost Register File Format">
|
||||
<enum name="Register File Format">
|
||||
<value name="F16" value="0"/>
|
||||
<value name="F32" value="1"/>
|
||||
<value name="I32" value="2"/>
|
||||
|
|
@ -577,44 +489,38 @@
|
|||
<value name="F16" value="1"/>
|
||||
</enum>
|
||||
|
||||
<enum name="Bifrost Blend Mode">
|
||||
<enum name="Blend Mode">
|
||||
<value name="Shader" value="0"/>
|
||||
<value name="Opaque" value="1"/>
|
||||
<value name="Fixed-Function" value="2"/>
|
||||
<value name="Off" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Bifrost Blend Shader" size="2">
|
||||
<struct name="Blend Shader" size="2">
|
||||
<field name="Return Value" size="29" start="0:3" type="uint" modifier="shr(3)"/>
|
||||
<field name="PC" size="28" start="1:4" type="uint" modifier="shr(4)"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Internal Conversion" size="1">
|
||||
<struct name="Internal Conversion" size="1">
|
||||
<field name="Memory Format" size="22" start="0" type="Pixel Format"/>
|
||||
<field name="Raw" size="1" start="22" type="bool"/>
|
||||
<field name="Register Format" size="3" start="24" type="Bifrost Register File Format"/>
|
||||
<field name="Register Format" size="3" start="24" type="Register File Format"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Blend Fixed-Function" size="2">
|
||||
<struct name="Blend Fixed-Function" size="2">
|
||||
<field name="Num Comps" size="2" start="0:3" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Alpha Zero NOP" size="1" start="0:5" type="bool"/>
|
||||
<field name="Alpha One Store" size="1" start="0:6" type="bool"/>
|
||||
<field name="RT" size="4" start="0:16" type="uint">
|
||||
<value name="MALI_BIFROST_BLEND_MAX_RT" value="8"/>
|
||||
</field>
|
||||
<field name="Conversion" size="32" start="1:0" type="Bifrost Internal Conversion"/>
|
||||
<field name="Conversion" size="32" start="1:0" type="Internal Conversion"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Internal Blend">
|
||||
<field name="Mode" size="2" start="0:0" type="Bifrost Blend Mode"/>
|
||||
<field name="Shader" size="64" start="0:0" type="Bifrost Blend Shader"/>
|
||||
<field name="Fixed-Function" size="64" start="0:0" type="Bifrost Blend Fixed-Function"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Blend Overlay" no-direct-packing="true">
|
||||
<field name="Constant" size="16" start="0:16" type="uint"/>
|
||||
<field name="Equation" size="32" start="1:0" type="Blend Equation"/>
|
||||
<field name="Internal" size="64" start="2:0" type="Bifrost Internal Blend"/>
|
||||
<struct name="Internal Blend">
|
||||
<field name="Mode" size="2" start="0:0" type="Blend Mode"/>
|
||||
<field name="Shader" size="64" start="0:0" type="Blend Shader"/>
|
||||
<field name="Fixed-Function" size="64" start="0:0" type="Blend Fixed-Function"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Blend" size="4" align="16">
|
||||
|
|
@ -623,8 +529,9 @@
|
|||
<field name="Enable" size="1" start="0:9" type="bool" default="true"/>
|
||||
<field name="sRGB" size="1" start="0:10" type="bool" default="false"/>
|
||||
<field name="Round to FB precision" size="1" start="0:11" type="bool" default="false"/>
|
||||
<field name="Midgard" size="1" start="0:0" type="Midgard Blend Overlay"/>
|
||||
<field name="Bifrost" size="1" start="0:0" type="Bifrost Blend Overlay"/>
|
||||
<field name="Constant" size="16" start="0:16" type="uint"/>
|
||||
<field name="Equation" size="32" start="1:0" type="Blend Equation"/>
|
||||
<field name="Internal" size="64" start="2:0" type="Internal Blend"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Invocation">
|
||||
|
|
@ -677,10 +584,9 @@
|
|||
<field name="Indices" size="64" start="4:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Draw" size="30" align="64">
|
||||
<struct name="Draw" size="32" align="64">
|
||||
<field name="Four Components Per Vertex" size="1" start="0:0" type="bool"/>
|
||||
<field name="Draw Descriptor Is 64b" size="1" start="0:1" type="bool"/>
|
||||
<field name="Texture Descriptor Is 64b" size="1" start="0:2" type="bool"/>
|
||||
<field name="Occlusion query" size="2" start="0:3" type="Occlusion Mode" default="Disabled"/>
|
||||
<field name="Front face CCW" size="1" start="0:5" type="bool"/>
|
||||
<field name="Cull front face" size="1" start="0:6" type="bool"/>
|
||||
|
|
@ -709,9 +615,6 @@
|
|||
<field name="FBD" size="64" start="28:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Draw Padding" size="2" align="8">
|
||||
</struct>
|
||||
|
||||
<struct name="Surface" align="8">
|
||||
<field name="Pointer" size="64" start="0:0" type="address"/>
|
||||
</struct>
|
||||
|
|
@ -722,41 +625,7 @@
|
|||
<field name="Surface stride" size="32" start="3:0" type="int"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Midgard Sampler" align="32">
|
||||
<field name="Magnify Nearest" size="1" start="0" type="bool" default="true"/>
|
||||
<field name="Minify Nearest" size="1" start="1" type="bool" default="true"/>
|
||||
<field name="Mipmap Mode" size="2" start="3" type="Mipmap Mode" default="Nearest"/>
|
||||
<field name="Normalized Coordinates" size="1" start="5" type="bool" default="true"/>
|
||||
<field name="LOD Bias" size="16" start="0:16" type="int" default="0"/>
|
||||
<field name="Minimum LOD" size="16" start="1:0" type="uint" default="0"/>
|
||||
<field name="Maximum LOD" size="16" start="1:16" type="uint" default="1"/>
|
||||
<field name="Wrap Mode S" size="4" start="2:0" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Wrap Mode T" size="4" start="2:4" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Wrap Mode R" size="4" start="2:8" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Compare Function" size="3" start="2:12" type="Func" default="Never"/>
|
||||
<field name="Seamless Cube Map" size="1" start="2:15" type="bool" default="true"/>
|
||||
<field name="Border Color R" size="32" start="4:0" type="uint/float" default="0.0"/>
|
||||
<field name="Border Color G" size="32" start="5:0" type="uint/float" default="0.0"/>
|
||||
<field name="Border Color B" size="32" start="6:0" type="uint/float" default="0.0"/>
|
||||
<field name="Border Color A" size="32" start="7:0" type="uint/float" default="0.0"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Midgard Texture" size="8" align="64">
|
||||
<field name="Width" size="16" start="0:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Height" size="16" start="0:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Depth" size="16" start="1:0" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Sample count" size="16" start="1:0" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Array size" size="16" start="1:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Format" size="22" start="2:0" type="Pixel Format"/>
|
||||
<field name="Dimension" size="2" start="2:22" type="Texture Dimension"/>
|
||||
<field name="Texel ordering" size="4" start="2:24" type="Texture Layout"/>
|
||||
<field name="Surface pointer is 64b" size="1" start="2:28" type="bool" default="true"/>
|
||||
<field name="Manual stride" size="1" start="2:29" type="bool" default="false"/>
|
||||
<field name="Levels" size="8" start="3:24" type="uint" modifier="minus(1)" default="1"/>
|
||||
<field name="Swizzle" size="12" start="4:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Sampler" size="8" align="32">
|
||||
<struct name="Sampler" size="8" align="32">
|
||||
<field name="Type" size="4" start="0:0" type="uint" default="1"/>
|
||||
<field name="Wrap Mode R" size="4" start="0:8" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
<field name="Wrap Mode T" size="4" start="0:12" type="Wrap Mode" default="Clamp to Edge"/>
|
||||
|
|
@ -785,7 +654,7 @@
|
|||
<field name="Border Color A" size="32" start="7:0" type="uint/float" default="0.0"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Texture" size="8" align="32">
|
||||
<struct name="Texture" size="8" align="32">
|
||||
<field name="Type" size="4" start="0:0" type="uint" default="2"/>
|
||||
<field name="Dimension" size="2" start="0:4" type="Texture Dimension"/>
|
||||
<field name="Sample corner position" size="1" start="0:8" type="bool" default="false"/>
|
||||
|
|
@ -805,48 +674,22 @@
|
|||
<field name="Depth" size="16" start="7:0" type="uint" modifier="minus(1)" default="1"/>
|
||||
</struct>
|
||||
|
||||
<enum name="FP Mode">
|
||||
<value name="GL Inf/NaN Allowed" value="0"/>
|
||||
<value name="GL Inf/NaN Suppressed" value="1"/>
|
||||
<value name="CL" value="2"/>
|
||||
<value name="D3D11" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Midgard Renderer Properties" size="1" no-direct-packing="true">
|
||||
<field name="Force early-z" size="1" start="10" type="bool"/>
|
||||
<field name="Shader contains discard" size="1" start="12" type="bool"/>
|
||||
<field name="Shader has side-effects" size="1" start="13" type="bool"/>
|
||||
<field name="Shader reads tilebuffer" size="1" start="14" type="bool"/>
|
||||
<field name="Forward pixel kill" size="1" start="15" type="bool"/>
|
||||
<field name="Work register count" size="5" start="16" type="uint"/>
|
||||
<field name="Uniform count" size="5" start="21" type="uint"/>
|
||||
<field name="FP mode" size="3" start="29" type="FP Mode"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Shader Register Allocation">
|
||||
<value name="64 Per Thread" value="0"/>
|
||||
<value name="32 Per Thread" value="2"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Bifrost Renderer Properties" size="1" no-direct-packing="true">
|
||||
<struct name="Renderer Properties" size="1">
|
||||
<field name="Uniform buffer count" size="8" start="0" type="uint"/>
|
||||
<field name="Depth source" size="2" start="8" type="Depth Source" default="Minimum"/>
|
||||
<field name="Shader contains barrier" size="1" start="11" type="bool"/>
|
||||
<field name="Shader register allocation" size="2" start="12" type="Shader Register Allocation"/>
|
||||
<field name="Secondary shader register allocation" size="2" start="14" type="Shader Register Allocation"/>
|
||||
<field name="Shader modifies coverage" size="1" start="16" type="bool"/>
|
||||
<field name="Allow forward pixel to kill" size="1" start="19" type="bool"/>
|
||||
<field name="Allow forward pixel to be killed" size="1" start="20" type="bool"/>
|
||||
<field name="Pixel kill operation" size="2" start="21" type="Pixel Kill"/>
|
||||
<field name="ZS update operation" size="2" start="23" type="Pixel Kill"/>
|
||||
<field name="Point sprite coord origin max Y" size="1" start="27" type="bool"/>
|
||||
<field name="Shader wait dependency 6" size="1" start="30" type="bool"/>
|
||||
<field name="Shader wait dependency 7" size="1" start="31" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Renderer Properties" size="1">
|
||||
<field name="Midgard" size="32" start="0" type="Midgard Renderer Properties"/>
|
||||
<field name="Bifrost" size="32" start="0" type="Bifrost Renderer Properties"/>
|
||||
<field name="Uniform buffer count" size="8" start="0" type="uint"/>
|
||||
<field name="Depth source" size="2" start="8" type="Depth Source" default="None"/>
|
||||
<field name="Shader contains barrier" size="1" start="11" type="bool"/>
|
||||
<field name="Stencil from shader" size="1" start="28" type="bool"/>
|
||||
</struct>
|
||||
|
||||
|
|
@ -909,9 +752,8 @@
|
|||
<field name="Evaluate per-sample" size="1" start="18" type="bool"/>
|
||||
<field name="Fixed-function depth range fixed" size="1" start="19" type="bool"/>
|
||||
<field name="Shader depth range fixed" size="1" start="20" type="bool"/>
|
||||
<field name="SFBD Load destination" size="1" start="21" type="bool"/>
|
||||
<field name="SFBD Blend shader" size="1" start="22" type="bool"/>
|
||||
<field name="SFBD Blend shader discard" size="1" start="23" type="bool"/>
|
||||
<field name="Overdraw alpha1" size="1" start="22" type="bool"/>
|
||||
<field name="Overdraw alpha0" size="1" start="23" type="bool"/>
|
||||
<field name="Depth function" size="3" start="24" type="Func"/>
|
||||
<field name="Depth write mask" size="1" start="27" type="bool"/>
|
||||
<field name="Fixed-function near discard" size="1" start="28" type="bool"/>
|
||||
|
|
@ -926,11 +768,7 @@
|
|||
<field name="Stencil enable" size="1" start="16" type="bool"/>
|
||||
<field name="Alpha-to-coverage" size="1" start="17" type="bool"/>
|
||||
<field name="Alpha-to-coverage Invert" size="1" start="18" type="bool"/>
|
||||
<field name="SFBD Alpha to one" size="1" start="19" type="bool"/>
|
||||
<field name="SFBD Write enable" size="1" start="20" type="bool"/>
|
||||
<field name="Alpha test compare function" size="3" start="21" type="Func"/>
|
||||
<field name="SFBD sRGB" size="1" start="24" type="bool"/>
|
||||
<field name="SFBD Dither disable" size="1" start="25" type="bool"/>
|
||||
<field name="Force seamless cubemaps" size="1" start="26" type="bool"/>
|
||||
<field name="Depth Range 1" size="1" start="28" type="bool"/>
|
||||
<field name="Depth Range 2" size="1" start="29" type="bool"/>
|
||||
|
|
@ -967,7 +805,7 @@
|
|||
<field name="VAR_TEX" size="16" start="0" type="VAR_TEX Preload"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Renderer State" align="64">
|
||||
<struct name="Renderer State" align="64" size="16">
|
||||
<field name="Shader" size="128" start="0:0" type="Shader"/>
|
||||
<field name="Properties" size="32" start="4:0" type="Renderer Properties"/>
|
||||
<field name="Depth units" size="32" start="5:0" type="float"/>
|
||||
|
|
@ -980,15 +818,8 @@
|
|||
<field name="Preload" size="32" start="12:0" type="Preload"/>
|
||||
<field name="Alpha reference" size="32" start="12:0" type="float"/>
|
||||
<field name="Thread Balancing" size="16" start="13:0" type="uint"/>
|
||||
<field name="SFBD Blend Shader" size="64" start="14:0" type="address"/>
|
||||
<field name="SFBD Blend Equation" size="32" start="14:0" type="Blend Equation"/>
|
||||
<field name="SFBD Blend Constant" size="32" start="15:0" type="float"/>
|
||||
<!-- New in v6, only without message preloading -->
|
||||
<field name="Secondary preload" size="32" start="13:0" type="Preload"/>
|
||||
<field name="Secondary shader" size="64" start="13:0" type="address"/>
|
||||
<!-- New in v7, only with a single shader (XXX: type Message Preload) -->
|
||||
<field name="Message Preload 1" size="16" start="15:0" type="uint"/>
|
||||
<field name="Message Preload 2" size="16" start="15:16" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Uniform Buffer" align="8">
|
||||
|
|
@ -1021,32 +852,6 @@
|
|||
<field name="WLS Base Pointer" size="64" start="4:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Midgard Tiler" size="10">
|
||||
<field name="Polygon List Size" size="32" start="0:0" type="uint" prefix="MALI_MIDGARD_TILER">
|
||||
<value name="Minimum Header Size" value="512"/>
|
||||
</field>
|
||||
<field name="Hierarchy Mask" size="16" start="1:0" type="uint" prefix="MALI_MIDGARD_TILER">
|
||||
<value name="Disabled" value="4096"/>
|
||||
<value name="User" value="4095"/>
|
||||
<value name="Hierarchy Mask" value="511"/>
|
||||
</field>
|
||||
<field name="Polygon List" size="64" start="2:0" type="address"/>
|
||||
<field name="Polygon List Body" size="64" start="4:0" type="address"/>
|
||||
<field name="Heap Start" size="64" start="6:0" type="address"/>
|
||||
<field name="Heap End" size="64" start="8:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Midgard Tiler Weights">
|
||||
<field name="Weight0" size="32" start="0:0" type="uint"/>
|
||||
<field name="Weight1" size="32" start="1:0" type="uint"/>
|
||||
<field name="Weight2" size="32" start="2:0" type="uint"/>
|
||||
<field name="Weight3" size="32" start="3:0" type="uint"/>
|
||||
<field name="Weight4" size="32" start="4:0" type="uint"/>
|
||||
<field name="Weight5" size="32" start="5:0" type="uint"/>
|
||||
<field name="Weight6" size="32" start="6:0" type="uint"/>
|
||||
<field name="Weight7" size="32" start="7:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Color Buffer Internal Format">
|
||||
<value name="Raw Value" value="0"/>
|
||||
<value name="R8G8B8A8" value="1"/>
|
||||
|
|
@ -1062,29 +867,7 @@
|
|||
<value name="RAW128" value="36"/>
|
||||
</enum>
|
||||
|
||||
<enum name="SFBD Color Format">
|
||||
<value name="4_32B_CHANNELS" value="0"/>
|
||||
<value name="3_32B_CHANNELS" value="1"/>
|
||||
<value name="2_32B_CHANNELS" value="2"/>
|
||||
<value name="1_32B_CHANNEL" value="3"/>
|
||||
<value name="4_16B_CHANNELS" value="4"/>
|
||||
<value name="3_16B_CHANNELS" value="5"/>
|
||||
<value name="2_16B_CHANNELS" value="6"/>
|
||||
<value name="1_16B_CHANNEL" value="7"/>
|
||||
<value name="R8" value="16"/>
|
||||
<value name="R8G8" value="17"/>
|
||||
<value name="R8G8B8" value="18"/>
|
||||
<value name="R8G8B8A8" value="19"/>
|
||||
<value name="R4G4B4A4" value="20"/>
|
||||
<value name="R5G6B5" value="21"/>
|
||||
<value name="R8G8B8_FROM_R8G8B8A2" value="22"/>
|
||||
<value name="R10G10B10A2" value="24"/>
|
||||
<value name="A2B10G10R10" value="25"/>
|
||||
<value name="R5G5B5A1" value="28"/>
|
||||
<value name="A1B5G5R5" value="29"/>
|
||||
</enum>
|
||||
|
||||
<enum name="MFBD Color Format">
|
||||
<enum name="Color Format">
|
||||
<value name="RAW8" value="0"/>
|
||||
<value name="RAW16" value="1"/>
|
||||
<value name="RAW24" value="2"/>
|
||||
|
|
@ -1169,71 +952,6 @@
|
|||
<field name="Surface Stride" size="32" start="3:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Single-Target Framebuffer Parameters" size="40">
|
||||
<field name="Internal Format" size="3" start="0:0" default="Raw Value" type="Color Buffer Internal Format"/>
|
||||
<field name="Sample Count" size="3" start="0:3" type="uint" default="1" modifier="log2"/>
|
||||
<field name="Swizzle" size="12" start="0:6" type="uint"/>
|
||||
<field name="Color Writeback Format" size="5" start="0:18" default="4_32B_CHANNELS" type="SFBD Color Format"/>
|
||||
<field name="MSAA" size="2" start="0:23" default="Single" type="MSAA"/>
|
||||
<field name="sRGB" size="1" start="0:25" type="bool"/>
|
||||
<field name="Color Block Format" size="2" start="0:26" type="Block Format"/>
|
||||
<field name="Dithering Enable" size="1" start="0:28" type="bool"/>
|
||||
<field name="Clean Pixel Write Enable" size="1" start="0:29" type="bool"/>
|
||||
<field name="Color Preload Enable" size="1" start="0:30" type="bool"/>
|
||||
<field name="Color Write Enable" size="1" start="0:31" type="bool"/>
|
||||
<field name="X Downsampling Scale" size="3" start="1:0" type="uint"/>
|
||||
<field name="Y Downsampling Scale" size="3" start="1:3" type="uint"/>
|
||||
<field name="Downsampling Accumulation Mode" size="2" start="1:6" type="Downsampling Accumulation Mode"/>
|
||||
<field name="Sample Layout" size="2" start="1:8" type="Sample Layout"/>
|
||||
<field name="Big Endian" size="1" start="1:10" type="bool"/>
|
||||
<field name="Tie-Break Rule" size="3" start="1:11" type="Tie-Break Rule"/>
|
||||
<field name="CRC Read Enable" size="1" start="1:14" type="bool"/>
|
||||
<field name="CRC Write Enable" size="1" start="1:15" type="bool"/>
|
||||
<field name="ZS Block Format" size="2" start="1:16" type="Block Format"/>
|
||||
<field name="ZS Format" size="4" start="1:18" type="ZS Format" default="D24S8"/>
|
||||
<field name="ZS Preload Enable" size="1" start="1:22" type="bool"/>
|
||||
<field name="ZS Write Enable" size="1" start="1:23" type="bool"/>
|
||||
<field name="S Block Format" size="2" start="1:24" type="Block Format"/>
|
||||
<field name="S Format" size="4" start="1:26" type="S Format"/>
|
||||
<field name="S Write Enable" size="1" start="1:31" type="bool"/>
|
||||
<field name="Bound Min X" size="16" start="2:0" type="uint"/>
|
||||
<field name="Bound Min Y" size="16" start="2:16" type="uint"/>
|
||||
<field name="Bound Max X" size="16" start="3:0" type="uint"/>
|
||||
<field name="Bound Max Y" size="16" start="3:16" type="uint"/>
|
||||
<field name="DCD Offset" size="32" start="4:0" type="uint"/>
|
||||
<field name="CRC Buffer" size="128" start="8:0" type="RT Buffer"/>
|
||||
<field name="Color Writeback" size="128" start="12:0" type="RT Buffer"/>
|
||||
<field name="ZS Writeback" size="128" start="16:0" type="RT Buffer"/>
|
||||
<field name="S Writeback" size="128" start="20:0" type="RT Buffer"/>
|
||||
<field name="Color Load Address" size="64" start="24:0" type="address"/>
|
||||
<field name="Color Load Row Stride" size="32" start="26:0" type="uint"/>
|
||||
<field name="Color Load Surface Stride" size="32" start="27:0" type="uint"/>
|
||||
<field name="Clear Color 0" size="32" start="24:0" type="uint"/>
|
||||
<field name="Clear Color 1" size="32" start="25:0" type="uint"/>
|
||||
<field name="Clear Color 2" size="32" start="26:0" type="uint"/>
|
||||
<field name="Clear Color 3" size="32" start="27:0" type="uint"/>
|
||||
<field name="ZS Load Address" size="64" start="28:0" type="address"/>
|
||||
<field name="ZS Load Row Stride" size="32" start="30:0" type="uint"/>
|
||||
<field name="ZS Load Surface Stride" size="32" start="31:0" type="uint"/>
|
||||
<field name="Z Clear" size="32" start="28:0" type="float"/>
|
||||
<field name="S Clear" size="8" start="32:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Single-Target Framebuffer Padding 1" size="6">
|
||||
</struct>
|
||||
|
||||
<struct name="Single-Target Framebuffer Padding 2" size="8">
|
||||
</struct>
|
||||
|
||||
<aggregate name="Single-Target Framebuffer" size="320" align="64">
|
||||
<section name="Local Storage" offset="0" type="Local Storage"/>
|
||||
<section name="Parameters" offset="32" type="Single-Target Framebuffer Parameters"/>
|
||||
<section name="Tiler" offset="192" type="Midgard Tiler"/>
|
||||
<section name="Padding 1" offset="232" type="Single-Target Framebuffer Padding 1"/>
|
||||
<section name="Tiler Weights" offset="256" type="Midgard Tiler Weights"/>
|
||||
<section name="Padding 2" offset="288" type="Single-Target Framebuffer Padding 2"/>
|
||||
</aggregate>
|
||||
|
||||
<enum name="Sample Pattern">
|
||||
<value name="Single-sampled" value="0"/>
|
||||
<value name="Ordered 4x Grid" value="1"/>
|
||||
|
|
@ -1254,52 +972,59 @@
|
|||
<value name="MASK" value="63"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Multi-Target Framebuffer Parameters">
|
||||
<field name="Width" size="16" start="0:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Height" size="16" start="0:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Bound Min X" size="16" start="1:0" type="uint"/>
|
||||
<field name="Bound Min Y" size="16" start="1:16" type="uint"/>
|
||||
<field name="Bound Max X" size="16" start="2:0" type="uint"/>
|
||||
<field name="Bound Max Y" size="16" start="2:16" type="uint"/>
|
||||
<field name="Sample Count" size="3" start="3:0" type="uint" default="1" modifier="log2"/>
|
||||
<field name="Sample Pattern" size="3" start="3:3" type="Sample Pattern"/>
|
||||
<field name="Tie-Break Rule" size="3" start="3:6" type="Tie-Break Rule"/>
|
||||
<field name="Effective Tile Size" size="4" start="3:9" type="uint" modifier="log2"/>
|
||||
<field name="X Downsampling Scale" size="3" start="3:13" type="uint"/>
|
||||
<field name="Y Downsampling Scale" size="3" start="3:16" type="uint"/>
|
||||
<field name="Render Target Count" size="4" start="3:19" type="uint" modifier="minus(1)"/>
|
||||
<field name="Color Buffer Allocation" size="8" start="3:24" type="uint" modifier="shr(10)"/>
|
||||
<field name="S Clear" size="8" start="4:0" type="uint"/>
|
||||
<field name="S Write Enable" size="1" start="4:8" type="bool"/>
|
||||
<field name="S Preload Enable" size="1" start="4:9" type="bool"/>
|
||||
<field name="S Unload Enable" size="1" start="4:10" type="bool"/>
|
||||
<field name="Z Internal Format" size="2" start="4:16" type="Z Internal Format"/>
|
||||
<field name="Z Write Enable" size="1" start="4:18" type="bool"/>
|
||||
<field name="Z Preload Enable" size="1" start="4:19" type="bool"/>
|
||||
<field name="Z Unload Enable" size="1" start="4:20" type="bool"/>
|
||||
<field name="Has ZS CRC Extension" size="1" start="4:21" type="bool"/>
|
||||
<field name="CRC Read Enable" size="1" start="4:30" type="bool"/>
|
||||
<field name="CRC Write Enable" size="1" start="4:31" type="bool"/>
|
||||
<field name="Z Clear" size="32" start="5:0" type="float"/>
|
||||
<enum name="Pre Post Frame Shader Mode">
|
||||
<value name="Never" value="0"/>
|
||||
<value name="Always" value="1"/>
|
||||
<value name="Intersect" value="2"/>
|
||||
<value name="Early ZS always" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Framebuffer Parameters">
|
||||
<field name="Pre Frame 0" size="3" start="0:0" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Pre Frame 1" size="3" start="0:3" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Post Frame" size="3" start="0:6" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Sample Locations" size="64" start="4:0" type="address"/>
|
||||
<field name="Frame Shader DCDs" size="64" start="6:0" type="address"/>
|
||||
<field name="Width" size="16" start="8:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="Height" size="16" start="8:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Bound Min X" size="16" start="9:0" type="uint"/>
|
||||
<field name="Bound Min Y" size="16" start="9:16" type="uint"/>
|
||||
<field name="Bound Max X" size="16" start="10:0" type="uint"/>
|
||||
<field name="Bound Max Y" size="16" start="10:16" type="uint"/>
|
||||
<field name="Sample Count" size="3" start="11:0" type="uint" default="1" modifier="log2"/>
|
||||
<field name="Sample Pattern" size="3" start="11:3" type="Sample Pattern"/>
|
||||
<field name="Tie-Break Rule" size="3" start="11:6" type="Tie-Break Rule"/>
|
||||
<field name="Effective Tile Size" size="4" start="11:9" type="uint" modifier="log2"/>
|
||||
<field name="X Downsampling Scale" size="3" start="11:13" type="uint"/>
|
||||
<field name="Y Downsampling Scale" size="3" start="11:16" type="uint"/>
|
||||
<field name="Render Target Count" size="4" start="11:19" type="uint" modifier="minus(1)"/>
|
||||
<field name="Color Buffer Allocation" size="8" start="11:24" type="uint" modifier="shr(10)"/>
|
||||
<field name="S Clear" size="8" start="12:0" type="uint"/>
|
||||
<field name="S Write Enable" size="1" start="12:8" type="bool"/>
|
||||
<field name="S Preload Enable" size="1" start="12:9" type="bool"/>
|
||||
<field name="S Unload Enable" size="1" start="12:10" type="bool"/>
|
||||
<field name="Z Internal Format" size="2" start="12:16" type="Z Internal Format"/>
|
||||
<field name="Z Write Enable" size="1" start="12:18" type="bool"/>
|
||||
<field name="Z Preload Enable" size="1" start="12:19" type="bool"/>
|
||||
<field name="Z Unload Enable" size="1" start="12:20" type="bool"/>
|
||||
<field name="Has ZS CRC Extension" size="1" start="12:21" type="bool"/>
|
||||
<field name="CRC Read Enable" size="1" start="12:30" type="bool"/>
|
||||
<field name="CRC Write Enable" size="1" start="12:31" type="bool"/>
|
||||
<field name="Z Clear" size="32" start="13:0" type="float"/>
|
||||
<field name="Tiler" size="64" start="14:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="ZS CRC Extension" align="64">
|
||||
<struct name="ZS CRC Extension" align="64" size="16">
|
||||
<field name="CRC Base" size="64" start="0:0" type="address"/>
|
||||
<field name="CRC Row Stride" size="32" start="2:0" type="uint"/>
|
||||
<field name="ZS Write Format" size="4" start="3:0" type="ZS Format"/>
|
||||
<field name="ZS Block Format" size="2" start="3:4" type="Block Format"/>
|
||||
<field name="ZS Block Format v7" size="4" start="3:4" type="Block Format v7"/>
|
||||
<field name="ZS MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
|
||||
<field name="ZS MSAA v7" size="2" start="3:8" default="Single" type="MSAA"/>
|
||||
<field name="ZS Big Endian" size="1" start="3:8" type="bool"/>
|
||||
<field name="ZS Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
|
||||
<field name="CRC Render Target" size="4" start="3:11" type="uint"/>
|
||||
<field name="S Write Format" size="4" start="3:16" type="S Format"/>
|
||||
<field name="S Block Format" size="2" start="3:20" type="Block Format"/>
|
||||
<field name="S Block Format v7" size="4" start="3:20" type="Block Format v7"/>
|
||||
<field name="S MSAA" size="2" start="3:22" default="Single" type="MSAA"/>
|
||||
<field name="S MSAA v7" size="2" start="3:24" default="Single" type="MSAA"/>
|
||||
<field name="ZS Preload Format" size="4" start="3:28" type="ZS Preload Format"/>
|
||||
<field name="ZS Writeback Base" size="64" start="4:0" type="address"/>
|
||||
<field name="ZS Writeback Row Stride" size="32" start="6:0" type="uint"/>
|
||||
<field name="ZS Writeback Surface Stride" size="32" start="7:0" type="uint"/>
|
||||
|
|
@ -1308,14 +1033,7 @@
|
|||
<field name="S Writeback Surface Stride" size="32" start="11:0" type="uint"/>
|
||||
<field name="ZS AFBC Header" size="64" start="4:0" type="address"/>
|
||||
<field name="ZS AFBC Row Stride" size="13" start="6:0" type="uint"/>
|
||||
<field name="ZS AFBC Chunk Size" size="12" start="7:0" type="uint"/>
|
||||
<field name="ZS AFBC Sparse" size="1" start="7:16" type="bool"/>
|
||||
<field name="ZS AFBC Body" size="64" start="8:0" type="address"/>
|
||||
<field name="ZS AFBC Body Size" size="32" start="10:0" type="uint"/>
|
||||
<field name="ZS Preload Base" size="64" start="12:0" type="address"/>
|
||||
<field name="ZS Preload Row Stride" size="32" start="14:0" type="uint"/>
|
||||
<field name="ZS Preload Surface Stride" size="32" start="15:0" type="uint"/>
|
||||
<field name="CRC Clear Color" size="64" start="12:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<enum name="RT Endianness">
|
||||
|
|
@ -1342,50 +1060,12 @@
|
|||
<value name="256" value="1"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Render Target Midgard Overlay" size="16">
|
||||
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
|
||||
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
|
||||
<field name="Writeback Sampling Mode" size="2" start="1:29" type="Downsampling Accumulation Mode"/>
|
||||
<field name="Preload Enable" size="1" start="2:0" type="bool"/>
|
||||
<field name="Unload Enable" size="1" start="2:1" type="bool"/>
|
||||
<field name="Preload Format" size="5" start="2:3" type="MFBD Color Format"/>
|
||||
<field name="Preload Endianness" size="2" start="2:8" type="RT Endianness"/>
|
||||
<field name="Preload Block Format" size="4" start="2:10" type="Block Format"/>
|
||||
<field name="Preload MSAA" size="2" start="2:14" type="MSAA"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target Midgard YUV Overlay" size="16">
|
||||
<field name="Conv K5" size="8" start="2:16" type="uint"/>
|
||||
<field name="Conv K6" size="1" start="2:24" type="YUV Conv K6"/>
|
||||
<field name="Conv K7 Clamp" size="2" start="2:25" type="YUV Conv K7 Clamp"/>
|
||||
<field name="Conv K8" size="1" start="2:27" type="YUV Conv K8"/>
|
||||
<field name="Conv Disable" size="1" start="2:31" type="bool"/>
|
||||
<field name="Conv K1" size="8" start="3:0" type="uint"/>
|
||||
<field name="Conv K2" size="8" start="3:8" type="uint"/>
|
||||
<field name="Conv K3" size="8" start="3:16" type="uint"/>
|
||||
<field name="Conv K4" size="8" start="3:24" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target Bifrost YUV Overlay" size="16">
|
||||
<struct name="Render Target YUV Overlay" size="16">
|
||||
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
|
||||
<field name="Full Range" size="1" start="2:20" type="bool"/>
|
||||
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
|
||||
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
|
||||
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target Bifrost v7 Overlay" size="16">
|
||||
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format v7"/>
|
||||
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target Bifrost v6 Overlay" size="16">
|
||||
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
|
||||
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
|
||||
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target YUV Overlay" size="16">
|
||||
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
|
||||
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
|
||||
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
|
||||
|
|
@ -1397,16 +1077,6 @@
|
|||
<field name="Header" size="64" start="4:0" type="address"/>
|
||||
<field name="Row Stride" size="13" start="6:0" type="uint"/>
|
||||
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
|
||||
<field name="YUV Transform Enable" size="1" start="7:17" type="bool"/>
|
||||
<field name="Body" size="64" start="8:0" type="address"/>
|
||||
<field name="Body Size" size="32" start="10:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target Midgard AFBC Overlay" size="16">
|
||||
<field name="Sparse" size="1" start="7:16" type="bool"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Render Target Bifrost AFBC Overlay" size="16">
|
||||
<field name="AFBC Split Block Enable" size="1" start="7:18" type="bool"/>
|
||||
<field name="AFBC Wide Block Enable" size="1" start="7:19" type="bool"/>
|
||||
|
||||
|
|
@ -1414,6 +1084,9 @@
|
|||
when in-place rendering is used with the AFBC block size differing
|
||||
from the effective tile size (XXX: does v6 need a different workaround?) -->
|
||||
<field name="Reverse Issue Order" size="1" start="7:20" type="bool"/>
|
||||
<field name="YUV Transform Enable" size="1" start="7:17" type="bool"/>
|
||||
<field name="Body" size="64" start="8:0" type="address"/>
|
||||
<field name="Body Size" size="32" start="10:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="RT Clear">
|
||||
|
|
@ -1424,53 +1097,33 @@
|
|||
</struct>
|
||||
|
||||
<struct name="Render Target" align="64">
|
||||
<field name="Midgard" size="512" start="0:0" type="Render Target Midgard Overlay"/>
|
||||
<field name="Bifrost v6" size="512" start="0:0" type="Render Target Bifrost v6 Overlay"/>
|
||||
<field name="Bifrost v7" size="512" start="0:0" type="Render Target Bifrost v7 Overlay"/>
|
||||
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
|
||||
<field name="Midgard YUV" size="512" start="0:0" type="Render Target Midgard YUV Overlay"/>
|
||||
<field name="Bifrost YUV" size="512" start="0:0" type="Render Target Bifrost YUV Overlay"/>
|
||||
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
|
||||
<field name="Midgard AFBC" size="512" start="0:0" type="Render Target Midgard AFBC Overlay"/>
|
||||
<field name="Bifrost AFBC" size="512" start="0:0" type="Render Target Bifrost AFBC Overlay"/>
|
||||
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
|
||||
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
|
||||
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
|
||||
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
|
||||
<field name="Write Enable" size="1" start="1:0" type="bool"/>
|
||||
<field name="Writeback Format" size="5" start="1:3" type="MFBD Color Format"/>
|
||||
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
|
||||
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
|
||||
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
|
||||
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
|
||||
<field name="sRGB" size="1" start="1:14" type="bool"/>
|
||||
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
|
||||
<field name="Swizzle" size="12" start="1:16" type="uint"/>
|
||||
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
|
||||
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
|
||||
<field name="Midgard Preload" size="128" start="12:0" type="RT Buffer"/>
|
||||
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
|
||||
</struct>
|
||||
|
||||
<enum name="Pre Post Frame Shader Mode">
|
||||
<value name="Never" value="0"/>
|
||||
<value name="Always" value="1"/>
|
||||
<value name="Intersect" value="2"/>
|
||||
<value name="Early ZS always" value="3"/>
|
||||
</enum>
|
||||
|
||||
<struct name="Bifrost Framebuffer Parameters">
|
||||
<field name="Pre Frame 0" size="3" start="0:0" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Pre Frame 1" size="3" start="0:3" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Post Frame" size="3" start="0:6" type="Pre Post Frame Shader Mode"/>
|
||||
<field name="Sample Locations" size="64" start="4:0" type="address"/>
|
||||
<field name="Frame Shader DCDs" size="64" start="6:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler Heap" align="64">
|
||||
<struct name="Tiler Heap" align="64">
|
||||
<field name="Size" size="32" start="1:0" type="uint" modifier="align(4096)"/>
|
||||
<field name="Base" size="64" start="2:0" type="address"/>
|
||||
<field name="Bottom" size="64" start="4:0" type="address"/>
|
||||
<field name="Top" size="64" start="6:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler Weights" size="8">
|
||||
<struct name="Tiler Weights" size="8">
|
||||
<field name="Weight0" size="16" start="0:16" type="uint"/>
|
||||
<field name="Weight1" size="16" start="1:16" type="uint"/>
|
||||
<field name="Weight2" size="16" start="2:16" type="uint"/>
|
||||
|
|
@ -1481,7 +1134,7 @@
|
|||
<field name="Weight7" size="16" start="7:16" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler State" size="16">
|
||||
<struct name="Tiler State" size="16">
|
||||
<field name="Word0" size="32" start="0:0" type="uint"/>
|
||||
<field name="Word1" size="32" start="1:0" type="uint"/>
|
||||
<field name="Word2" size="32" start="2:0" type="uint"/>
|
||||
|
|
@ -1500,7 +1153,7 @@
|
|||
<field name="Word15" size="32" start="15:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler" size="48" align="64">
|
||||
<struct name="Tiler Context" size="48" align="64">
|
||||
<field name="Polygon List" size="64" start="0:0" type="address"/>
|
||||
<field name="Hierarchy Mask" size="13" start="2:0" type="uint"/>
|
||||
<field name="Sample Pattern" size="3" start="2:13" type="Sample Pattern"/>
|
||||
|
|
@ -1508,25 +1161,16 @@
|
|||
<field name="FB Width" size="16" start="3:0" type="uint" modifier="minus(1)"/>
|
||||
<field name="FB Height" size="16" start="3:16" type="uint" modifier="minus(1)"/>
|
||||
<field name="Heap" size="64" start="6:0" type="address"/>
|
||||
<field name="Weights" size="256" start="8:0" type="Bifrost Tiler Weights"/>
|
||||
<field name="State" size="512" start="32:0" type="Bifrost Tiler State"/>
|
||||
<field name="Weights" size="256" start="8:0" type="Tiler Weights"/>
|
||||
<field name="State" size="512" start="32:0" type="Tiler State"/>
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Tiler Pointer">
|
||||
<field name="Address" size="64" start="0:0" type="address"/>
|
||||
<struct name="Framebuffer Padding" size="16">
|
||||
</struct>
|
||||
|
||||
<struct name="Bifrost Framebuffer Padding" size="16">
|
||||
</struct>
|
||||
|
||||
<aggregate name="Multi-Target Framebuffer" align="64">
|
||||
<section name="Local Storage" offset="0" type="Local Storage"/>
|
||||
<section name="Bifrost Parameters" offset="0" type="Bifrost Framebuffer Parameters"/>
|
||||
<section name="Parameters" offset="32" type="Multi-Target Framebuffer Parameters"/>
|
||||
<section name="Tiler" offset="56" type="Midgard Tiler"/>
|
||||
<section name="Tiler Weights" offset="96" type="Midgard Tiler Weights"/>
|
||||
<section name="Bifrost Tiler Pointer" offset="56" type="Bifrost Tiler Pointer"/>
|
||||
<section name="Bifrost Padding" offset="64" type="Bifrost Framebuffer Padding"/>
|
||||
<aggregate name="Framebuffer" align="64">
|
||||
<section name="Parameters" offset="0" type="Framebuffer Parameters"/>
|
||||
<section name="Padding" offset="64" type="Framebuffer Padding"/>
|
||||
</aggregate>
|
||||
|
||||
<struct name="Job Header" align="64">
|
||||
|
|
@ -1611,7 +1255,6 @@
|
|||
<section name="Invocation" offset="32" type="Invocation"/>
|
||||
<section name="Parameters" offset="40" type="Compute Job Parameters"/>
|
||||
<section name="Draw" offset="64" type="Draw"/>
|
||||
<section name="Draw Padding" offset="184" type="Draw Padding"/>
|
||||
</aggregate>
|
||||
|
||||
<struct name="Primitive Size">
|
||||
|
|
@ -1619,38 +1262,31 @@
|
|||
<field name="Size Array" size="64" start="0:0" type="uint"/>
|
||||
</struct>
|
||||
|
||||
<aggregate name="Midgard Tiler Job" size="192" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Invocation" offset="32" type="Invocation"/>
|
||||
<section name="Primitive" offset="40" type="Primitive"/>
|
||||
<section name="Draw" offset="64" type="Draw"/>
|
||||
<section name="Primitive Size" offset="184" type="Primitive Size"/>
|
||||
</aggregate>
|
||||
|
||||
<struct name="Bifrost Tiler Job Padding" size="12">
|
||||
<struct name="Tiler Pointer">
|
||||
<field name="Address" size="64" start="0:0" type="address"/>
|
||||
</struct>
|
||||
|
||||
<aggregate name="Bifrost Tiler Job" size="256" align="64">
|
||||
<struct name="Tiler Job Padding" size="12">
|
||||
</struct>
|
||||
|
||||
<aggregate name="Tiler Job" size="256" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Invocation" offset="32" type="Invocation"/>
|
||||
<section name="Primitive" offset="40" type="Primitive"/>
|
||||
<section name="Primitive Size" offset="64" type="Primitive Size"/>
|
||||
<section name="Tiler" offset="72" type="Bifrost Tiler Pointer"/>
|
||||
<section name="Padding" offset="80" type="Bifrost Tiler Job Padding"/>
|
||||
<section name="Tiler" offset="72" type="Tiler Pointer"/>
|
||||
<section name="Padding" offset="80" type="Tiler Job Padding"/>
|
||||
<section name="Draw" offset="128" type="Draw"/>
|
||||
<section name="Draw Padding" offset="248" type="Draw Padding"/>
|
||||
</aggregate>
|
||||
|
||||
<aggregate name="Bifrost Indexed Vertex Job" size="384" align="64">
|
||||
<aggregate name="Indexed Vertex Job" size="384" align="64">
|
||||
<section name="Header" offset="0" type="Job Header"/>
|
||||
<section name="Invocation" offset="32" type="Invocation"/>
|
||||
<section name="Primitive" offset="40" type="Primitive"/>
|
||||
<section name="Primitive Size" offset="64" type="Primitive Size"/>
|
||||
<section name="Tiler" offset="72" type="Bifrost Tiler Pointer"/>
|
||||
<section name="Padding" offset="80" type="Bifrost Tiler Job Padding"/>
|
||||
<section name="Tiler" offset="72" type="Tiler Pointer"/>
|
||||
<section name="Padding" offset="80" type="Tiler Job Padding"/>
|
||||
<section name="Fragment Draw" offset="128" type="Draw"/>
|
||||
<section name="Fragment Draw Padding" offset="248" type="Draw Padding"/>
|
||||
<section name="Vertex Draw" offset="256" type="Draw"/>
|
||||
<section name="Vertex Draw Padding" offset="376" type="Draw Padding"/>
|
||||
</aggregate>
|
||||
</panxml>
|
||||
1333
src/panfrost/lib/v7.xml
Normal file
1333
src/panfrost/lib/v7.xml
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -97,7 +97,7 @@ panvk_copy_fb_desc(struct panvk_cmd_buffer *cmdbuf, void *src)
|
|||
{
|
||||
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
|
||||
struct panvk_batch *batch = cmdbuf->state.batch;
|
||||
uint32_t size = pan_size(MULTI_TARGET_FRAMEBUFFER);
|
||||
uint32_t size = pan_size(FRAMEBUFFER);
|
||||
|
||||
if (fbinfo->zs.view.zs || fbinfo->zs.view.s)
|
||||
size += pan_size(ZS_CRC_EXTENSION);
|
||||
|
|
@ -118,7 +118,7 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
|
|||
|
||||
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
|
||||
#if PAN_ARCH <= 5
|
||||
uint32_t tmp_fbd[(pan_size(MULTI_TARGET_FRAMEBUFFER) +
|
||||
uint32_t tmp_fbd[(pan_size(FRAMEBUFFER) +
|
||||
pan_size(ZS_CRC_EXTENSION) +
|
||||
(MAX_RTS * pan_size(RENDER_TARGET))) / 4];
|
||||
#endif
|
||||
|
|
@ -209,7 +209,7 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
|
|||
#if PAN_ARCH <= 5
|
||||
panvk_copy_fb_desc(cmdbuf, tmp_fbd);
|
||||
memcpy(batch->tiler.templ,
|
||||
pan_section_ptr(fbd, MULTI_TARGET_FRAMEBUFFER, TILER),
|
||||
pan_section_ptr(fbd, FRAMEBUFFER, TILER),
|
||||
pan_size(TILER_CONTEXT));
|
||||
#endif
|
||||
|
||||
|
|
@ -262,7 +262,7 @@ panvk_per_arch(cmd_alloc_fb_desc)(struct panvk_cmd_buffer *cmdbuf)
|
|||
batch->fb.info = cmdbuf->state.framebuffer;
|
||||
batch->fb.desc =
|
||||
pan_pool_alloc_desc_aggregate(&cmdbuf->desc_pool.base,
|
||||
PAN_DESC(MULTI_TARGET_FRAMEBUFFER),
|
||||
PAN_DESC(FRAMEBUFFER),
|
||||
PAN_DESC_ARRAY(has_zs_ext ? 1 : 0, ZS_CRC_EXTENSION),
|
||||
PAN_DESC_ARRAY(MAX2(fbinfo->rt_count, 1), RENDER_TARGET));
|
||||
|
||||
|
|
|
|||
|
|
@ -388,9 +388,6 @@ panvk_per_arch(emit_vertex_job)(const struct panvk_pipeline *pipeline,
|
|||
|
||||
pan_section_pack(job, COMPUTE_JOB, DRAW, cfg) {
|
||||
cfg.draw_descriptor_is_64b = true;
|
||||
#if PAN_ARCH == 5
|
||||
cfg.texture_descriptor_is_64b = true;
|
||||
#endif
|
||||
cfg.state = pipeline->rsds[MESA_SHADER_VERTEX];
|
||||
cfg.attributes = draw->stages[MESA_SHADER_VERTEX].attributes;
|
||||
cfg.attribute_buffers = draw->attribute_bufs;
|
||||
|
|
@ -405,8 +402,6 @@ panvk_per_arch(emit_vertex_job)(const struct panvk_pipeline *pipeline,
|
|||
cfg.textures = draw->textures;
|
||||
cfg.samplers = draw->samplers;
|
||||
}
|
||||
|
||||
pan_section_pack(job, COMPUTE_JOB, DRAW_PADDING, cfg);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -450,9 +445,6 @@ panvk_emit_tiler_dcd(const struct panvk_pipeline *pipeline,
|
|||
pan_pack(dcd, DRAW, cfg) {
|
||||
cfg.four_components_per_vertex = true;
|
||||
cfg.draw_descriptor_is_64b = true;
|
||||
#if PAN_ARCH == 5
|
||||
cfg.texture_descriptor_is_64b = true;
|
||||
#endif
|
||||
cfg.front_face_ccw = pipeline->rast.front_ccw;
|
||||
cfg.cull_front_face = pipeline->rast.cull_front_face;
|
||||
cfg.cull_back_face = pipeline->rast.cull_back_face;
|
||||
|
|
@ -519,7 +511,6 @@ panvk_per_arch(emit_tiler_job)(const struct panvk_pipeline *pipeline,
|
|||
pan_section_pack(job, TILER_JOB, TILER, cfg) {
|
||||
cfg.address = draw->tiler_ctx->bifrost;
|
||||
}
|
||||
pan_section_pack(job, TILER_JOB, DRAW_PADDING, padding);
|
||||
pan_section_pack(job, TILER_JOB, PADDING, padding);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -562,24 +553,24 @@ panvk_per_arch(emit_viewport)(const VkViewport *viewport,
|
|||
}
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
static enum mali_bifrost_register_file_format
|
||||
static enum mali_register_file_format
|
||||
bifrost_blend_type_from_nir(nir_alu_type nir_type)
|
||||
{
|
||||
switch(nir_type) {
|
||||
case 0: /* Render target not in use */
|
||||
return 0;
|
||||
case nir_type_float16:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_F16;
|
||||
return MALI_REGISTER_FILE_FORMAT_F16;
|
||||
case nir_type_float32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
|
||||
return MALI_REGISTER_FILE_FORMAT_F32;
|
||||
case nir_type_int32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
|
||||
return MALI_REGISTER_FILE_FORMAT_I32;
|
||||
case nir_type_uint32:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
return MALI_REGISTER_FILE_FORMAT_U32;
|
||||
case nir_type_int16:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_I16;
|
||||
return MALI_REGISTER_FILE_FORMAT_I16;
|
||||
case nir_type_uint16:
|
||||
return MALI_BIFROST_REGISTER_FILE_FORMAT_U16;
|
||||
return MALI_REGISTER_FILE_FORMAT_U16;
|
||||
default:
|
||||
unreachable("Unsupported blend shader type for NIR alu type");
|
||||
}
|
||||
|
|
@ -599,7 +590,7 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
|
|||
if (!blend->rt_count || !rts->equation.color_mask) {
|
||||
cfg.enable = false;
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF;
|
||||
cfg.internal.mode = MALI_BLEND_MODE_OFF;
|
||||
#endif
|
||||
continue;
|
||||
}
|
||||
|
|
@ -609,10 +600,10 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
|
|||
cfg.round_to_fb_precision = !dithered;
|
||||
|
||||
#if PAN_ARCH <= 5
|
||||
cfg.midgard.blend_shader = false;
|
||||
cfg.blend_shader = false;
|
||||
pan_blend_to_fixed_function_equation(blend->rts[rt].equation,
|
||||
&cfg.midgard.equation);
|
||||
cfg.midgard.constant =
|
||||
&cfg.equation);
|
||||
cfg.constant =
|
||||
pan_blend_get_constant(pan_blend_constant_mask(blend->rts[rt].equation),
|
||||
blend->constants);
|
||||
#else
|
||||
|
|
@ -624,7 +615,7 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
|
|||
chan_size = MAX2(format_desc->channel[i].size, chan_size);
|
||||
|
||||
pan_blend_to_fixed_function_equation(blend->rts[rt].equation,
|
||||
&cfg.bifrost.equation);
|
||||
&cfg.equation);
|
||||
|
||||
/* Fixed point constant */
|
||||
float fconst =
|
||||
|
|
@ -632,22 +623,22 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
|
|||
blend->constants);
|
||||
u16 constant = fconst * ((1 << chan_size) - 1);
|
||||
constant <<= 16 - chan_size;
|
||||
cfg.bifrost.constant = constant;
|
||||
cfg.constant = constant;
|
||||
|
||||
if (pan_blend_is_opaque(blend->rts[rt].equation))
|
||||
cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OPAQUE;
|
||||
cfg.internal.mode = MALI_BLEND_MODE_OPAQUE;
|
||||
else
|
||||
cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION;
|
||||
cfg.internal.mode = MALI_BLEND_MODE_FIXED_FUNCTION;
|
||||
|
||||
/* If we want the conversion to work properly,
|
||||
* num_comps must be set to 4
|
||||
*/
|
||||
cfg.bifrost.internal.fixed_function.num_comps = 4;
|
||||
cfg.bifrost.internal.fixed_function.conversion.memory_format =
|
||||
cfg.internal.fixed_function.num_comps = 4;
|
||||
cfg.internal.fixed_function.conversion.memory_format =
|
||||
panfrost_format_to_bifrost_blend(pdev, rts->format, dithered);
|
||||
cfg.bifrost.internal.fixed_function.conversion.register_format =
|
||||
cfg.internal.fixed_function.conversion.register_format =
|
||||
bifrost_blend_type_from_nir(pipeline->fs.info.bifrost.blend[rt].type);
|
||||
cfg.bifrost.internal.fixed_function.rt = rt;
|
||||
cfg.internal.fixed_function.rt = rt;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -663,9 +654,9 @@ panvk_per_arch(emit_blend_constant)(const struct panvk_device *dev,
|
|||
pan_pack(bd, BLEND, cfg) {
|
||||
cfg.enable = false;
|
||||
#if PAN_ARCH == 5
|
||||
cfg.midgard.constant = constant;
|
||||
cfg.constant = constant;
|
||||
#else
|
||||
cfg.bifrost.constant = constant * pipeline->blend.constant[rt].bifrost_factor;
|
||||
cfg.constant = constant * pipeline->blend.constant[rt].bifrost_factor;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -716,8 +707,8 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
|
|||
(pipeline->zs.z_test && pipeline->zs.z_compare_func != MALI_FUNC_ALWAYS) ||
|
||||
pipeline->zs.s_test;
|
||||
|
||||
cfg.properties.midgard.work_register_count = info->work_reg_count;
|
||||
cfg.properties.midgard.force_early_z =
|
||||
cfg.properties.work_register_count = info->work_reg_count;
|
||||
cfg.properties.force_early_z =
|
||||
info->fs.can_early_z && !pipeline->ms.alpha_to_coverage &&
|
||||
pipeline->zs.z_compare_func == MALI_FUNC_ALWAYS;
|
||||
|
||||
|
|
@ -726,15 +717,15 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
|
|||
* when discarding even when the depth buffer is read-only, by
|
||||
* lying to the hardware about the discard and setting the
|
||||
* reads tilebuffer? flag to compensate */
|
||||
cfg.properties.midgard.shader_reads_tilebuffer =
|
||||
cfg.properties.shader_reads_tilebuffer =
|
||||
info->fs.outputs_read ||
|
||||
(!zs_enabled && info->fs.can_discard);
|
||||
cfg.properties.midgard.shader_contains_discard =
|
||||
cfg.properties.shader_contains_discard =
|
||||
zs_enabled && info->fs.can_discard;
|
||||
#else
|
||||
uint8_t rt_written = pipeline->fs.info.outputs_written >> FRAG_RESULT_DATA0;
|
||||
uint8_t rt_mask = pipeline->fs.rt_mask;
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_kill =
|
||||
cfg.properties.allow_forward_pixel_to_kill =
|
||||
pipeline->fs.info.fs.can_fpk &&
|
||||
!(rt_mask & ~rt_written) &&
|
||||
!pipeline->ms.alpha_to_coverage &&
|
||||
|
|
@ -743,14 +734,14 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
|
|||
} else {
|
||||
#if PAN_ARCH == 5
|
||||
cfg.shader.shader = 0x1;
|
||||
cfg.properties.midgard.work_register_count = 1;
|
||||
cfg.properties.work_register_count = 1;
|
||||
cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
|
||||
cfg.properties.midgard.force_early_z = true;
|
||||
cfg.properties.force_early_z = true;
|
||||
#else
|
||||
cfg.properties.bifrost.shader_modifies_coverage = true;
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_kill = true;
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
|
||||
cfg.properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
|
||||
cfg.properties.shader_modifies_coverage = true;
|
||||
cfg.properties.allow_forward_pixel_to_kill = true;
|
||||
cfg.properties.allow_forward_pixel_to_be_killed = true;
|
||||
cfg.properties.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -201,8 +201,8 @@ panvk_per_arch(set_texture_desc)(struct panvk_descriptor_set *set,
|
|||
{
|
||||
VK_FROM_HANDLE(panvk_image_view, view, pImageInfo->imageView);
|
||||
|
||||
#if PAN_ARCH > 5
|
||||
memcpy(&((struct mali_bifrost_texture_packed *)set->textures)[idx],
|
||||
#if PAN_ARCH >= 6
|
||||
memcpy(&((struct mali_texture_packed *)set->textures)[idx],
|
||||
view->descs.tex, pan_size(TEXTURE));
|
||||
#else
|
||||
((mali_ptr *)set->textures)[idx] = view->bo->ptr.gpu;
|
||||
|
|
@ -218,7 +218,7 @@ panvk_per_arch(write_descriptor_set)(struct panvk_device *dev,
|
|||
unsigned dest_offset = pDescriptorWrite->dstArrayElement;
|
||||
unsigned binding = pDescriptorWrite->dstBinding;
|
||||
struct mali_uniform_buffer_packed *ubos = set->ubos;
|
||||
struct mali_midgard_sampler_packed *samplers = set->samplers;
|
||||
struct mali_sampler_packed *samplers = set->samplers;
|
||||
unsigned src_offset = 0;
|
||||
|
||||
while (src_offset < pDescriptorWrite->descriptorCount &&
|
||||
|
|
|
|||
|
|
@ -58,10 +58,10 @@ panvk_queue_submit_batch(struct panvk_queue *queue,
|
|||
}
|
||||
#else
|
||||
if (batch->fb.desc.cpu) {
|
||||
void *tiler = pan_section_ptr(batch->fb.desc.cpu, MULTI_TARGET_FRAMEBUFFER, TILER);
|
||||
void *tiler = pan_section_ptr(batch->fb.desc.cpu, FRAMEBUFFER, TILER);
|
||||
memcpy(tiler, batch->tiler.templ, pan_size(TILER_CONTEXT));
|
||||
/* All weights set to 0, nothing to do here */
|
||||
pan_section_pack(batch->fb.desc.cpu, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS, w);
|
||||
pan_section_pack(batch->fb.desc.cpu, FRAMEBUFFER, TILER_WEIGHTS, w);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -115,16 +115,16 @@ panvk_meta_clear_attachments_emit_rsd(struct panfrost_device *pdev,
|
|||
cfg.stencil_back = cfg.stencil_front;
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_kill = true;
|
||||
cfg.properties.bifrost.zs_update_operation =
|
||||
cfg.properties.allow_forward_pixel_to_be_killed = true;
|
||||
cfg.properties.allow_forward_pixel_to_kill = true;
|
||||
cfg.properties.zs_update_operation =
|
||||
MALI_PIXEL_KILL_STRONG_EARLY;
|
||||
cfg.properties.bifrost.pixel_kill_operation =
|
||||
cfg.properties.pixel_kill_operation =
|
||||
MALI_PIXEL_KILL_FORCE_EARLY;
|
||||
#else
|
||||
cfg.properties.midgard.shader_reads_tilebuffer = false;
|
||||
cfg.properties.midgard.work_register_count = shader_info->work_reg_count;
|
||||
cfg.properties.midgard.force_early_z = true;
|
||||
cfg.properties.shader_reads_tilebuffer = false;
|
||||
cfg.properties.work_register_count = shader_info->work_reg_count;
|
||||
cfg.properties.force_early_z = true;
|
||||
cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -132,28 +132,22 @@ panvk_meta_clear_attachments_emit_rsd(struct panfrost_device *pdev,
|
|||
pan_pack(rsd_ptr.cpu + pan_size(RENDERER_STATE), BLEND, cfg) {
|
||||
cfg.round_to_fb_precision = true;
|
||||
cfg.load_destination = false;
|
||||
cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OPAQUE;
|
||||
cfg.bifrost.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.bifrost.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.bifrost.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.bifrost.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.bifrost.equation.color_mask = 0xf;
|
||||
cfg.bifrost.internal.fixed_function.num_comps = 4;
|
||||
cfg.bifrost.internal.fixed_function.conversion.memory_format =
|
||||
cfg.internal.mode = MALI_BLEND_MODE_OPAQUE;
|
||||
cfg.equation.color_mask = 0xf;
|
||||
cfg.internal.fixed_function.num_comps = 4;
|
||||
cfg.internal.fixed_function.conversion.memory_format =
|
||||
panfrost_format_to_bifrost_blend(pdev, format, false);
|
||||
cfg.bifrost.internal.fixed_function.conversion.register_format =
|
||||
cfg.internal.fixed_function.conversion.register_format =
|
||||
shader_info->bifrost.blend[rt].format;
|
||||
#else
|
||||
cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.midgard.equation.color_mask =
|
||||
cfg.equation.color_mask =
|
||||
(1 << util_format_get_nr_components(format)) - 1;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -214,7 +208,6 @@ panvk_meta_clear_attachment_emit_dcd(struct pan_pool *pool,
|
|||
cfg.push_uniforms = push_constants;
|
||||
cfg.position = coords;
|
||||
cfg.viewport = vpd;
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -141,7 +141,6 @@ panvk_meta_copy_emit_dcd(struct pan_pool *pool,
|
|||
&cfg.varyings);
|
||||
}
|
||||
cfg.viewport = vpd;
|
||||
cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
|
||||
cfg.textures = texture;
|
||||
cfg.samplers = sampler;
|
||||
}
|
||||
|
|
@ -218,8 +217,6 @@ panvk_meta_copy_emit_compute_job(struct pan_pool *desc_pool,
|
|||
0, tsd, rsd, ubo, push_constants,
|
||||
pan_section_ptr(job.cpu, COMPUTE_JOB, DRAW));
|
||||
|
||||
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
|
||||
|
||||
panfrost_add_job(desc_pool, scoreboard, MALI_JOB_TYPE_COMPUTE,
|
||||
false, false, 0, 0, &job, false);
|
||||
return job;
|
||||
|
|
@ -278,17 +275,17 @@ panvk_meta_copy_to_img_emit_rsd(struct panfrost_device *pdev,
|
|||
cfg.stencil_back = cfg.stencil_front;
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
|
||||
cfg.properties.bifrost.allow_forward_pixel_to_kill =
|
||||
cfg.properties.allow_forward_pixel_to_be_killed = true;
|
||||
cfg.properties.allow_forward_pixel_to_kill =
|
||||
!partialwrite && !readstb;
|
||||
cfg.properties.bifrost.zs_update_operation =
|
||||
cfg.properties.zs_update_operation =
|
||||
MALI_PIXEL_KILL_STRONG_EARLY;
|
||||
cfg.properties.bifrost.pixel_kill_operation =
|
||||
cfg.properties.pixel_kill_operation =
|
||||
MALI_PIXEL_KILL_FORCE_EARLY;
|
||||
#else
|
||||
cfg.properties.midgard.shader_reads_tilebuffer = readstb;
|
||||
cfg.properties.midgard.work_register_count = shader_info->work_reg_count;
|
||||
cfg.properties.midgard.force_early_z = true;
|
||||
cfg.properties.shader_reads_tilebuffer = readstb;
|
||||
cfg.properties.work_register_count = shader_info->work_reg_count;
|
||||
cfg.properties.force_early_z = true;
|
||||
cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -296,42 +293,36 @@ panvk_meta_copy_to_img_emit_rsd(struct panfrost_device *pdev,
|
|||
pan_pack(rsd_ptr.cpu + pan_size(RENDERER_STATE), BLEND, cfg) {
|
||||
cfg.round_to_fb_precision = true;
|
||||
cfg.load_destination = partialwrite;
|
||||
cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
#if PAN_ARCH >= 6
|
||||
cfg.bifrost.internal.mode =
|
||||
cfg.internal.mode =
|
||||
partialwrite ?
|
||||
MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION :
|
||||
MALI_BIFROST_BLEND_MODE_OPAQUE;
|
||||
cfg.bifrost.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.bifrost.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.bifrost.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.bifrost.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.bifrost.equation.color_mask = partialwrite ? wrmask : 0xf;
|
||||
cfg.bifrost.internal.fixed_function.num_comps = 4;
|
||||
MALI_BLEND_MODE_FIXED_FUNCTION :
|
||||
MALI_BLEND_MODE_OPAQUE;
|
||||
cfg.equation.color_mask = partialwrite ? wrmask : 0xf;
|
||||
cfg.internal.fixed_function.num_comps = 4;
|
||||
if (!raw) {
|
||||
cfg.bifrost.internal.fixed_function.conversion.memory_format =
|
||||
cfg.internal.fixed_function.conversion.memory_format =
|
||||
panfrost_format_to_bifrost_blend(pdev, fmt, false);
|
||||
cfg.bifrost.internal.fixed_function.conversion.register_format =
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
|
||||
cfg.internal.fixed_function.conversion.register_format =
|
||||
MALI_REGISTER_FILE_FORMAT_F32;
|
||||
} else {
|
||||
unsigned imgtexelsz = util_format_get_blocksize(fmt);
|
||||
|
||||
cfg.bifrost.internal.fixed_function.conversion.memory_format =
|
||||
cfg.internal.fixed_function.conversion.memory_format =
|
||||
panvk_meta_copy_img_bifrost_raw_format(imgtexelsz);
|
||||
cfg.bifrost.internal.fixed_function.conversion.register_format =
|
||||
cfg.internal.fixed_function.conversion.register_format =
|
||||
(imgtexelsz & 2) ?
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U16 :
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
MALI_REGISTER_FILE_FORMAT_U16 :
|
||||
MALI_REGISTER_FILE_FORMAT_U32;
|
||||
}
|
||||
#else
|
||||
cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
|
||||
cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
|
||||
cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
|
||||
cfg.midgard.equation.color_mask = wrmask;
|
||||
cfg.equation.color_mask = wrmask;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -540,11 +531,11 @@ panvk_meta_copy_img2img_shader(struct panfrost_device *pdev,
|
|||
};
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
pan_pack(&inputs.bifrost.rt_conv[0], BIFROST_INTERNAL_CONVERSION, cfg) {
|
||||
pan_pack(&inputs.bifrost.rt_conv[0], INTERNAL_CONVERSION, cfg) {
|
||||
cfg.memory_format = (dstcompsz == 2 ? MALI_RG16UI : MALI_RG32UI) << 12;
|
||||
cfg.register_format = dstcompsz == 2 ?
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U16 :
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
MALI_REGISTER_FILE_FORMAT_U16 :
|
||||
MALI_REGISTER_FILE_FORMAT_U32;
|
||||
}
|
||||
inputs.bifrost.static_rt_conv = true;
|
||||
#endif
|
||||
|
|
@ -1093,11 +1084,11 @@ panvk_meta_copy_buf2img_shader(struct panfrost_device *pdev,
|
|||
};
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
pan_pack(&inputs.bifrost.rt_conv[0], BIFROST_INTERNAL_CONVERSION, cfg) {
|
||||
pan_pack(&inputs.bifrost.rt_conv[0], INTERNAL_CONVERSION, cfg) {
|
||||
cfg.memory_format = (imgcompsz == 2 ? MALI_RG16UI : MALI_RG32UI) << 12;
|
||||
cfg.register_format = imgcompsz == 2 ?
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U16 :
|
||||
MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
|
||||
MALI_REGISTER_FILE_FORMAT_U16 :
|
||||
MALI_REGISTER_FILE_FORMAT_U32;
|
||||
}
|
||||
inputs.bifrost.static_rt_conv = true;
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue