diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index 2ee61207dfa..4d0ba99a6a3 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -579,7 +579,7 @@ get_copy_region_aux_settings(struct iris_context *ice, * for adjusting the clear color, so clear support may only be enabled * in some cases: * - * - On gen11+, the clear color is indirect and comes in two forms: a + * - On gfx11+, the clear color is indirect and comes in two forms: a * 32bpc representation used for rendering and a pixel representation * used for sampling. blorp_copy doesn't change indirect clear colors, * so clears are only supported in the sampling case. diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index 9b84500a565..dbc47e63503 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -1860,7 +1860,7 @@ iris_bufmgr_create(struct gen_device_info *devinfo, int fd, bool bo_reuse) util_vma_heap_init(&bufmgr->vma_allocator[IRIS_MEMZONE_SURFACE], IRIS_MEMZONE_SURFACE_START, _4GB_minus_1 - IRIS_MAX_BINDERS * IRIS_BINDER_SIZE); - /* TODO: Why does limiting to 2GB help some state items on gen12? + /* TODO: Why does limiting to 2GB help some state items on gfx12? * - CC Viewport Pointer * - Blend State Pointer * - Color Calc State Pointer diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c index da010d5c627..493632893ce 100644 --- a/src/gallium/drivers/iris/iris_context.c +++ b/src/gallium/drivers/iris/iris_context.c @@ -256,19 +256,19 @@ iris_destroy_context(struct pipe_context *ctx) #define genX_call(devinfo, func, ...) \ switch ((devinfo)->verx10) { \ case 125: \ - gen125_##func(__VA_ARGS__); \ + gfx125_##func(__VA_ARGS__); \ break; \ case 120: \ - gen12_##func(__VA_ARGS__); \ + gfx12_##func(__VA_ARGS__); \ break; \ case 110: \ - gen11_##func(__VA_ARGS__); \ + gfx11_##func(__VA_ARGS__); \ break; \ case 90: \ - gen9_##func(__VA_ARGS__); \ + gfx9_##func(__VA_ARGS__); \ break; \ case 80: \ - gen8_##func(__VA_ARGS__); \ + gfx8_##func(__VA_ARGS__); \ break; \ default: \ unreachable("Unknown hardware generation"); \ diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 94197469f5e..a7dde354c72 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -993,7 +993,7 @@ int iris_get_driver_query_group_info(struct pipe_screen *pscreen, struct pipe_driver_query_group_info *info); /* iris_state.c */ -void gen9_toggle_preemption(struct iris_context *ice, +void gfx9_toggle_preemption(struct iris_context *ice, struct iris_batch *batch, const struct pipe_draw_info *draw); @@ -1002,34 +1002,34 @@ void gen9_toggle_preemption(struct iris_context *ice, #ifdef genX # include "iris_genx_protos.h" #else -# define genX(x) gen4_##x +# define genX(x) gfx4_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen5_##x +# define genX(x) gfx5_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen6_##x +# define genX(x) gfx6_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen7_##x +# define genX(x) gfx7_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen75_##x +# define genX(x) gfx75_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen8_##x +# define genX(x) gfx8_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen9_##x +# define genX(x) gfx9_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen11_##x +# define genX(x) gfx11_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen12_##x +# define genX(x) gfx12_##x # include "iris_genx_protos.h" # undef genX -# define genX(x) gen125_##x +# define genX(x) gfx125_##x # include "iris_genx_protos.h" # undef genX #endif diff --git a/src/gallium/drivers/iris/iris_defines.h b/src/gallium/drivers/iris/iris_defines.h index ca103927800..fce73551670 100644 --- a/src/gallium/drivers/iris/iris_defines.h +++ b/src/gallium/drivers/iris/iris_defines.h @@ -55,7 +55,7 @@ /* The number of bits in our TIMESTAMP queries. */ #define TIMESTAMP_BITS 36 -/* For gen12 we set the streamout buffers using 4 separate commands +/* For gfx12 we set the streamout buffers using 4 separate commands * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c index 6a6a601bdfa..f1502703f62 100644 --- a/src/gallium/drivers/iris/iris_draw.c +++ b/src/gallium/drivers/iris/iris_draw.c @@ -268,7 +268,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info, iris_update_draw_info(ice, info); if (devinfo->ver == 9) - gen9_toggle_preemption(ice, batch, info); + gfx9_toggle_preemption(ice, batch, info); iris_update_compiled_shaders(ice); diff --git a/src/gallium/drivers/iris/iris_formats.c b/src/gallium/drivers/iris/iris_formats.c index 2a327a6ba4e..74f04ccb6ab 100644 --- a/src/gallium/drivers/iris/iris_formats.c +++ b/src/gallium/drivers/iris/iris_formats.c @@ -210,7 +210,7 @@ iris_is_format_supported(struct pipe_screen *pscreen, } /* TODO: Support ASTC 5x5 on Gen9 properly. This means implementing - * a complex sampler workaround (see i965's gen9_apply_astc5x5_wa_flush). + * a complex sampler workaround (see i965's gfx9_apply_astc5x5_wa_flush). * Without it, st/mesa will emulate ASTC 5x5 via uncompressed textures. */ if (devinfo->ver == 9 && (format == ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 || diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 97adecb814d..55a68eab4f2 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -351,7 +351,7 @@ iris_cache_flush_for_render(struct iris_batch *batch, * * Even though it's not obvious, this can easily happen in practice. * Suppose a client is blending on a surface with sRGB encode enabled on - * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client + * gfx9. This implies that you get AUX_USAGE_CCS_D at best. If the client * then disables sRGB decode and continues blending we will flip on * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is * perfectly valid since CCS_E is a subset of CCS_D). However, this means @@ -897,11 +897,11 @@ iris_image_view_aux_usage(struct iris_context *ice, static bool isl_formats_are_fast_clear_compatible(enum isl_format a, enum isl_format b) { - /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear + /* On gfx8 and earlier, the hardware was only capable of handling 0/1 clear * values so sRGB curve application was a no-op for all fast-clearable * formats. * - * On gen9+, the hardware supports arbitrary clear values. For sRGB clear + * On gfx9+, the hardware supports arbitrary clear values. For sRGB clear * values, the hardware interprets the floats, not as what would be * returned from the sampler (or written by the shader), but as being * between format conversion and sRGB curve application. This means that @@ -985,7 +985,7 @@ iris_resource_render_aux_usage(struct iris_context *ice, case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: case ISL_AUX_USAGE_GEN12_CCS_E: - /* Disable CCS for some cases of texture-view rendering. On gen12, HW + /* Disable CCS for some cases of texture-view rendering. On gfx12, HW * may convert some subregions of shader output to fast-cleared blocks * if CCS is enabled and the shader output matches the clear color. * Existing fast-cleared blocks are correctly interpreted by the clear diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index ca9fdfb2815..68751dca362 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -61,19 +61,19 @@ #define genX_call(devinfo, func, ...) \ switch ((devinfo)->verx10) { \ case 125: \ - gen125_##func(__VA_ARGS__); \ + gfx125_##func(__VA_ARGS__); \ break; \ case 120: \ - gen12_##func(__VA_ARGS__); \ + gfx12_##func(__VA_ARGS__); \ break; \ case 110: \ - gen11_##func(__VA_ARGS__); \ + gfx11_##func(__VA_ARGS__); \ break; \ case 90: \ - gen9_##func(__VA_ARGS__); \ + gfx9_##func(__VA_ARGS__); \ break; \ case 80: \ - gen8_##func(__VA_ARGS__); \ + gfx8_##func(__VA_ARGS__); \ break; \ default: \ unreachable("Unknown hardware generation"); \ diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 1b55e50ebae..497aae70fdd 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -836,7 +836,7 @@ calculate_pixel_hashing_table(unsigned n, unsigned m, #if GFX_VER == 11 static void -gen11_upload_pixel_hashing_tables(struct iris_batch *batch) +gfx11_upload_pixel_hashing_tables(struct iris_batch *batch) { const struct gen_device_info *devinfo = &batch->screen->devinfo; assert(devinfo->ppipe_subslices[2] == 0); @@ -872,7 +872,7 @@ gen11_upload_pixel_hashing_tables(struct iris_batch *batch) } #elif GFX_VERx10 == 120 static void -gen12_upload_pixel_hashing_tables(struct iris_batch *batch) +gfx12_upload_pixel_hashing_tables(struct iris_batch *batch) { const struct gen_device_info *devinfo = &batch->screen->devinfo; /* For each n calculate ppipes_of[n], equal to the number of pixel pipes @@ -1033,11 +1033,11 @@ iris_init_render_context(struct iris_batch *batch) } } - gen11_upload_pixel_hashing_tables(batch); + gfx11_upload_pixel_hashing_tables(batch); #endif #if GFX_VERx10 == 120 - gen12_upload_pixel_hashing_tables(batch); + gfx12_upload_pixel_hashing_tables(batch); #endif /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid @@ -2787,7 +2787,7 @@ iris_set_shader_images(struct pipe_context *ctx, enum isl_format isl_fmt = iris_image_view_get_format(ice, img); - /* Render compression with images supported on gen12+ only. */ + /* Render compression with images supported on gfx12+ only. */ unsigned aux_usages = GFX_VER >= 12 ? res->aux.possible_usages : 1 << ISL_AUX_USAGE_NONE; @@ -4581,7 +4581,7 @@ iris_store_cs_state(const struct gen_device_info *devinfo, * preemption. * * We still have issues with mid-thread preemption (it was already - * disabled by the kernel on gen11, due to missing workarounds). It's + * disabled by the kernel on gfx11, due to missing workarounds). It's * possible that we are just missing some workarounds, and could enable * it later, but for now let's disable it to fix a GPU in compute in Car * Chase (and possibly more). @@ -4745,8 +4745,8 @@ update_clear_value(struct iris_context *ice, UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev; UNUSED unsigned aux_modes = all_aux_modes; - /* We only need to update the clear color in the surface state for gen8 and - * gen9. Newer gens can read it directly from the clear color state buffer. + /* We only need to update the clear color in the surface state for gfx8 and + * gfx9. Newer gens can read it directly from the clear color state buffer. */ #if GFX_VER == 9 /* Skip updating the ISL_AUX_USAGE_NONE surface state */ @@ -6824,7 +6824,7 @@ iris_upload_compute_walker(struct iris_context *ice, if (stage_dirty & IRIS_STAGE_DIRTY_CS) { iris_emit_cmd(batch, GENX(CFE_STATE), cfe) { - /* TODO: Enable gen12-hp scratch support*/ + /* TODO: Enable gfx12-hp scratch support*/ assert(prog_data->total_scratch == 0); cfe.MaximumNumberofThreads = @@ -7802,7 +7802,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * We don't put this in the vtable because it's only used on Gen9. */ void -gen9_toggle_preemption(struct iris_context *ice, +gfx9_toggle_preemption(struct iris_context *ice, struct iris_batch *batch, const struct pipe_draw_info *draw) { diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index a265fdc5842..81ced17e27d 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/intel/Android.vulkan.mk @@ -239,10 +239,10 @@ LOCAL_GENERATED_SOURCES := $(addprefix $(intermediates)/,$(VULKAN_GENERATED_FILE ANV_VK_ENTRYPOINTS_GEN_ARGS= \ --proto --weak --prefix anv \ - --device-prefix gen7 --device-prefix gen75 \ - --device-prefix gen8 --device-prefix gen9 \ - --device-prefix gen11 --device-prefix gen12 \ - --device-prefix gen125 + --device-prefix gfx7 --device-prefix gfx75 \ + --device-prefix gfx8 --device-prefix gfx9 \ + --device-prefix gfx11 --device-prefix gfx12 \ + --device-prefix gfx125 $(intermediates)/vulkan/anv_entrypoints.c: $(VK_ENTRYPOINTS_GEN_SCRIPT) \ $(VULKAN_API_XML) diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 6c1b9ad613f..46433ebd294 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -39,7 +39,7 @@ blorp_shader_type_to_name(enum blorp_shader_type type) [BLORP_SHADER_TYPE_CLEAR] = "BLORP-clear", [BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE] = "BLORP-mcs-partial-resolve", [BLORP_SHADER_TYPE_LAYER_OFFSET_VS] = "BLORP-layer-offset-vs", - [BLORP_SHADER_TYPE_GEN4_SF] = "BLORP-gen4-sf", + [BLORP_SHADER_TYPE_GEN4_SF] = "BLORP-gfx4-sf", }; assert(type < ARRAY_SIZE(shader_name)); diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h index dd0d4c8ce13..41272617d48 100644 --- a/src/intel/blorp/blorp.h +++ b/src/intel/blorp/blorp.h @@ -110,7 +110,7 @@ struct blorp_surf /** * If set (bo != NULL), clear_color is ignored and the actual clear color - * is fetched from this address. On gen7-8, this is all of dword 7 of + * is fetched from this address. On gfx7-8, this is all of dword 7 of * RENDER_SURFACE_STATE and is the responsibility of the caller to ensure * that it contains a swizzle of RGBA and resource min LOD of 0. */ @@ -205,7 +205,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch, void -blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch, +blorp_gfx8_hiz_clear_attachments(struct blorp_batch *batch, uint32_t num_samples, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index a615b627ebe..e14d55c5bbe 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1361,7 +1361,7 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx, src_pos = nir_f2i32(&b, nir_channels(&b, src_pos, 0x3)); if (devinfo->ver == 6) { - /* Because gen6 only supports 4x interleved MSAA, we can do all the + /* Because gfx6 only supports 4x interleved MSAA, we can do all the * blending we need with a single linear-interpolated texture lookup * at the center of the sample. The texture coordinates to be odd * integers so that they correspond to the center of a 2x2 block @@ -1637,10 +1637,10 @@ blorp_surf_retile_w_to_y(const struct isl_device *isl_dev, /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */ blorp_surf_convert_to_single_slice(isl_dev, info); - /* On gen7+, we don't have interleaved multisampling for color render + /* On gfx7+, we don't have interleaved multisampling for color render * targets so we have to fake it. * - * TODO: Are we sure we don't also need to fake it on gen6? + * TODO: Are we sure we don't also need to fake it on gfx6? */ if (isl_dev->info->ver > 6 && info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { @@ -1868,7 +1868,7 @@ try_blorp_blit(struct blorp_batch *batch, if (devinfo->ver == 4) { /* The MinLOD and MinimumArrayElement don't work properly for cube maps. - * Convert them to a single slice on gen4. + * Convert them to a single slice on gfx4. */ if (params->dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT) { blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, ¶ms->dst); diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 5984e49395d..4858aa9c063 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -435,7 +435,7 @@ blorp_clear(struct blorp_batch *batch, if (surf->surf->tiling == ISL_TILING_LINEAR) use_simd16_replicated_data = false; - /* Replicated clears don't work yet before gen6 */ + /* Replicated clears don't work yet before gfx6 */ if (batch->blorp->isl_dev->info->ver < 6) use_simd16_replicated_data = false; @@ -478,7 +478,7 @@ blorp_clear(struct blorp_batch *batch, } /* The MinLOD and MinimumArrayElement don't work properly for cube maps. - * Convert them to a single slice on gen4. + * Convert them to a single slice on gfx4. */ if (batch->blorp->isl_dev->info->ver == 4 && (params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) { @@ -498,7 +498,7 @@ blorp_clear(struct blorp_batch *batch, } if (params.dst.tile_x_sa || params.dst.tile_y_sa) { - /* Either we're on gen4 where there is no multisampling or the + /* Either we're on gfx4 where there is no multisampling or the * surface is compressed which also implies no multisampling. * Therefore, sa == px and we don't need to do a conversion. */ @@ -762,7 +762,7 @@ blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo, uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) { - /* This function currently doesn't support any gen prior to gen8 */ + /* This function currently doesn't support any gen prior to gfx8 */ assert(devinfo->ver >= 8); if (devinfo->ver == 8 && surf->format == ISL_FORMAT_R16_UNORM) { @@ -895,7 +895,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch, blorp_params_init(¶ms); params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR; - /* This requires WM_HZ_OP which only exists on gen8+ */ + /* This requires WM_HZ_OP which only exists on gfx8+ */ assert(ISL_GFX_VER(batch->blorp->isl_dev) >= 8); params.hiz_op = ISL_AUX_OP_FAST_CLEAR; @@ -948,7 +948,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch, * tagged as cleared so the depth clear value is not actually needed. */ void -blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch, +blorp_gfx8_hiz_clear_attachments(struct blorp_batch *batch, uint32_t num_samples, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, @@ -1273,7 +1273,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch, uint32_t level, uint32_t layer) { if (ISL_GFX_VER(batch->blorp->isl_dev) >= 10) { - /* On gen10 and above, we have a hardware resolve op for this */ + /* On gfx10 and above, we have a hardware resolve op for this */ return blorp_ccs_resolve(batch, surf, level, layer, 1, surf->surf->format, ISL_AUX_OP_AMBIGUATE); } @@ -1366,7 +1366,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch, width_cl = DIV_ROUND_UP(width_el, x_el_per_cl); height_cl = DIV_ROUND_UP(height_el, y_el_per_cl); } else { - /* On gen7, the CCS tiling is not so nice. However, there we are + /* On gfx7, the CCS tiling is not so nice. However, there we are * guaranteed that we only have a single level and slice so we don't * have to worry about it and can just align to a whole tile. */ diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 0a1b5221ccc..ae82d60f906 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -653,7 +653,7 @@ blorp_emit_sampler_state(struct blorp_batch *batch) } /* What follows is the code for setting up a "pipeline" on Sandy Bridge and - * later hardware. This file will be included by i965 for gen4-5 as well, so + * later hardware. This file will be included by i965 for gfx4-5 as well, so * this code is guarded by GFX_VER >= 6. */ #if GFX_VER >= 6 @@ -861,7 +861,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, } /* 3DSTATE_PS expects the number of threads per PSD, which is always 64 - * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is + * for pre Gen11 and 128 for gfx11+; On gfx11+ If a programmed value is * k, it implies 2(k+1) threads. It implicitly scales for different GT * levels (which have some # of PSDs). * @@ -1286,7 +1286,7 @@ blorp_emit_pipeline(struct blorp_batch *batch, * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE. * * The dynamic state emit helpers emit their own STATE_POINTERS packets on - * gen7+. However, on gen6 and earlier, they're all lumpped together in + * gfx7+. However, on gfx6 and earlier, they're all lumpped together in * one CC_STATE_POINTERS packet so we have to emit that here. */ blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), cc) { @@ -1427,7 +1427,7 @@ blorp_emit_surface_state(struct blorp_batch *batch, enum isl_aux_usage aux_usage = surface->aux_usage; - /* On gen12, implicit CCS has no aux buffer */ + /* On gfx12, implicit CCS has no aux buffer */ bool use_aux_address = (aux_usage != ISL_AUX_USAGE_NONE) && (surface->aux_addr.buffer != NULL); @@ -1465,7 +1465,7 @@ blorp_emit_surface_state(struct blorp_batch *batch, surface->addr, 0); if (use_aux_address) { - /* On gen7 and prior, the bottom 12 bits of the MCS base address are + /* On gfx7 and prior, the bottom 12 bits of the MCS base address are * used to store other information. This should be ok, however, because * surface buffer addresses are always 4K page alinged. */ @@ -1493,7 +1493,7 @@ blorp_emit_surface_state(struct blorp_batch *batch, isl_dev->ss.clear_value_size); } #else - unreachable("Fast clears are only supported on gen7+"); + unreachable("Fast clears are only supported on gfx7+"); #endif } @@ -1718,7 +1718,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, * clearing operations without such information. * */ static void -blorp_emit_gen8_hiz_op(struct blorp_batch *batch, +blorp_emit_gfx8_hiz_op(struct blorp_batch *batch, const struct blorp_params *params) { /* We should be performing an operation on a depth or stencil buffer. @@ -1966,7 +1966,7 @@ blorp_exec(struct blorp_batch *batch, const struct blorp_params *params) #if GFX_VER >= 8 if (params->hiz_op != ISL_AUX_OP_NONE) { - blorp_emit_gen8_hiz_op(batch, params); + blorp_emit_gfx8_hiz_op(batch, params); return; } #endif diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h index 3d1d984a2fd..c55dea70625 100644 --- a/src/intel/blorp/blorp_priv.h +++ b/src/intel/blorp/blorp_priv.h @@ -359,7 +359,7 @@ struct brw_blorp_blit_prog_key * \name BLORP internals * \{ * - * Used internally by gen6_blorp_exec() and gen7_blorp_exec(). + * Used internally by gfx6_blorp_exec() and gfx7_blorp_exec(). */ void brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key); diff --git a/src/intel/common/intel_batch_decoder.c b/src/intel/common/intel_batch_decoder.c index 458ceb0f33d..886d31e040c 100644 --- a/src/intel/common/intel_batch_decoder.c +++ b/src/intel/common/intel_batch_decoder.c @@ -749,7 +749,7 @@ decode_3dstate_constant(struct intel_batch_decode_ctx *ctx, const uint32_t *p) } static void -decode_gen6_3dstate_binding_table_pointers(struct intel_batch_decode_ctx *ctx, +decode_gfx6_3dstate_binding_table_pointers(struct intel_batch_decode_ctx *ctx, const uint32_t *p) { fprintf(ctx->fp, "VS Binding Table:\n"); @@ -777,7 +777,7 @@ decode_3dstate_sampler_state_pointers(struct intel_batch_decode_ctx *ctx, } static void -decode_3dstate_sampler_state_pointers_gen6(struct intel_batch_decode_ctx *ctx, +decode_3dstate_sampler_state_pointers_gfx6(struct intel_batch_decode_ctx *ctx, const uint32_t *p) { dump_samplers(ctx, p[1], 1); @@ -1136,7 +1136,7 @@ struct custom_decoder { { "3DSTATE_CONSTANT_DS", decode_3dstate_constant }, { "3DSTATE_CONSTANT_ALL", decode_3dstate_constant_all }, - { "3DSTATE_BINDING_TABLE_POINTERS", decode_gen6_3dstate_binding_table_pointers }, + { "3DSTATE_BINDING_TABLE_POINTERS", decode_gfx6_3dstate_binding_table_pointers }, { "3DSTATE_BINDING_TABLE_POINTERS_VS", decode_3dstate_binding_table_pointers }, { "3DSTATE_BINDING_TABLE_POINTERS_HS", decode_3dstate_binding_table_pointers }, { "3DSTATE_BINDING_TABLE_POINTERS_DS", decode_3dstate_binding_table_pointers }, @@ -1148,7 +1148,7 @@ struct custom_decoder { { "3DSTATE_SAMPLER_STATE_POINTERS_DS", decode_3dstate_sampler_state_pointers }, { "3DSTATE_SAMPLER_STATE_POINTERS_GS", decode_3dstate_sampler_state_pointers }, { "3DSTATE_SAMPLER_STATE_POINTERS_PS", decode_3dstate_sampler_state_pointers }, - { "3DSTATE_SAMPLER_STATE_POINTERS", decode_3dstate_sampler_state_pointers_gen6 }, + { "3DSTATE_SAMPLER_STATE_POINTERS", decode_3dstate_sampler_state_pointers_gfx6 }, { "3DSTATE_VIEWPORT_STATE_POINTERS_CC", decode_3dstate_viewport_state_pointers_cc }, { "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", decode_3dstate_viewport_state_pointers_sf_clip }, diff --git a/src/intel/common/intel_l3_config.c b/src/intel/common/intel_l3_config.c index 51f14c23ce0..049f1e8815b 100644 --- a/src/intel/common/intel_l3_config.c +++ b/src/intel/common/intel_l3_config.c @@ -40,7 +40,7 @@ struct intel_l3_list { /** * IVB/HSW validated L3 configurations. The first entry will be used as - * default by gen7_restore_default_l3_config(), otherwise the ordering is + * default by gfx7_restore_default_l3_config(), otherwise the ordering is * unimportant. */ static const struct intel_l3_config ivb_l3_configs[] = { diff --git a/src/intel/common/tests/mi_builder_test.cpp b/src/intel/common/tests/mi_builder_test.cpp index aad4f6cc358..bc5ed6b7e59 100644 --- a/src/intel/common/tests/mi_builder_test.cpp +++ b/src/intel/common/tests/mi_builder_test.cpp @@ -213,7 +213,7 @@ mi_builder_test::SetUp() ctx_id = ctx_create.ctx_id; if (GFX_VER >= 8) { - /* On gen8+, we require softpin */ + /* On gfx8+, we require softpin */ int has_softpin; drm_i915_getparam getparam = drm_i915_getparam(); getparam.param = I915_PARAM_HAS_EXEC_SOFTPIN; @@ -309,7 +309,7 @@ mi_builder_test::submit_batch() objects[0].handle = data_bo_handle; objects[0].relocation_count = 0; objects[0].relocs_ptr = 0; -#if GFX_VER >= 8 /* On gen8+, we pin everything */ +#if GFX_VER >= 8 /* On gfx8+, we pin everything */ objects[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE; @@ -320,7 +320,7 @@ mi_builder_test::submit_batch() #endif objects[1].handle = batch_bo_handle; -#if GFX_VER >= 8 /* On gen8+, we don't use relocations */ +#if GFX_VER >= 8 /* On gfx8+, we don't use relocations */ objects[1].relocation_count = 0; objects[1].relocs_ptr = 0; objects[1].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | diff --git a/src/intel/compiler/brw_compile_sf.c b/src/intel/compiler/brw_compile_sf.c index b4062b0e178..b0dc0d5235c 100644 --- a/src/intel/compiler/brw_compile_sf.c +++ b/src/intel/compiler/brw_compile_sf.c @@ -345,7 +345,7 @@ static void invert_det( struct brw_sf_compile *c) /* Looks like we invert all 8 elements just to get 1/det in * position 2 !?! */ - gen4_math(&c->func, + gfx4_math(&c->func, c->inv_det, BRW_MATH_FUNCTION_INV, 0, @@ -633,7 +633,7 @@ static void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate) if (pc_coord_replace) { set_predicate_control_flag_value(p, c, pc_coord_replace); /* Caculate 1.0/PointWidth */ - gen4_math(&c->func, + gfx4_math(&c->func, c->tmp, BRW_MATH_FUNCTION_INV, 0, diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 23e62dec187..bcbde3b6e10 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -179,7 +179,7 @@ brw_shader_stage_is_bindless(gl_shader_stage stage) * @{ */ -enum PACKED gen6_gather_sampler_wa { +enum PACKED gfx6_gather_sampler_wa { WA_SIGN = 1, /* whether we need to sign extend */ WA_8BIT = 2, /* if we have an 8bit format needing wa */ WA_16BIT = 4, /* if we have a 16bit format needing wa */ @@ -216,7 +216,7 @@ struct brw_sampler_prog_key_data { /** * For Sandybridge, which shader w/a we need for gather quirks. */ - enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS]; + enum gfx6_gather_sampler_wa gfx6_gather_wa[MAX_SAMPLERS]; /** * Texture units that have a YUV image bound. @@ -575,7 +575,7 @@ struct brw_image_param { #define BRW_MAX_SOL_BINDINGS 64 /** - * Binding table index for the first gen6 SOL binding. + * Binding table index for the first gfx6 SOL binding. */ #define BRW_GEN6_SOL_BINDING_START 0 @@ -852,7 +852,7 @@ struct brw_wm_prog_data { /** * Mask of which interpolation modes are required by the fragment shader. - * Used in hardware setup on gen6+. + * Used in hardware setup on gfx6+. */ uint32_t barycentric_interp_modes; @@ -1054,8 +1054,8 @@ typedef enum /** * We always program SF to start reading at an offset of 1 (2 varying slots) * from the start of the vertex URB entry. This causes it to skip: - * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5 - * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+ + * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gfx4-5 + * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gfx6+ */ #define BRW_SF_URB_ENTRY_READ_OFFSET 1 diff --git a/src/intel/compiler/brw_debug_recompile.c b/src/intel/compiler/brw_debug_recompile.c index 8d561a2bded..d165cc1fe74 100644 --- a/src/intel/compiler/brw_debug_recompile.c +++ b/src/intel/compiler/brw_debug_recompile.c @@ -75,7 +75,7 @@ debug_sampler_recompile(const struct brw_compiler *c, void *log, for (unsigned i = 0; i < MAX_SAMPLERS; i++) { found |= check("EXT_texture_swizzle or DEPTH_TEXTURE_MODE", swizzles[i]); - found |= check("textureGather workarounds", gen6_gather_wa[i]); + found |= check("textureGather workarounds", gfx6_gather_wa[i]); found |= check_float("scale factor", scale_factors[i]); } diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 11f9cb7d254..4ea6440d7c1 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -289,7 +289,7 @@ static const char *const end_of_thread[2] = { }; /* SFIDs on Gen4-5 */ -static const char *const gen4_sfid[16] = { +static const char *const gfx4_sfid[16] = { [BRW_SFID_NULL] = "null", [BRW_SFID_MATH] = "math", [BRW_SFID_SAMPLER] = "sampler", @@ -301,7 +301,7 @@ static const char *const gen4_sfid[16] = { [BRW_SFID_VME] = "vme", }; -static const char *const gen6_sfid[16] = { +static const char *const gfx6_sfid[16] = { [BRW_SFID_NULL] = "null", [BRW_SFID_MATH] = "math", [BRW_SFID_SAMPLER] = "sampler", @@ -318,7 +318,7 @@ static const char *const gen6_sfid[16] = { [GEN_RT_SFID_RAY_TRACE_ACCELERATOR] = "rt accel", }; -static const char *const gen7_gateway_subfuncid[8] = { +static const char *const gfx7_gateway_subfuncid[8] = { [BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open", [BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close", [BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg", @@ -328,7 +328,7 @@ static const char *const gen7_gateway_subfuncid[8] = { [BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write", }; -static const char *const gen4_dp_read_port_msg_type[4] = { +static const char *const gfx4_dp_read_port_msg_type[4] = { [0b00] = "OWord Block Read", [0b01] = "OWord Dual Block Read", [0b10] = "Media Block Read", @@ -355,7 +355,7 @@ static const char *const dp_write_port_msg_type[8] = { [0b111] = "flush render cache", }; -static const char *const dp_rc_msg_type_gen6[16] = { +static const char *const dp_rc_msg_type_gfx6[16] = { [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read", [GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read", [GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read", @@ -375,7 +375,7 @@ static const char *const dp_rc_msg_type_gen6[16] = { [GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write", }; -static const char *const dp_rc_msg_type_gen7[16] = { +static const char *const dp_rc_msg_type_gfx7[16] = { [GFX7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read", [GFX7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read", [GFX7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op", @@ -385,7 +385,7 @@ static const char *const dp_rc_msg_type_gen7[16] = { [GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write" }; -static const char *const dp_rc_msg_type_gen9[16] = { +static const char *const dp_rc_msg_type_gfx9[16] = { [GFX9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write", [GFX9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read" }; @@ -393,9 +393,9 @@ static const char *const dp_rc_msg_type_gen9[16] = { static const char *const * dp_rc_msg_type(const struct gen_device_info *devinfo) { - return (devinfo->ver >= 9 ? dp_rc_msg_type_gen9 : - devinfo->ver >= 7 ? dp_rc_msg_type_gen7 : - devinfo->ver >= 6 ? dp_rc_msg_type_gen6 : + return (devinfo->ver >= 9 ? dp_rc_msg_type_gfx9 : + devinfo->ver >= 7 ? dp_rc_msg_type_gfx7 : + devinfo->ver >= 6 ? dp_rc_msg_type_gfx6 : dp_write_port_msg_type); } @@ -409,7 +409,7 @@ static const char *const m_rt_write_subtype[] = { [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */ }; -static const char *const dp_dc0_msg_type_gen7[16] = { +static const char *const dp_dc0_msg_type_gfx7[16] = { [GFX7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read", [GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] = "DC unaligned OWORD block read", @@ -535,12 +535,12 @@ static const char *const math_precision[2] = { [1] = "partial_precision" }; -static const char *const gen5_urb_opcode[] = { +static const char *const gfx5_urb_opcode[] = { [0] = "urb_write", [1] = "ff_sync", }; -static const char *const gen7_urb_opcode[] = { +static const char *const gfx7_urb_opcode[] = { [BRW_URB_OPCODE_WRITE_HWORD] = "write HWord", [BRW_URB_OPCODE_WRITE_OWORD] = "write OWord", [BRW_URB_OPCODE_READ_HWORD] = "read HWord", @@ -574,7 +574,7 @@ static const char *const urb_complete[2] = { [1] = "complete" }; -static const char *const gen5_sampler_msg_type[] = { +static const char *const gfx5_sampler_msg_type[] = { [GFX5_SAMPLER_MESSAGE_SAMPLE] = "sample", [GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b", [GFX5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l", @@ -600,7 +600,7 @@ static const char *const gen5_sampler_msg_type[] = { [GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss", }; -static const char *const gen5_sampler_simd_mode[4] = { +static const char *const gfx5_sampler_simd_mode[4] = { [BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2", [BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8", [BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16", @@ -1018,7 +1018,7 @@ src_da16(FILE *file, static enum brw_vertical_stride vstride_from_align1_3src_vstride(const struct gen_device_info *devinfo, - enum gen10_align1_3src_vertical_stride vstride) + enum gfx10_align1_3src_vertical_stride vstride) { switch (vstride) { case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0; @@ -1035,7 +1035,7 @@ vstride_from_align1_3src_vstride(const struct gen_device_info *devinfo, } static enum brw_horizontal_stride -hstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hstride) +hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride) { switch (hstride) { case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_HORIZONTAL_STRIDE_0; @@ -1048,7 +1048,7 @@ hstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hs } static enum brw_vertical_stride -vstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hstride) +vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride) { switch (hstride) { case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0; @@ -1732,7 +1732,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, brw_inst_cond_modifier(devinfo, inst), NULL); /* If we're using the conditional modifier, print which flags reg is - * used for it. Note that on gen6+, the embedded-condition SEL and + * used for it. Note that on gfx6+, the embedded-condition SEL and * control flow doesn't update flags. */ if (brw_inst_cond_modifier(devinfo, inst) && @@ -1770,7 +1770,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, if (devinfo->ver >= 7) { jip = brw_inst_jip(devinfo, inst); } else { - jip = brw_inst_gen6_jump_count(devinfo, inst); + jip = brw_inst_gfx6_jump_count(devinfo, inst); } pad(file, 16); @@ -1780,18 +1780,18 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, opcode == BRW_OPCODE_CONTINUE || opcode == BRW_OPCODE_ELSE)) { pad(file, 16); - format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst)); + format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst)); pad(file, 32); - format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst)); + format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst)); } else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_IF || opcode == BRW_OPCODE_IFF || opcode == BRW_OPCODE_HALT || opcode == BRW_OPCODE_WHILE)) { pad(file, 16); - format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst)); + format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst)); } else if (devinfo->ver < 6 && opcode == BRW_OPCODE_ENDIF) { pad(file, 16); - format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst)); + format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst)); } else if (opcode == BRW_OPCODE_JMPI) { pad(file, 16); err |= src1(file, devinfo, inst); @@ -1871,7 +1871,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, space = 0; fprintf(file, " "); - err |= control(file, "SFID", devinfo->ver >= 6 ? gen6_sfid : gen4_sfid, + err |= control(file, "SFID", devinfo->ver >= 6 ? gfx6_sfid : gfx4_sfid, sfid, &space); string(file, " MsgDesc:"); @@ -1894,10 +1894,10 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, break; case BRW_SFID_SAMPLER: if (devinfo->ver >= 5) { - err |= control(file, "sampler message", gen5_sampler_msg_type, + err |= control(file, "sampler message", gfx5_sampler_msg_type, brw_sampler_desc_msg_type(devinfo, imm_desc), &space); - err |= control(file, "sampler simd mode", gen5_sampler_simd_mode, + err |= control(file, "sampler simd mode", gfx5_sampler_simd_mode, brw_sampler_desc_simd_mode(devinfo, imm_desc), &space); format(file, " Surface = %u Sampler = %u", @@ -1930,7 +1930,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, } else { bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x; err |= control(file, "DP read message type", - is_965 ? gen4_dp_read_port_msg_type : + is_965 ? gfx4_dp_read_port_msg_type : g45_dp_read_port_msg_type, brw_dp_read_desc_msg_type(devinfo, imm_desc), &space); @@ -1982,8 +1982,8 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, space = 1; err |= control(file, "urb opcode", - devinfo->ver >= 7 ? gen7_urb_opcode - : gen5_urb_opcode, + devinfo->ver >= 7 ? gfx7_urb_opcode + : gfx5_urb_opcode, opcode, &space); if (devinfo->ver >= 7 && @@ -2018,7 +2018,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, case BRW_SFID_MESSAGE_GATEWAY: format(file, " (%s)", - gen7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]); + gfx7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]); break; case GFX7_SFID_DATAPORT_DATA_CACHE: @@ -2026,7 +2026,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, format(file, " ("); err |= control(file, "DP DC0 message type", - dp_dc0_msg_type_gen7, + dp_dc0_msg_type_gfx7, brw_dp_desc_msg_type(devinfo, imm_desc), &space); format(file, ", %u, ", diff --git a/src/intel/compiler/brw_eu.cpp b/src/intel/compiler/brw_eu.cpp index 870a5b89f77..414483494b5 100644 --- a/src/intel/compiler/brw_eu.cpp +++ b/src/intel/compiler/brw_eu.cpp @@ -495,7 +495,7 @@ brw_label_assembly(const struct gen_device_info *devinfo, if (devinfo->ver >= 7) { jip = brw_inst_jip(devinfo, inst); } else { - jip = brw_inst_gen6_jump_count(devinfo, inst); + jip = brw_inst_gfx6_jump_count(devinfo, inst); } brw_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx); diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 123156fb7d4..9072949d0c5 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -54,7 +54,7 @@ struct brw_insn_state { /* Group in units of channels */ unsigned group:5; - /* Compression control on gen4-5 */ + /* Compression control on gfx4-5 */ bool compressed:1; /* One of BRW_MASK_* */ @@ -129,7 +129,7 @@ struct brw_codegen { */ int *loop_stack; /** - * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF + * pre-gfx6, the BREAK and CONT instructions had to tell how many IF/ENDIF * blocks they were popping out of, to fix up the mask stack. This tracks * the IF/ENDIF nesting in each current nested loop level. */ @@ -202,7 +202,7 @@ brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode); void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest); void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg); -void gen6_resolve_implied_move(struct brw_codegen *p, +void gfx6_resolve_implied_move(struct brw_codegen *p, struct brw_reg *src, unsigned msg_reg_nr); @@ -446,7 +446,7 @@ brw_dp_desc(const struct gen_device_info *devinfo, unsigned msg_type, unsigned msg_control) { - /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc + /* Prior to gfx6, things are too inconsistent; use the dp_read/write_desc * helpers instead. */ assert(devinfo->ver >= 6); @@ -1155,7 +1155,7 @@ brw_inst *brw_fb_WRITE(struct brw_codegen *p, bool last_render_target, bool header_present); -brw_inst *gen9_fb_READ(struct brw_codegen *p, +brw_inst *gfx9_fb_READ(struct brw_codegen *p, struct brw_reg dst, struct brw_reg payload, unsigned binding_table_index, @@ -1180,14 +1180,14 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p, struct brw_reg header, struct brw_reg sampler_index); -void gen4_math(struct brw_codegen *p, +void gfx4_math(struct brw_codegen *p, struct brw_reg dest, unsigned function, unsigned msg_reg_nr, struct brw_reg src, unsigned precision ); -void gen6_math(struct brw_codegen *p, +void gfx6_math(struct brw_codegen *p, struct brw_reg dest, unsigned function, struct brw_reg src0, @@ -1212,7 +1212,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p, int num_regs, unsigned offset); -void gen7_block_read_scratch(struct brw_codegen *p, +void gfx7_block_read_scratch(struct brw_codegen *p, struct brw_reg dest, int num_regs, unsigned offset); @@ -1251,7 +1251,7 @@ void brw_barrier(struct brw_codegen *p, struct brw_reg src); * channel. */ brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size); -brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, +brw_inst *gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, struct brw_reg src0, struct brw_reg src1); void brw_ELSE(struct brw_codegen *p); diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index 24e8e37d95e..856cccfa7e4 100644 --- a/src/intel/compiler/brw_eu_compact.c +++ b/src/intel/compiler/brw_eu_compact.c @@ -223,7 +223,7 @@ static const uint16_t g45_src_index_table[32] = { 0b111101110100, }; -static const uint32_t gen6_control_index_table[32] = { +static const uint32_t gfx6_control_index_table[32] = { 0b00000000000000000, 0b01000000000000000, 0b00110000000000000, @@ -258,7 +258,7 @@ static const uint32_t gen6_control_index_table[32] = { 0b00100000000001001, }; -static const uint32_t gen6_datatype_table[32] = { +static const uint32_t gfx6_datatype_table[32] = { 0b001001110000000000, 0b001000110000100000, 0b001001110000000001, @@ -293,7 +293,7 @@ static const uint32_t gen6_datatype_table[32] = { 0b001000001110111110, }; -static const uint16_t gen6_subreg_table[32] = { +static const uint16_t gfx6_subreg_table[32] = { 0b000000000000000, 0b000000000000100, 0b000000110000000, @@ -328,7 +328,7 @@ static const uint16_t gen6_subreg_table[32] = { 0b000110000000000, }; -static const uint16_t gen6_src_index_table[32] = { +static const uint16_t gfx6_src_index_table[32] = { 0b000000000000, 0b010110001000, 0b010001101000, @@ -363,7 +363,7 @@ static const uint16_t gen6_src_index_table[32] = { 0b001101010000, }; -static const uint32_t gen7_control_index_table[32] = { +static const uint32_t gfx7_control_index_table[32] = { 0b0000000000000000010, 0b0000100000000000000, 0b0000100000000000001, @@ -398,7 +398,7 @@ static const uint32_t gen7_control_index_table[32] = { 0b0101000000100000000, }; -static const uint32_t gen7_datatype_table[32] = { +static const uint32_t gfx7_datatype_table[32] = { 0b001000000000000001, 0b001000000000100000, 0b001000000000100001, @@ -433,7 +433,7 @@ static const uint32_t gen7_datatype_table[32] = { 0b001010110100101000, }; -static const uint16_t gen7_subreg_table[32] = { +static const uint16_t gfx7_subreg_table[32] = { 0b000000000000000, 0b000000000000001, 0b000000000001000, @@ -468,7 +468,7 @@ static const uint16_t gen7_subreg_table[32] = { 0b111000000011100, }; -static const uint16_t gen7_src_index_table[32] = { +static const uint16_t gfx7_src_index_table[32] = { 0b000000000000, 0b000000000010, 0b000000010000, @@ -503,7 +503,7 @@ static const uint16_t gen7_src_index_table[32] = { 0b010110001000, }; -static const uint32_t gen8_control_index_table[32] = { +static const uint32_t gfx8_control_index_table[32] = { 0b0000000000000000010, 0b0000100000000000000, 0b0000100000000000001, @@ -538,7 +538,7 @@ static const uint32_t gen8_control_index_table[32] = { 0b0101000000100000000, }; -static const uint32_t gen8_datatype_table[32] = { +static const uint32_t gfx8_datatype_table[32] = { 0b001000000000000000001, 0b001000000000001000000, 0b001000000000001000001, @@ -573,7 +573,7 @@ static const uint32_t gen8_datatype_table[32] = { 0b001001011001001001000, }; -static const uint16_t gen8_subreg_table[32] = { +static const uint16_t gfx8_subreg_table[32] = { 0b000000000000000, 0b000000000000001, 0b000000000001000, @@ -608,7 +608,7 @@ static const uint16_t gen8_subreg_table[32] = { 0b111000000011100, }; -static const uint16_t gen8_src_index_table[32] = { +static const uint16_t gfx8_src_index_table[32] = { 0b000000000000, 0b000000000010, 0b000000010000, @@ -643,7 +643,7 @@ static const uint16_t gen8_src_index_table[32] = { 0b010110001000, }; -static const uint32_t gen11_datatype_table[32] = { +static const uint32_t gfx11_datatype_table[32] = { 0b001000000000000000001, 0b001000000000001000000, 0b001000000000001000001, @@ -678,7 +678,7 @@ static const uint32_t gen11_datatype_table[32] = { 0b001001011001001001000, }; -static const uint32_t gen12_control_index_table[32] = { +static const uint32_t gfx12_control_index_table[32] = { 0b000000000000000000100, /* (16|M0) */ 0b000000000000000000011, /* (8|M0) */ 0b000000010000000000000, /* (W) (1|M0) */ @@ -713,7 +713,7 @@ static const uint32_t gen12_control_index_table[32] = { 0b000000010000000100100, /* (W) (16|M16) */ }; -static const uint32_t gen12_datatype_table[32] = { +static const uint32_t gfx12_datatype_table[32] = { 0b11010110100101010100, /* grf<1>:f grf:f grf:f */ 0b00000110100101010100, /* grf<1>:f grf:f arf:ub */ 0b00000010101101010100, /* grf<1>:f imm:f arf:ub */ @@ -748,7 +748,7 @@ static const uint32_t gen12_datatype_table[32] = { 0b00000010100101010100, /* grf<1>:f arf:f arf:ub */ }; -static const uint16_t gen12_subreg_table[32] = { +static const uint16_t gfx12_subreg_table[32] = { 0b000000000000000, /* .0 .0 .0 */ 0b100000000000000, /* .0 .0 .16 */ 0b001000000000000, /* .0 .0 .4 */ @@ -783,7 +783,7 @@ static const uint16_t gen12_subreg_table[32] = { 0b110001100000000, /* .0 .24 .24 */ }; -static const uint16_t gen12_src0_index_table[16] = { +static const uint16_t gfx12_src0_index_table[16] = { 0b010001100100, /* r<8;8,1> */ 0b000000000000, /* r<0;1,0> */ 0b010001100110, /* -r<8;8,1> */ @@ -802,7 +802,7 @@ static const uint16_t gen12_src0_index_table[16] = { 0b111100010000, /* r[a]<1,0> */ }; -static const uint16_t gen12_src1_index_table[16] = { +static const uint16_t gfx12_src1_index_table[16] = { 0b000100011001, /* r<8;8,1> */ 0b000000000000, /* r<0;1,0> */ 0b100100011001, /* -r<8;8,1> */ @@ -827,7 +827,7 @@ static const uint16_t gen12_src1_index_table[16] = { * * The low 24 bits have the same mappings on both hardware. */ -static const uint32_t gen8_3src_control_index_table[4] = { +static const uint32_t gfx8_3src_control_index_table[4] = { 0b00100000000110000000000001, 0b00000000000110000000000001, 0b00000000001000000000000001, @@ -841,14 +841,14 @@ static const uint32_t gen8_3src_control_index_table[4] = { * The low 44 bits have the same mappings on both hardware, and since the high * three bits on Broadwell are zero, we can reuse Cherryview's table. */ -static const uint64_t gen8_3src_source_index_table[4] = { +static const uint64_t gfx8_3src_source_index_table[4] = { 0b0000001110010011100100111001000001111000000000000, 0b0000001110010011100100111001000001111000000000010, 0b0000001110010011100100111001000001111000000001000, 0b0000001110010011100100111001000001111000000100000, }; -static const uint64_t gen12_3src_control_index_table[32] = { +static const uint64_t gfx12_3src_control_index_table[32] = { 0b000001001010010101000000000000000100, /* (16|M0) grf<1>:f :f :f :f */ 0b000001001010010101000000000000000011, /* (8|M0) grf<1>:f :f :f :f */ 0b000001001000010101000000000000000011, /* (8|M0) arf<1>:f :f :f :f */ @@ -883,7 +883,7 @@ static const uint64_t gen12_3src_control_index_table[32] = { 0b000001001000010101010000000000000011, /* (8|M0) (sat)arf<1>:f :f :f :f */ }; -static const uint32_t gen12_3src_source_index_table[32] = { +static const uint32_t gfx12_3src_source_index_table[32] = { 0b100101100001100000000, /* grf<0;0> grf<8;1> grf<0> */ 0b100101100001001000010, /* arf<4;1> grf<8;1> grf<0> */ 0b101101100001101000011, /* grf<8;1> grf<8;1> grf<1> */ @@ -918,7 +918,7 @@ static const uint32_t gen12_3src_source_index_table[32] = { 0b101001100101101000011, /* grf<8;1> arf<8;1> -grf<1> */ }; -static const uint32_t gen12_3src_subreg_table[32] = { +static const uint32_t gfx12_3src_subreg_table[32] = { 0b00000000000000000000, /* .0 .0 .0 .0 */ 0b00100000000000000000, /* .0 .0 .0 .4 */ 0b00000000000110000000, /* .0 .12 .0 .0 */ @@ -993,7 +993,7 @@ set_control_index(const struct compaction_state *c, uncompacted = (brw_inst_bits(src, 31, 31) << 16) | /* 1b */ (brw_inst_bits(src, 23, 8)); /* 16b */ - /* On gen7, the flag register and subregister numbers are integrated into + /* On gfx7, the flag register and subregister numbers are integrated into * the control index. */ if (devinfo->ver == 7) @@ -1093,14 +1093,14 @@ set_src0_index(const struct compaction_state *c, brw_compact_inst *dst, int table_len; if (devinfo->ver >= 12) { - table_len = ARRAY_SIZE(gen12_src0_index_table); + table_len = ARRAY_SIZE(gfx12_src0_index_table); uncompacted = (brw_inst_bits(src, 87, 84) << 8) | /* 4b */ (brw_inst_bits(src, 83, 81) << 5) | /* 3b */ (brw_inst_bits(src, 80, 80) << 4) | /* 1b */ (brw_inst_bits(src, 65, 64) << 2) | /* 2b */ (brw_inst_bits(src, 45, 44)); /* 2b */ } else { - table_len = ARRAY_SIZE(gen8_src_index_table); + table_len = ARRAY_SIZE(gfx8_src_index_table); uncompacted = brw_inst_bits(src, 88, 77); /* 12b */ } @@ -1133,14 +1133,14 @@ set_src1_index(const struct compaction_state *c, brw_compact_inst *dst, int table_len; if (devinfo->ver >= 12) { - table_len = ARRAY_SIZE(gen12_src0_index_table); + table_len = ARRAY_SIZE(gfx12_src0_index_table); uncompacted = (brw_inst_bits(src, 121, 120) << 10) | /* 2b */ (brw_inst_bits(src, 119, 116) << 6) | /* 4b */ (brw_inst_bits(src, 115, 113) << 3) | /* 3b */ (brw_inst_bits(src, 112, 112) << 2) | /* 1b */ (brw_inst_bits(src, 97, 96)); /* 2b */ } else { - table_len = ARRAY_SIZE(gen8_src_index_table); + table_len = ARRAY_SIZE(gfx8_src_index_table); uncompacted = brw_inst_bits(src, 120, 109); /* 12b */ } @@ -1182,8 +1182,8 @@ set_3src_control_index(const struct gen_device_info *devinfo, (brw_inst_bits(src, 21, 19) << 3) | /* 3b */ (brw_inst_bits(src, 18, 16)); /* 3b */ - for (unsigned i = 0; i < ARRAY_SIZE(gen12_3src_control_index_table); i++) { - if (gen12_3src_control_index_table[i] == uncompacted) { + for (unsigned i = 0; i < ARRAY_SIZE(gfx12_3src_control_index_table); i++) { + if (gfx12_3src_control_index_table[i] == uncompacted) { brw_compact_inst_set_3src_control_index(devinfo, dst, i); return true; } @@ -1198,8 +1198,8 @@ set_3src_control_index(const struct gen_device_info *devinfo, brw_inst_bits(src, 36, 35) << 24; /* 2b */ } - for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) { - if (gen8_3src_control_index_table[i] == uncompacted) { + for (unsigned i = 0; i < ARRAY_SIZE(gfx8_3src_control_index_table); i++) { + if (gfx8_3src_control_index_table[i] == uncompacted) { brw_compact_inst_set_3src_control_index(devinfo, dst, i); return true; } @@ -1233,8 +1233,8 @@ set_3src_source_index(const struct gen_device_info *devinfo, (brw_inst_bits(src, 43, 43) << 1) | /* 1b */ (brw_inst_bits(src, 35, 35)); /* 1b */ - for (unsigned i = 0; i < ARRAY_SIZE(gen12_3src_source_index_table); i++) { - if (gen12_3src_source_index_table[i] == uncompacted) { + for (unsigned i = 0; i < ARRAY_SIZE(gfx12_3src_source_index_table); i++) { + if (gfx12_3src_source_index_table[i] == uncompacted) { brw_compact_inst_set_3src_source_index(devinfo, dst, i); return true; } @@ -1258,8 +1258,8 @@ set_3src_source_index(const struct gen_device_info *devinfo, (brw_inst_bits(src, 104, 104) << 44); /* 1b */ } - for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) { - if (gen8_3src_source_index_table[i] == uncompacted) { + for (unsigned i = 0; i < ARRAY_SIZE(gfx8_3src_source_index_table); i++) { + if (gfx8_3src_source_index_table[i] == uncompacted) { brw_compact_inst_set_3src_source_index(devinfo, dst, i); return true; } @@ -1281,8 +1281,8 @@ set_3src_subreg_index(const struct gen_device_info *devinfo, (brw_inst_bits(src, 71, 67) << 5) | /* 5b */ (brw_inst_bits(src, 55, 51)); /* 5b */ - for (unsigned i = 0; i < ARRAY_SIZE(gen12_3src_subreg_table); i++) { - if (gen12_3src_subreg_table[i] == uncompacted) { + for (unsigned i = 0; i < ARRAY_SIZE(gfx12_3src_subreg_table); i++) { + if (gfx12_3src_subreg_table[i] == uncompacted) { brw_compact_inst_set_3src_subreg_index(devinfo, dst, i); return true; } @@ -1887,7 +1887,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c, if (devinfo->ver >= 12) { uint64_t compacted = brw_compact_inst_3src_control_index(devinfo, src); - uint64_t uncompacted = gen12_3src_control_index_table[compacted]; + uint64_t uncompacted = gfx12_3src_control_index_table[compacted]; brw_inst_set_bits(dst, 95, 92, (uncompacted >> 32)); brw_inst_set_bits(dst, 90, 88, (uncompacted >> 29) & 0x7); @@ -1909,7 +1909,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c, brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7); } else { uint32_t compacted = brw_compact_inst_3src_control_index(devinfo, src); - uint32_t uncompacted = gen8_3src_control_index_table[compacted]; + uint32_t uncompacted = gfx8_3src_control_index_table[compacted]; brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7); brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff); @@ -1928,7 +1928,7 @@ set_uncompacted_3src_source_index(const struct gen_device_info *devinfo, uint32_t compacted = brw_compact_inst_3src_source_index(devinfo, src); if (devinfo->ver >= 12) { - uint32_t uncompacted = gen12_3src_source_index_table[compacted]; + uint32_t uncompacted = gfx12_3src_source_index_table[compacted]; brw_inst_set_bits(dst, 114, 114, (uncompacted >> 20)); brw_inst_set_bits(dst, 113, 112, (uncompacted >> 18) & 0x3); @@ -1946,7 +1946,7 @@ set_uncompacted_3src_source_index(const struct gen_device_info *devinfo, brw_inst_set_bits(dst, 43, 43, (uncompacted >> 1) & 0x1); brw_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1); } else { - uint64_t uncompacted = gen8_3src_source_index_table[compacted]; + uint64_t uncompacted = gfx8_3src_source_index_table[compacted]; brw_inst_set_bits(dst, 83, 83, (uncompacted >> 43) & 0x1); brw_inst_set_bits(dst, 114, 107, (uncompacted >> 35) & 0xff); @@ -1972,7 +1972,7 @@ set_uncompacted_3src_subreg_index(const struct gen_device_info *devinfo, assert(devinfo->ver >= 12); uint32_t compacted = brw_compact_inst_3src_subreg_index(devinfo, src); - uint32_t uncompacted = gen12_3src_subreg_table[compacted]; + uint32_t uncompacted = gfx12_3src_subreg_table[compacted]; brw_inst_set_bits(dst, 119, 115, (uncompacted >> 15)); brw_inst_set_bits(dst, 103, 99, (uncompacted >> 10) & 0x1f); @@ -2165,7 +2165,7 @@ update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn, } static void -update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn, +update_gfx4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn, int this_old_ip, int *compacted_counts) { assert(devinfo->ver == 5 || devinfo->is_g4x); @@ -2176,7 +2176,7 @@ update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn, */ int shift = devinfo->is_g4x ? 1 : 0; - int jump_count_compacted = brw_inst_gen4_jump_count(devinfo, insn) << shift; + int jump_count_compacted = brw_inst_gfx4_jump_count(devinfo, insn) << shift; int target_old_ip = this_old_ip + (jump_count_compacted / 2); @@ -2184,7 +2184,7 @@ update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn, int target_compacted_count = compacted_counts[target_old_ip]; jump_count_compacted -= (target_compacted_count - this_compacted_count); - brw_inst_set_gen4_jump_count(devinfo, insn, jump_count_compacted >> shift); + brw_inst_set_gfx4_jump_count(devinfo, insn, jump_count_compacted >> shift); } static void @@ -2195,62 +2195,62 @@ compaction_state_init(struct compaction_state *c, assert(g45_datatype_table[ARRAY_SIZE(g45_datatype_table) - 1] != 0); assert(g45_subreg_table[ARRAY_SIZE(g45_subreg_table) - 1] != 0); assert(g45_src_index_table[ARRAY_SIZE(g45_src_index_table) - 1] != 0); - assert(gen6_control_index_table[ARRAY_SIZE(gen6_control_index_table) - 1] != 0); - assert(gen6_datatype_table[ARRAY_SIZE(gen6_datatype_table) - 1] != 0); - assert(gen6_subreg_table[ARRAY_SIZE(gen6_subreg_table) - 1] != 0); - assert(gen6_src_index_table[ARRAY_SIZE(gen6_src_index_table) - 1] != 0); - assert(gen7_control_index_table[ARRAY_SIZE(gen7_control_index_table) - 1] != 0); - assert(gen7_datatype_table[ARRAY_SIZE(gen7_datatype_table) - 1] != 0); - assert(gen7_subreg_table[ARRAY_SIZE(gen7_subreg_table) - 1] != 0); - assert(gen7_src_index_table[ARRAY_SIZE(gen7_src_index_table) - 1] != 0); - assert(gen8_control_index_table[ARRAY_SIZE(gen8_control_index_table) - 1] != 0); - assert(gen8_datatype_table[ARRAY_SIZE(gen8_datatype_table) - 1] != 0); - assert(gen8_subreg_table[ARRAY_SIZE(gen8_subreg_table) - 1] != 0); - assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0); - assert(gen11_datatype_table[ARRAY_SIZE(gen11_datatype_table) - 1] != 0); - assert(gen12_control_index_table[ARRAY_SIZE(gen12_control_index_table) - 1] != 0); - assert(gen12_datatype_table[ARRAY_SIZE(gen12_datatype_table) - 1] != 0); - assert(gen12_subreg_table[ARRAY_SIZE(gen12_subreg_table) - 1] != 0); - assert(gen12_src0_index_table[ARRAY_SIZE(gen12_src0_index_table) - 1] != 0); - assert(gen12_src1_index_table[ARRAY_SIZE(gen12_src1_index_table) - 1] != 0); + assert(gfx6_control_index_table[ARRAY_SIZE(gfx6_control_index_table) - 1] != 0); + assert(gfx6_datatype_table[ARRAY_SIZE(gfx6_datatype_table) - 1] != 0); + assert(gfx6_subreg_table[ARRAY_SIZE(gfx6_subreg_table) - 1] != 0); + assert(gfx6_src_index_table[ARRAY_SIZE(gfx6_src_index_table) - 1] != 0); + assert(gfx7_control_index_table[ARRAY_SIZE(gfx7_control_index_table) - 1] != 0); + assert(gfx7_datatype_table[ARRAY_SIZE(gfx7_datatype_table) - 1] != 0); + assert(gfx7_subreg_table[ARRAY_SIZE(gfx7_subreg_table) - 1] != 0); + assert(gfx7_src_index_table[ARRAY_SIZE(gfx7_src_index_table) - 1] != 0); + assert(gfx8_control_index_table[ARRAY_SIZE(gfx8_control_index_table) - 1] != 0); + assert(gfx8_datatype_table[ARRAY_SIZE(gfx8_datatype_table) - 1] != 0); + assert(gfx8_subreg_table[ARRAY_SIZE(gfx8_subreg_table) - 1] != 0); + assert(gfx8_src_index_table[ARRAY_SIZE(gfx8_src_index_table) - 1] != 0); + assert(gfx11_datatype_table[ARRAY_SIZE(gfx11_datatype_table) - 1] != 0); + assert(gfx12_control_index_table[ARRAY_SIZE(gfx12_control_index_table) - 1] != 0); + assert(gfx12_datatype_table[ARRAY_SIZE(gfx12_datatype_table) - 1] != 0); + assert(gfx12_subreg_table[ARRAY_SIZE(gfx12_subreg_table) - 1] != 0); + assert(gfx12_src0_index_table[ARRAY_SIZE(gfx12_src0_index_table) - 1] != 0); + assert(gfx12_src1_index_table[ARRAY_SIZE(gfx12_src1_index_table) - 1] != 0); c->devinfo = devinfo; switch (devinfo->ver) { case 12: - c->control_index_table = gen12_control_index_table;; - c->datatype_table = gen12_datatype_table; - c->subreg_table = gen12_subreg_table; - c->src0_index_table = gen12_src0_index_table; - c->src1_index_table = gen12_src1_index_table; + c->control_index_table = gfx12_control_index_table;; + c->datatype_table = gfx12_datatype_table; + c->subreg_table = gfx12_subreg_table; + c->src0_index_table = gfx12_src0_index_table; + c->src1_index_table = gfx12_src1_index_table; break; case 11: - c->control_index_table = gen8_control_index_table; - c->datatype_table = gen11_datatype_table; - c->subreg_table = gen8_subreg_table; - c->src0_index_table = gen8_src_index_table; - c->src1_index_table = gen8_src_index_table; + c->control_index_table = gfx8_control_index_table; + c->datatype_table = gfx11_datatype_table; + c->subreg_table = gfx8_subreg_table; + c->src0_index_table = gfx8_src_index_table; + c->src1_index_table = gfx8_src_index_table; break; case 9: case 8: - c->control_index_table = gen8_control_index_table; - c->datatype_table = gen8_datatype_table; - c->subreg_table = gen8_subreg_table; - c->src0_index_table = gen8_src_index_table; - c->src1_index_table = gen8_src_index_table; + c->control_index_table = gfx8_control_index_table; + c->datatype_table = gfx8_datatype_table; + c->subreg_table = gfx8_subreg_table; + c->src0_index_table = gfx8_src_index_table; + c->src1_index_table = gfx8_src_index_table; break; case 7: - c->control_index_table = gen7_control_index_table; - c->datatype_table = gen7_datatype_table; - c->subreg_table = gen7_subreg_table; - c->src0_index_table = gen7_src_index_table; - c->src1_index_table = gen7_src_index_table; + c->control_index_table = gfx7_control_index_table; + c->datatype_table = gfx7_datatype_table; + c->subreg_table = gfx7_subreg_table; + c->src0_index_table = gfx7_src_index_table; + c->src1_index_table = gfx7_src_index_table; break; case 6: - c->control_index_table = gen6_control_index_table; - c->datatype_table = gen6_datatype_table; - c->subreg_table = gen6_subreg_table; - c->src0_index_table = gen6_src_index_table; - c->src1_index_table = gen6_src_index_table; + c->control_index_table = gfx6_control_index_table; + c->datatype_table = gfx6_datatype_table; + c->subreg_table = gfx6_subreg_table; + c->src0_index_table = gfx6_src_index_table; + c->src1_index_table = gfx6_src_index_table; break; case 5: case 4: @@ -2362,7 +2362,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, if (devinfo->ver >= 6) { update_uip_jip(devinfo, insn, this_old_ip, compacted_counts); } else { - update_gen4_jump_count(devinfo, insn, this_old_ip, + update_gfx4_jump_count(devinfo, insn, this_old_ip, compacted_counts); } break; @@ -2391,14 +2391,14 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, assert(!brw_inst_cmpt_control(devinfo, insn)); /* Jump Count is in units of compacted instructions on Gen6. */ - int jump_count_compacted = brw_inst_gen6_jump_count(devinfo, insn); + int jump_count_compacted = brw_inst_gfx6_jump_count(devinfo, insn); int target_old_ip = this_old_ip + (jump_count_compacted / 2); int target_compacted_count = compacted_counts[target_old_ip]; jump_count_compacted -= (target_compacted_count - this_compacted_count); - brw_inst_set_gen6_jump_count(devinfo, insn, jump_count_compacted); + brw_inst_set_gfx6_jump_count(devinfo, insn, jump_count_compacted); } else { - update_gen4_jump_count(devinfo, insn, this_old_ip, + update_gfx4_jump_count(devinfo, insn, this_old_ip, compacted_counts); } break; diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 7e95ef5f008..4a13852b58d 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -157,14 +157,14 @@ enum PACKED brw_horizontal_stride { BRW_HORIZONTAL_STRIDE_4 = 3, }; -enum PACKED gen10_align1_3src_src_horizontal_stride { +enum PACKED gfx10_align1_3src_src_horizontal_stride { BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0, BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1, BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2, BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3, }; -enum PACKED gen10_align1_3src_dst_horizontal_stride { +enum PACKED gfx10_align1_3src_dst_horizontal_stride { BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1, }; @@ -610,7 +610,7 @@ enum opcode { /** * Write geometry shader output data to the URB and request a new URB - * handle (gen6). + * handle (gfx6). * * This opcode doesn't do an implied move from R0 to the first MRF. */ @@ -690,7 +690,7 @@ enum opcode { GS_OPCODE_GET_INSTANCE_ID, /** - * Send a FF_SYNC message to allocate initial URB handles (gen6). + * Send a FF_SYNC message to allocate initial URB handles (gfx6). * * - dst will be used as the writeback register for the FF_SYNC operation. * @@ -709,7 +709,7 @@ enum opcode { GS_OPCODE_FF_SYNC, /** - * Move r0.1 (which holds PrimitiveID information in gen6) to a separate + * Move r0.1 (which holds PrimitiveID information in gfx6) to a separate * register. * * - dst is the GRF where PrimitiveID information will be moved. @@ -718,7 +718,7 @@ enum opcode { /** * Write transform feedback data to the SVB by sending a SVB WRITE message. - * Used in gen6. + * Used in gfx6. * * - dst is the MRF register containing the message header. * @@ -730,7 +730,7 @@ enum opcode { /** * Set destination index in the SVB write message payload (M0.5). Used - * in gen6 for transform feedback. + * in gfx6 for transform feedback. * * - dst is the header to save the destination indices for SVB WRITE. * - src is the register that holds the destination indices value. @@ -739,7 +739,7 @@ enum opcode { /** * Prepare Mx.0 subregister for being used in the FF_SYNC message header. - * Used in gen6 for transform feedback. + * Used in gfx6 for transform feedback. * * - dst will hold the register with the final Mx.0 value. * @@ -987,7 +987,7 @@ enum PACKED brw_reg_file { BAD_FILE, }; -enum PACKED gen10_align1_3src_reg_file { +enum PACKED gfx10_align1_3src_reg_file { BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0, BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */ BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ @@ -998,7 +998,7 @@ enum PACKED gen10_align1_3src_reg_file { * on float or integer types. The register arguments have fields that offer * more fine control their respective types. */ -enum PACKED gen10_align1_3src_exec_type { +enum PACKED gfx10_align1_3src_exec_type { BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0, BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1, }; @@ -1041,7 +1041,7 @@ enum PACKED brw_vertical_stride { BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF, }; -enum PACKED gen10_align1_3src_vertical_stride { +enum PACKED gfx10_align1_3src_vertical_stride { BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1, BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, @@ -1530,8 +1530,8 @@ enum brw_message_target { #define BRW_MATH_FUNCTION_RSQ 5 #define BRW_MATH_FUNCTION_SIN 6 #define BRW_MATH_FUNCTION_COS 7 -#define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */ -#define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */ +#define BRW_MATH_FUNCTION_SINCOS 8 /* gfx4, gfx5 */ +#define BRW_MATH_FUNCTION_FDIV 9 /* gfx6+ */ #define BRW_MATH_FUNCTION_POW 10 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 8b3aa74f06f..9b0810d879f 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -43,7 +43,7 @@ * explicit move; it should be called before emitting a SEND instruction. */ void -gen6_resolve_implied_move(struct brw_codegen *p, +gfx6_resolve_implied_move(struct brw_codegen *p, struct brw_reg *src, unsigned msg_reg_nr) { @@ -68,7 +68,7 @@ gen6_resolve_implied_move(struct brw_codegen *p, } static void -gen7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg) +gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg) { /* From the Ivybridge PRM, Volume 4 Part 3, page 218 ("send"): * "The send with EOT should use register space R112-R127 for . This is @@ -107,7 +107,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) dest.hstride = BRW_HORIZONTAL_STRIDE_2; } - gen7_convert_mrf_to_grf(p, &dest); + gfx7_convert_mrf_to_grf(p, &dest); if (devinfo->ver >= 12 && (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND || @@ -215,7 +215,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) else if (reg.file == BRW_GENERAL_REGISTER_FILE) assert(reg.nr < 128); - gen7_convert_mrf_to_grf(p, ®); + gfx7_convert_mrf_to_grf(p, ®); if (devinfo->ver >= 6 && (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND || @@ -373,7 +373,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) assert(reg.file != BRW_ARCHITECTURE_REGISTER_FILE || reg.nr != BRW_ARF_ACCUMULATOR); - gen7_convert_mrf_to_grf(p, ®); + gfx7_convert_mrf_to_grf(p, ®); assert(reg.file != BRW_MESSAGE_REGISTER_FILE); brw_inst_set_src1_file_type(devinfo, inst, reg.file, reg.type); @@ -580,7 +580,7 @@ static void brw_set_urb_message( struct brw_codegen *p, } static void -gen7_set_dp_scratch_message(struct brw_codegen *p, +gfx7_set_dp_scratch_message(struct brw_codegen *p, brw_inst *inst, bool write, bool dword, @@ -741,7 +741,7 @@ get_3src_subreg_nr(struct brw_reg reg) return reg.subnr / 4; } -static enum gen10_align1_3src_vertical_stride +static enum gfx10_align1_3src_vertical_stride to_3src_align1_vstride(const struct gen_device_info *devinfo, enum brw_vertical_stride vstride) { @@ -765,7 +765,7 @@ to_3src_align1_vstride(const struct gen_device_info *devinfo, } -static enum gen10_align1_3src_src_horizontal_stride +static enum gfx10_align1_3src_src_horizontal_stride to_3src_align1_hstride(enum brw_horizontal_stride hstride) { switch (hstride) { @@ -789,7 +789,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, const struct gen_device_info *devinfo = p->devinfo; brw_inst *inst = next_insn(p, opcode); - gen7_convert_mrf_to_grf(p, &dest); + gfx7_convert_mrf_to_grf(p, &dest); assert(dest.nr < 128); @@ -1410,7 +1410,7 @@ brw_IF(struct brw_codegen *p, unsigned execute_size) brw_set_src1(p, insn, brw_imm_d(0x0)); } else if (devinfo->ver == 6) { brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_gen6_jump_count(devinfo, insn, 0); + brw_inst_set_gfx6_jump_count(devinfo, insn, 0); brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); } else if (devinfo->ver == 7) { @@ -1439,11 +1439,11 @@ brw_IF(struct brw_codegen *p, unsigned execute_size) return insn; } -/* This function is only used for gen6-style IF instructions with an - * embedded comparison (conditional modifier). It is not used on gen7. +/* This function is only used for gfx6-style IF instructions with an + * embedded comparison (conditional modifier). It is not used on gfx7. */ brw_inst * -gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, +gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, struct brw_reg src0, struct brw_reg src1) { const struct gen_device_info *devinfo = p->devinfo; @@ -1453,7 +1453,7 @@ gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, brw_set_dest(p, insn, brw_imm_w(0)); brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p)); - brw_inst_set_gen6_jump_count(devinfo, insn, 0); + brw_inst_set_gfx6_jump_count(devinfo, insn, 0); brw_set_src0(p, insn, src0); brw_set_src1(p, insn, src1); @@ -1546,12 +1546,12 @@ patch_IF_ELSE(struct brw_codegen *p, * all-false and jumping past the ENDIF. */ brw_inst_set_opcode(devinfo, if_inst, BRW_OPCODE_IFF); - brw_inst_set_gen4_jump_count(devinfo, if_inst, + brw_inst_set_gfx4_jump_count(devinfo, if_inst, br * (endif_inst - if_inst + 1)); - brw_inst_set_gen4_pop_count(devinfo, if_inst, 0); + brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0); } else if (devinfo->ver == 6) { - /* As of gen6, there is no IFF and IF must point to the ENDIF. */ - brw_inst_set_gen6_jump_count(devinfo, if_inst, br*(endif_inst - if_inst)); + /* As of gfx6, there is no IFF and IF must point to the ENDIF. */ + brw_inst_set_gfx6_jump_count(devinfo, if_inst, br*(endif_inst - if_inst)); } else { brw_inst_set_uip(devinfo, if_inst, br * (endif_inst - if_inst)); brw_inst_set_jip(devinfo, if_inst, br * (endif_inst - if_inst)); @@ -1561,25 +1561,25 @@ patch_IF_ELSE(struct brw_codegen *p, /* Patch IF -> ELSE */ if (devinfo->ver < 6) { - brw_inst_set_gen4_jump_count(devinfo, if_inst, + brw_inst_set_gfx4_jump_count(devinfo, if_inst, br * (else_inst - if_inst)); - brw_inst_set_gen4_pop_count(devinfo, if_inst, 0); + brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0); } else if (devinfo->ver == 6) { - brw_inst_set_gen6_jump_count(devinfo, if_inst, + brw_inst_set_gfx6_jump_count(devinfo, if_inst, br * (else_inst - if_inst + 1)); } /* Patch ELSE -> ENDIF */ if (devinfo->ver < 6) { - /* BRW_OPCODE_ELSE pre-gen6 should point just past the + /* BRW_OPCODE_ELSE pre-gfx6 should point just past the * matching ENDIF. */ - brw_inst_set_gen4_jump_count(devinfo, else_inst, + brw_inst_set_gfx4_jump_count(devinfo, else_inst, br * (endif_inst - else_inst + 1)); - brw_inst_set_gen4_pop_count(devinfo, else_inst, 1); + brw_inst_set_gfx4_pop_count(devinfo, else_inst, 1); } else if (devinfo->ver == 6) { - /* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */ - brw_inst_set_gen6_jump_count(devinfo, else_inst, + /* BRW_OPCODE_ELSE on gfx6 should point to the matching ENDIF. */ + brw_inst_set_gfx6_jump_count(devinfo, else_inst, br * (endif_inst - else_inst)); } else { /* The IF instruction's JIP should point just past the ELSE */ @@ -1611,7 +1611,7 @@ brw_ELSE(struct brw_codegen *p) brw_set_src1(p, insn, brw_imm_d(0x0)); } else if (devinfo->ver == 6) { brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_gen6_jump_count(devinfo, insn, 0); + brw_inst_set_gfx6_jump_count(devinfo, insn, 0); brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); } else if (devinfo->ver == 7) { @@ -1707,10 +1707,10 @@ brw_ENDIF(struct brw_codegen *p) /* Also pop item off the stack in the endif instruction: */ if (devinfo->ver < 6) { - brw_inst_set_gen4_jump_count(devinfo, insn, 0); - brw_inst_set_gen4_pop_count(devinfo, insn, 1); + brw_inst_set_gfx4_jump_count(devinfo, insn, 0); + brw_inst_set_gfx4_pop_count(devinfo, insn, 1); } else if (devinfo->ver == 6) { - brw_inst_set_gen6_jump_count(devinfo, insn, 2); + brw_inst_set_gfx6_jump_count(devinfo, insn, 2); } else { brw_inst_set_jip(devinfo, insn, 2); } @@ -1735,7 +1735,7 @@ brw_BREAK(struct brw_codegen *p) brw_set_dest(p, insn, brw_ip_reg()); brw_set_src0(p, insn, brw_ip_reg()); brw_set_src1(p, insn, brw_imm_d(0x0)); - brw_inst_set_gen4_pop_count(devinfo, insn, + brw_inst_set_gfx4_pop_count(devinfo, insn, p->if_depth_in_loop[p->loop_stack_depth]); } brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); @@ -1760,7 +1760,7 @@ brw_CONT(struct brw_codegen *p) } if (devinfo->ver < 6) { - brw_inst_set_gen4_pop_count(devinfo, insn, + brw_inst_set_gfx4_pop_count(devinfo, insn, p->if_depth_in_loop[p->loop_stack_depth]); } brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE); @@ -1806,11 +1806,11 @@ brw_HALT(struct brw_codegen *p) * For uniform control flow, the WHILE is just a jump, so ADD ip, ip, * jip and no DO instruction. * - * For non-uniform control flow pre-gen6, there's a DO instruction to + * For non-uniform control flow pre-gfx6, there's a DO instruction to * push the mask, and a WHILE to jump back, and BREAK to get out and * pop the mask. * - * For gen6, there's no more mask stack, so no need for DO. WHILE + * For gfx6, there's no more mask stack, so no need for DO. WHILE * just points back to the first instruction of the loop. */ brw_inst * @@ -1841,10 +1841,10 @@ brw_DO(struct brw_codegen *p, unsigned execute_size) } /** - * For pre-gen6, we patch BREAK/CONT instructions to point at the WHILE + * For pre-gfx6, we patch BREAK/CONT instructions to point at the WHILE * instruction here. * - * For gen6+, see brw_set_uip_jip(), which doesn't care so much about the loop + * For gfx6+, see brw_set_uip_jip(), which doesn't care so much about the loop * nesting, since it can always just point to the end of the block/current loop. */ static void @@ -1863,11 +1863,11 @@ brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst) * patching. */ if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_BREAK && - brw_inst_gen4_jump_count(devinfo, inst) == 0) { - brw_inst_set_gen4_jump_count(devinfo, inst, br*((while_inst - inst) + 1)); + brw_inst_gfx4_jump_count(devinfo, inst) == 0) { + brw_inst_set_gfx4_jump_count(devinfo, inst, br*((while_inst - inst) + 1)); } else if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_CONTINUE && - brw_inst_gen4_jump_count(devinfo, inst) == 0) { - brw_inst_set_gen4_jump_count(devinfo, inst, br * (while_inst - inst)); + brw_inst_gfx4_jump_count(devinfo, inst) == 0) { + brw_inst_set_gfx4_jump_count(devinfo, inst, br * (while_inst - inst)); } } } @@ -1895,7 +1895,7 @@ brw_WHILE(struct brw_codegen *p) brw_inst_set_jip(devinfo, insn, br * (do_insn - insn)); } else { brw_set_dest(p, insn, brw_imm_w(0)); - brw_inst_set_gen6_jump_count(devinfo, insn, br * (do_insn - insn)); + brw_inst_set_gfx6_jump_count(devinfo, insn, br * (do_insn - insn)); brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); } @@ -1922,8 +1922,8 @@ brw_WHILE(struct brw_codegen *p) brw_set_src1(p, insn, brw_imm_d(0)); brw_inst_set_exec_size(devinfo, insn, brw_inst_exec_size(devinfo, do_insn)); - brw_inst_set_gen4_jump_count(devinfo, insn, br * (do_insn - insn + 1)); - brw_inst_set_gen4_pop_count(devinfo, insn, 0); + brw_inst_set_gfx4_jump_count(devinfo, insn, br * (do_insn - insn + 1)); + brw_inst_set_gfx4_pop_count(devinfo, insn, 0); brw_patch_break_cont(p, insn); } @@ -1949,7 +1949,7 @@ void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx) assert(brw_inst_opcode(devinfo, jmp_insn) == BRW_OPCODE_JMPI); assert(brw_inst_src1_reg_file(devinfo, jmp_insn) == BRW_IMMEDIATE_VALUE); - brw_inst_set_gen4_jump_count(devinfo, jmp_insn, + brw_inst_set_gfx4_jump_count(devinfo, jmp_insn, jmpi * (p->nr_insn - jmp_insn_idx - 1)); } @@ -2022,7 +2022,7 @@ void brw_CMPN(struct brw_codegen *p, /** Extended math function, float[8]. */ -void gen4_math(struct brw_codegen *p, +void gfx4_math(struct brw_codegen *p, struct brw_reg dest, unsigned function, unsigned msg_reg_nr, @@ -2056,7 +2056,7 @@ void gen4_math(struct brw_codegen *p, data_type); } -void gen6_math(struct brw_codegen *p, +void gfx6_math(struct brw_codegen *p, struct brw_reg dest, unsigned function, struct brw_reg src0, @@ -2190,13 +2190,13 @@ void brw_oword_block_write_scratch(struct brw_codegen *p, if (devinfo->ver < 6) brw_inst_set_base_mrf(devinfo, insn, mrf.nr); - /* Until gen6, writes followed by reads from the same location + /* Until gfx6, writes followed by reads from the same location * are not guaranteed to be ordered unless write_commit is set. * If set, then a no-op write is issued to the destination * register to set a dependency, and a read from the destination * can be used to ensure the ordering. * - * For gen6, only writes between different threads need ordering + * For gfx6, only writes between different threads need ordering * protection. Our use of DP writes is all about register * spilling within a thread. */ @@ -2313,7 +2313,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p, } void -gen7_block_read_scratch(struct brw_codegen *p, +gfx7_block_read_scratch(struct brw_codegen *p, struct brw_reg dest, int num_regs, unsigned offset) @@ -2335,7 +2335,7 @@ gen7_block_read_scratch(struct brw_codegen *p, offset /= REG_SIZE; assert(offset < (1 << 12)); - gen7_set_dp_scratch_message(p, insn, + gfx7_set_dp_scratch_message(p, insn, false, /* scratch read */ false, /* OWords */ false, /* invalidate after read */ @@ -2477,7 +2477,7 @@ brw_fb_WRITE(struct brw_codegen *p, } brw_inst * -gen9_fb_READ(struct brw_codegen *p, +gfx9_fb_READ(struct brw_codegen *p, struct brw_reg dst, struct brw_reg payload, unsigned binding_table_index, @@ -2528,7 +2528,7 @@ void brw_SAMPLE(struct brw_codegen *p, brw_inst *insn; if (msg_reg_nr != -1) - gen6_resolve_implied_move(p, &src0, msg_reg_nr); + gfx6_resolve_implied_move(p, &src0, msg_reg_nr); insn = next_insn(p, BRW_OPCODE_SEND); brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER); @@ -2626,7 +2626,7 @@ void brw_urb_WRITE(struct brw_codegen *p, const struct gen_device_info *devinfo = p->devinfo; brw_inst *insn; - gen6_resolve_implied_move(p, &src0, msg_reg_nr); + gfx6_resolve_implied_move(p, &src0, msg_reg_nr); if (devinfo->ver >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) { /* Enable Channel Masks in the URB_WRITE_HWORD message header */ @@ -2873,7 +2873,7 @@ while_jumps_before_offset(const struct gen_device_info *devinfo, brw_inst *insn, int while_offset, int start_offset) { int scale = 16 / brw_jump_scale(devinfo); - int jip = devinfo->ver == 6 ? brw_inst_gen6_jump_count(devinfo, insn) + int jip = devinfo->ver == 6 ? brw_inst_gfx6_jump_count(devinfo, insn) : brw_inst_jip(devinfo, insn); assert(jip < 0); return while_offset + jip * scale <= start_offset; @@ -2922,7 +2922,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset) return 0; } -/* There is no DO instruction on gen6, so to find the end of the loop +/* There is no DO instruction on gfx6, so to find the end of the loop * we have to see if the loop is jumping back before our start * instruction. */ @@ -2997,7 +2997,7 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset) if (devinfo->ver >= 7) brw_inst_set_jip(devinfo, insn, jump); else - brw_inst_set_gen6_jump_count(devinfo, insn, jump); + brw_inst_set_gfx6_jump_count(devinfo, insn, jump); break; } @@ -3039,7 +3039,7 @@ void brw_ff_sync(struct brw_codegen *p, const struct gen_device_info *devinfo = p->devinfo; brw_inst *insn; - gen6_resolve_implied_move(p, &src0, msg_reg_nr); + gfx6_resolve_implied_move(p, &src0, msg_reg_nr); insn = next_insn(p, BRW_OPCODE_SEND); brw_set_dest(p, insn, dest); @@ -3082,7 +3082,7 @@ brw_svb_write(struct brw_codegen *p, BRW_SFID_DATAPORT_WRITE); brw_inst *insn; - gen6_resolve_implied_move(p, &src0, msg_reg_nr); + gfx6_resolve_implied_move(p, &src0, msg_reg_nr); insn = next_insn(p, BRW_OPCODE_SEND); brw_inst_set_sfid(devinfo, insn, target_cache); diff --git a/src/intel/compiler/brw_eu_util.c b/src/intel/compiler/brw_eu_util.c index 31c21a49723..9fc8ff9c7c7 100644 --- a/src/intel/compiler/brw_eu_util.c +++ b/src/intel/compiler/brw_eu_util.c @@ -38,7 +38,7 @@ void brw_math_invert( struct brw_codegen *p, struct brw_reg dst, struct brw_reg src) { - gen4_math(p, + gfx4_math(p, dst, BRW_MATH_FUNCTION_INV, 0, diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index a031fe5bd84..0e4b4dda552 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -1628,7 +1628,7 @@ region_alignment_rules(const struct gen_device_info *devinfo, * destination must be an integer DWord, the hardware allows at least a * float destination type as well. We emit such instructions from * - * fs_visitor::emit_interpolation_setup_gen6 + * fs_visitor::emit_interpolation_setup_gfx6 * fs_visitor::emit_fragcoord_interpolation * * and have for years with no ill effects. diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 117c659874a..02869c0151b 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -411,7 +411,7 @@ fs_inst::has_source_and_destination_hazard() const * * Now our destination for the first instruction overwrote the * second instruction's src0, and we get garbage for those 8 - * pixels. There's a similar issue for the pre-gen6 + * pixels. There's a similar issue for the pre-gfx6 * pixel_x/pixel_y, which are registers of 16-bit values and thus * would get stomped by the first decode as well. */ @@ -1490,10 +1490,10 @@ fs_visitor::emit_sampleid_setup() * can assume 4x MSAA. Disallow it on IVB+ * * FINISHME: One day, we could come up with a way to do this that - * actually works on gen7. + * actually works on gfx7. */ if (devinfo->ver >= 7) - limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7"); + limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gfx7"); abld.exec_all().group(8, 0).MOV(t2, brw_imm_v(0x32103210)); /* This special instruction takes care of setting vstride=1, @@ -3221,7 +3221,7 @@ fs_visitor::compute_to_mrf() break; if (devinfo->ver == 6) { - /* gen6 math instructions must have the destination be + /* gfx6 math instructions must have the destination be * GRF, so no compute-to-MRF for them. */ if (scan_inst->is_math()) { @@ -3626,7 +3626,7 @@ clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len) * same time that both consider ‘r3’ as the target of their final writes. */ void -fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t *block, +fs_visitor::insert_gfx4_pre_send_dependency_workarounds(bblock_t *block, fs_inst *inst) { int write_len = regs_written(inst); @@ -3698,7 +3698,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t *block, * instruction with a different destination register. */ void -fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_inst *inst) +fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_inst *inst) { int write_len = regs_written(inst); unsigned first_write_grf = inst->dst.nr; @@ -3748,7 +3748,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins } void -fs_visitor::insert_gen4_send_dependency_workarounds() +fs_visitor::insert_gfx4_send_dependency_workarounds() { if (devinfo->ver != 4 || devinfo->is_g4x) return; @@ -3757,8 +3757,8 @@ fs_visitor::insert_gen4_send_dependency_workarounds() foreach_block_and_inst(block, fs_inst, inst, cfg) { if (inst->mlen != 0 && inst->dst.file == VGRF) { - insert_gen4_pre_send_dependency_workarounds(block, inst); - insert_gen4_post_send_dependency_workarounds(block, inst); + insert_gfx4_pre_send_dependency_workarounds(block, inst); + insert_gfx4_post_send_dependency_workarounds(block, inst); progress = true; } } @@ -4476,13 +4476,13 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, unsigned length = 0; if (devinfo->ver < 6) { - /* TODO: Support SIMD32 on gen4-5 */ + /* TODO: Support SIMD32 on gfx4-5 */ assert(bld.group() < 16); - /* For gen4-5, we always have a header consisting of g0 and g1. We have + /* For gfx4-5, we always have a header consisting of g0 and g1. We have * an implied MOV from g0,g1 to the start of the message. The MOV from * g0 is handled by the hardware and the MOV from g1 is provided by the - * generator. This is required because, on gen4-5, the generator may + * generator. This is required because, on gfx4-5, the generator may * generate two write messages with different message lengths in order * to handle AA data properly. * @@ -4634,8 +4634,8 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, assert(devinfo->ver >= 9); assert(bld.dispatch_width() == 8); - /* XXX: src_stencil is only available on gen9+. dst_depth is never - * available on gen9+. As such it's impossible to have both enabled at the + /* XXX: src_stencil is only available on gfx9+. dst_depth is never + * available on gfx9+. As such it's impossible to have both enabled at the * same time and therefore length cannot overrun the array. */ assert(length < 15); @@ -4752,7 +4752,7 @@ lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst) } static void -lower_sampler_logical_send_gen4(const fs_builder &bld, fs_inst *inst, opcode op, +lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op, const fs_reg &coordinate, const fs_reg &shadow_c, const fs_reg &lod, const fs_reg &lod2, @@ -4859,7 +4859,7 @@ lower_sampler_logical_send_gen4(const fs_builder &bld, fs_inst *inst, opcode op, } static void -lower_sampler_logical_send_gen5(const fs_builder &bld, fs_inst *inst, opcode op, +lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op, const fs_reg &coordinate, const fs_reg &shadow_c, const fs_reg &lod, const fs_reg &lod2, @@ -5025,7 +5025,7 @@ sampler_msg_type(const gen_device_info *devinfo, } static void -lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op, +lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, const fs_reg &coordinate, const fs_reg &shadow_c, fs_reg lod, const fs_reg &lod2, @@ -5336,7 +5336,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op, sampler.file == IMM ? sampler.ud % 16 : 0, msg_type, simd_mode, - 0 /* return_format unused on gen7+ */); + 0 /* return_format unused on gfx7+ */); inst->src[0] = brw_imm_ud(0); inst->src[1] = brw_imm_ud(0); /* ex_desc */ } else if (surface_handle.file != BAD_FILE) { @@ -5347,7 +5347,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op, sampler.file == IMM ? sampler.ud % 16 : 0, msg_type, simd_mode, - 0 /* return_format unused on gen7+ */); + 0 /* return_format unused on gfx7+ */); /* For bindless samplers, the entire address is included in the message * header so we can leave the portion in the message descriptor 0. @@ -5372,7 +5372,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op, 0, /* sampler */ msg_type, simd_mode, - 0 /* return_format unused on gen7+ */); + 0 /* return_format unused on gfx7+ */); const fs_builder ubld = bld.group(1, 0).exec_all(); fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); if (surface.equals(sampler)) { @@ -5435,7 +5435,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) const unsigned grad_components = inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud; if (devinfo->ver >= 7) { - lower_sampler_logical_send_gen7(bld, inst, op, coordinate, + lower_sampler_logical_send_gfx7(bld, inst, op, coordinate, shadow_c, lod, lod2, min_lod, sample_index, mcs, surface, sampler, @@ -5443,12 +5443,12 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) tg4_offset, coord_components, grad_components); } else if (devinfo->ver >= 5) { - lower_sampler_logical_send_gen5(bld, inst, op, coordinate, + lower_sampler_logical_send_gfx5(bld, inst, op, coordinate, shadow_c, lod, lod2, sample_index, surface, sampler, coord_components, grad_components); } else { - lower_sampler_logical_send_gen4(bld, inst, op, coordinate, + lower_sampler_logical_send_gfx4(bld, inst, op, coordinate, shadow_c, lod, lod2, surface, sampler, coord_components, grad_components); @@ -5598,7 +5598,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) unsigned mlen, ex_mlen = 0; if (devinfo->ver >= 9 && (src.file == BAD_FILE || header.file == BAD_FILE)) { - /* We have split sends on gen9 and above */ + /* We have split sends on gfx9 and above */ if (header.file == BAD_FILE) { payload = bld.move_to_vgrf(addr, addr_sz); payload2 = bld.move_to_vgrf(src, src_sz); @@ -6431,7 +6431,7 @@ static bool is_mixed_float_with_fp32_dst(const fs_inst *inst) { /* This opcode sometimes uses :W type on the source even if the operand is - * a :HF, because in gen7 there is no support for :HF, and thus it uses :W. + * a :HF, because in gfx7 there is no support for :HF, and thus it uses :W. */ if (inst->opcode == BRW_OPCODE_F16TO32) return true; @@ -6451,7 +6451,7 @@ static bool is_mixed_float_with_packed_fp16_dst(const fs_inst *inst) { /* This opcode sometimes uses :W type on the destination even if the - * destination is a :HF, because in gen7 there is no support for :HF, and + * destination is a :HF, because in gfx7 there is no support for :HF, and * thus it uses :W. */ if (inst->opcode == BRW_OPCODE_F32TO16 && @@ -7669,7 +7669,7 @@ fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) con } void -fs_visitor::setup_fs_payload_gen6() +fs_visitor::setup_fs_payload_gfx6() { assert(stage == MESA_SHADER_FRAGMENT); struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); @@ -8276,7 +8276,7 @@ fs_visitor::allocate_registers(bool allow_spilling) * it inserts dead code that happens to have side effects, and it does * so based on the actual physical registers in use. */ - insert_gen4_send_dependency_workarounds(); + insert_gfx4_send_dependency_workarounds(); if (failed) return; @@ -8574,7 +8574,7 @@ fs_visitor::run_gs() * overhead. */ static void -gen9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data) +gfx9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data) { if (wm_prog_data->num_varying_inputs) return; @@ -8597,9 +8597,9 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) assert(stage == MESA_SHADER_FRAGMENT); if (devinfo->ver >= 6) - setup_fs_payload_gen6(); + setup_fs_payload_gfx6(); else - setup_fs_payload_gen4(); + setup_fs_payload_gfx4(); if (0) { emit_dummy_fs(); @@ -8614,9 +8614,9 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) || (nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) { if (devinfo->ver < 6) - emit_interpolation_setup_gen4(); + emit_interpolation_setup_gfx4(); else - emit_interpolation_setup_gen6(); + emit_interpolation_setup_gfx6(); } /* We handle discards by keeping track of the still-live pixels in f0.1. @@ -8657,7 +8657,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) assign_curb_setup(); if (devinfo->ver >= 9) - gen9_ps_header_only_workaround(wm_prog_data); + gfx9_ps_header_only_workaround(wm_prog_data); assign_urb_setup(); @@ -9044,7 +9044,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader, } /** - * Pre-gen6, the register file of the EUs was shared between threads, + * Pre-gfx6, the register file of the EUs was shared between threads, * and each thread used some subset allocated on a 16-register block * granularity. The unit states wanted these block counts. */ @@ -9121,13 +9121,13 @@ brw_compile_fs(const struct brw_compiler *compiler, allow_spilling = false; } - /* Limit dispatch width to simd8 with dual source blending on gen8. + /* Limit dispatch width to simd8 with dual source blending on gfx8. * See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917 */ if (devinfo->ver == 8 && prog_data->dual_src_blend && !(INTEL_DEBUG & DEBUG_NO8)) { assert(!params->use_rep_send); - v8->limit_dispatch_width(8, "gen8 workaround: " + v8->limit_dispatch_width(8, "gfx8 workaround: " "using SIMD8 when dual src blending.\n"); } diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 8cebf4c9b35..eb6e46507f0 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -132,8 +132,8 @@ public: bool run_bs(bool allow_spilling); void optimize(); void allocate_registers(bool allow_spilling); - void setup_fs_payload_gen4(); - void setup_fs_payload_gen6(); + void setup_fs_payload_gfx4(); + void setup_fs_payload_gfx6(); void setup_vs_payload(); void setup_gs_payload(); void setup_cs_payload(); @@ -180,10 +180,10 @@ public: bool remove_extra_rounding_modes(); void schedule_instructions(instruction_scheduler_mode mode); - void insert_gen4_send_dependency_workarounds(); - void insert_gen4_pre_send_dependency_workarounds(bblock_t *block, + void insert_gfx4_send_dependency_workarounds(); + void insert_gfx4_pre_send_dependency_workarounds(bblock_t *block, fs_inst *inst); - void insert_gen4_post_send_dependency_workarounds(bblock_t *block, + void insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_inst *inst); void vfail(const char *msg, va_list args); void fail(const char *msg, ...); @@ -208,13 +208,13 @@ public: fs_reg *emit_samplepos_setup(); fs_reg *emit_sampleid_setup(); fs_reg *emit_samplemaskin_setup(); - void emit_interpolation_setup_gen4(); - void emit_interpolation_setup_gen6(); + void emit_interpolation_setup_gfx4(); + void emit_interpolation_setup_gfx6(); void compute_sample_position(fs_reg dst, fs_reg int_sample_pos); fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components, const fs_reg &texture, const fs_reg &texture_handle); - void emit_gen6_gather_wa(uint8_t wa, fs_reg dst); + void emit_gfx6_gather_wa(uint8_t wa, fs_reg dst); fs_reg resolve_source_modifiers(const fs_reg &src); void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr, fs_reg result, fs_reg *op, unsigned fsign_src); @@ -513,16 +513,16 @@ private: struct brw_reg dst, struct brw_reg src); void generate_scratch_write(fs_inst *inst, struct brw_reg src); void generate_scratch_read(fs_inst *inst, struct brw_reg dst); - void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst); + void generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst); void generate_scratch_header(fs_inst *inst, struct brw_reg dst); void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg offset); - void generate_uniform_pull_constant_load_gen7(fs_inst *inst, + void generate_uniform_pull_constant_load_gfx7(fs_inst *inst, struct brw_reg dst, struct brw_reg surf_index, struct brw_reg payload); - void generate_varying_pull_constant_load_gen4(fs_inst *inst, + void generate_varying_pull_constant_load_gfx4(fs_inst *inst, struct brw_reg dst, struct brw_reg index); void generate_mov_dispatch_to_flags(fs_inst *inst); diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 96841a5fd83..7f418041b8f 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -663,7 +663,7 @@ namespace brw { * * CMP null src0 src1 * - * Original gen4 does type conversion to the destination type + * Original gfx4 does type conversion to the destination type * before comparison, producing garbage results for floating * point comparisons. * @@ -688,7 +688,7 @@ namespace brw { * * CMP null src0 src1 * - * Original gen4 does type conversion to the destination type + * Original gfx4 does type conversion to the destination type * before comparison, producing garbage results for floating * point comparisons. * @@ -844,7 +844,7 @@ namespace brw { src_reg fix_math_operand(const src_reg &src) const { - /* Can't do hstride == 0 args on gen6 math, so expand it out. We + /* Can't do hstride == 0 args on gfx6 math, so expand it out. We * might be able to do better by doing execsize = 1 math and then * expanding that result out, but we would need to be careful with * masking. diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 866ed788ce9..63858252e24 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -446,7 +446,7 @@ fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst, /* We assume that render targets start at binding table index 0. */ const unsigned surf_index = inst->target; - gen9_fb_READ(p, dst, payload, surf_index, + gfx9_fb_READ(p, dst, payload, surf_index, inst->header_size, inst->size_written / REG_SIZE, prog_data->persample_dispatch); } @@ -609,7 +609,7 @@ fs_generator::generate_shuffle(fs_inst *inst, assert(devinfo->ver >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4); /* Because we're using the address register, we're limited to 8-wide - * execution on gen7. On gen8, we're limited to 16-wide by the address + * execution on gfx7. On gfx8, we're limited to 16-wide by the address * register file and 8-wide for 64-bit types. We could try and make this * instruction splittable higher up in the compiler but that gets weird * because it reads all of the channels regardless of execution size. It's @@ -946,7 +946,7 @@ fs_generator::generate_linterp(fs_inst *inst, * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16 * ----------------------------------- * - * See also: emit_interpolation_setup_gen4(). + * See also: emit_interpolation_setup_gfx4(). */ struct brw_reg delta_x = src[0]; struct brw_reg delta_y = offset(src[0], inst->exec_size / 8); @@ -954,7 +954,7 @@ fs_generator::generate_linterp(fs_inst *inst, brw_inst *i[2]; /* nir_lower_interpolation() will do the lowering to MAD instructions for - * us on gen11+ + * us on gfx11+ */ assert(devinfo->ver < 11); @@ -968,7 +968,7 @@ fs_generator::generate_linterp(fs_inst *inst, * * This means that we need to split PLN into LINE+MAC on-the-fly. * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so - * we have to split into SIMD8 pieces. For gen4 (!has_pln), the + * we have to split into SIMD8 pieces. For gfx4 (!has_pln), the * coordinate registers are laid out differently so we leave it as a * SIMD16 instruction. */ @@ -986,7 +986,7 @@ fs_generator::generate_linterp(fs_inst *inst, offset(delta_x, g * 2)); brw_inst_set_group(devinfo, line, inst->group + g * 8); - /* LINE writes the accumulator automatically on gen4-5. On Sandy + /* LINE writes the accumulator automatically on gfx4-5. On Sandy * Bridge and later, we have to explicitly enable it. */ if (devinfo->ver >= 6) @@ -1101,11 +1101,11 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, } /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type - * is set as part of the message descriptor. On gen4, the PRM seems to + * is set as part of the message descriptor. On gfx4, the PRM seems to * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is * gone from the message descriptor entirely and you just get UINT32 all - * the time regasrdless. Since we can really only do non-UINT32 on gen4, + * the time regasrdless. Since we can really only do non-UINT32 on gfx4, * just stomp it to UINT32 all the time. */ if (inst->opcode == SHADER_OPCODE_TXS) @@ -1369,7 +1369,7 @@ fs_generator::generate_ddx(const fs_inst *inst, * correctly for compressed instructions. At least on Haswell and * Iron Lake, compressed ALIGN16 instructions do work. Since we * would have to split to SIMD8 no matter which method we choose, we - * may as well use ALIGN16 on all platforms gen7 and earlier. + * may as well use ALIGN16 on all platforms gfx7 and earlier. */ struct brw_reg src0 = stride(src, 4, 4, 1); struct brw_reg src1 = stride(src, 4, 4, 1); @@ -1449,7 +1449,7 @@ fs_generator::generate_ddy(const fs_inst *inst, * correctly for compressed instructions. At least on Haswell and * Iron Lake, compressed ALIGN16 instructions do work. Since we * would have to split to SIMD8 no matter which method we choose, we - * may as well use ALIGN16 on all platforms gen7 and earlier. + * may as well use ALIGN16 on all platforms gfx7 and earlier. */ struct brw_reg src0 = stride(src, 4, 4, 1); struct brw_reg src1 = stride(src, 4, 4, 1); @@ -1526,11 +1526,11 @@ fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst) } void -fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst) +fs_generator::generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst) { assert(inst->exec_size <= 16 || inst->force_writemask_all); - gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset); + gfx7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset); } /* The A32 messages take a buffer base address in header.5:[31:0] (See @@ -1625,7 +1625,7 @@ fs_generator::generate_uniform_pull_constant_load(fs_inst *inst, } void -fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, +fs_generator::generate_uniform_pull_constant_load_gfx7(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg payload) @@ -1687,11 +1687,11 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, } void -fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst, +fs_generator::generate_varying_pull_constant_load_gfx4(fs_inst *inst, struct brw_reg dst, struct brw_reg index) { - assert(devinfo->ver < 7); /* Should use the gen7 variant. */ + assert(devinfo->ver < 7); /* Should use the gfx7 variant. */ assert(inst->header_size != 0); assert(inst->mlen); @@ -1723,7 +1723,7 @@ fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst, } struct brw_reg header = brw_vec8_grf(0, 0); - gen6_resolve_implied_move(p, &header, inst->base_mrf); + gfx6_resolve_implied_move(p, &header, inst->base_mrf); brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); brw_inst_set_compression(devinfo, send, false); @@ -2000,7 +2000,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_set_default_access_mode(p, BRW_ALIGN_1); brw_set_default_predicate_control(p, inst->predicate); brw_set_default_predicate_inverse(p, inst->predicate_inverse); - /* On gen7 and above, hardware automatically adds the group onto the + /* On gfx7 and above, hardware automatically adds the group onto the * flag subregister number. On Sandy Bridge and older, we have to do it * ourselves. */ @@ -2203,9 +2203,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, case BRW_OPCODE_IF: if (inst->src[0].file != BAD_FILE) { - /* The instruction has an embedded compare (only allowed on gen6) */ + /* The instruction has an embedded compare (only allowed on gfx6) */ assert(devinfo->ver == 6); - gen6_IF(p, inst->conditional_mod, src[0], src[1]); + gfx6_IF(p, inst->conditional_mod, src[0], src[1]); } else { brw_IF(p, brw_get_default_exec_size(p)); } @@ -2245,12 +2245,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, if (devinfo->ver >= 6) { assert(inst->mlen == 0); assert(devinfo->ver >= 7 || inst->exec_size == 8); - gen6_math(p, dst, brw_math_function(inst->opcode), + gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], brw_null_reg()); } else { assert(inst->mlen >= 1); assert(devinfo->ver == 5 || devinfo->is_g4x || inst->exec_size == 8); - gen4_math(p, dst, + gfx4_math(p, dst, brw_math_function(inst->opcode), inst->base_mrf, src[0], BRW_MATH_PRECISION_FULL); @@ -2265,11 +2265,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, assert(inst->mlen == 0); assert((devinfo->ver >= 7 && inst->opcode == SHADER_OPCODE_POW) || inst->exec_size == 8); - gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); + gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); } else { assert(inst->mlen >= 1); assert(inst->exec_size == 8); - gen4_math(p, dst, brw_math_function(inst->opcode), + gfx4_math(p, dst, brw_math_function(inst->opcode), inst->base_mrf, src[0], BRW_MATH_PRECISION_FULL); send_count++; @@ -2342,7 +2342,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case SHADER_OPCODE_GEN7_SCRATCH_READ: - generate_scratch_read_gen7(inst, dst); + generate_scratch_read_gfx7(inst, dst); fill_count++; break; @@ -2381,12 +2381,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: assert(inst->force_writemask_all); - generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]); + generate_uniform_pull_constant_load_gfx7(inst, dst, src[0], src[1]); send_count++; break; case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: - generate_varying_pull_constant_load_gen4(inst, dst, src[0]); + generate_varying_pull_constant_load_gfx4(inst, dst, src[0]); send_count++; break; diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 35838c3060b..6a9f76570e2 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1030,8 +1030,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, * * But if we want to use that opcode, we need to provide support on * different optimizations and lowerings. As right now HF support is - * only for gen8+, it will be better to use directly the MOV, and use - * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7. + * only for gfx8+, it will be better to use directly the MOV, and use + * BRW_OPCODE_F32TO16 when/if we work for HF support on gfx7. */ assert(type_sz(op[0].type) < 8); /* brw_nir_lower_conversions */ inst = bld.MOV(result, op[0]); @@ -1895,7 +1895,7 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld, case 64: assert(devinfo->ver >= 7); if (devinfo->ver == 7) { - /* We don't get 64-bit integer types until gen8 */ + /* We don't get 64-bit integer types until gfx8 */ for (unsigned i = 0; i < instr->def.num_components; i++) { bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF), setup_imm_df(bld, instr->value[i].f64)); @@ -1933,7 +1933,7 @@ fs_visitor::get_nir_src(const nir_src &src) } if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) { - /* The only 64-bit type available on gen7 is DF, so use that. */ + /* The only 64-bit type available on gfx7 is DF, so use that. */ reg.type = BRW_REGISTER_TYPE_DF; } else { /* To avoid floating-point denorm flushing problems, set the type by @@ -1951,8 +1951,8 @@ fs_visitor::get_nir_src(const nir_src &src) * Return an IMM for constants; otherwise call get_nir_src() as normal. * * This function should not be called on any value which may be 64 bits. - * We could theoretically support 64-bit on gen8+ but we choose not to - * because it wouldn't work in general (no gen7 support) and there are + * We could theoretically support 64-bit on gfx8+ but we choose not to + * because it wouldn't work in general (no gfx7 support) and there are * enough restrictions in 64-bit immediates that you can't take the return * value and treat it the same as the result of get_nir_src(). */ @@ -5187,9 +5187,9 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr const fs_reg tmp = bld.vgrf(value.type); if (devinfo->ver <= 7) { /* The hardware doesn't seem to support these crazy regions with - * compressed instructions on gen7 and earlier so we fall back to + * compressed instructions on gfx7 and earlier so we fall back to * using quad swizzles. Fortunately, we don't support 64-bit - * anything in Vulkan on gen7. + * anything in Vulkan on gfx7. */ assert(nir_src_bit_size(instr->src[0]) == 32); const fs_builder ubld = bld.exec_all(); @@ -6033,7 +6033,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) inst->shadow_compare = true; if (instr->op == nir_texop_tg4 && devinfo->ver == 6) - emit_gen6_gather_wa(key_tex->gen6_gather_wa[texture], dst); + emit_gfx6_gather_wa(key_tex->gfx6_gather_wa[texture], dst); fs_reg nir_dest[5]; for (unsigned i = 0; i < dest_size; i++) @@ -6203,7 +6203,7 @@ setup_imm_df(const fs_builder &bld, double v) if (devinfo->ver >= 8) return brw_imm_df(v); - /* gen7.5 does not support DF immediates straighforward but the DIM + /* gfx7.5 does not support DF immediates straighforward but the DIM * instruction allows to set the 64-bit immediate value. */ if (devinfo->is_haswell) { @@ -6213,13 +6213,13 @@ setup_imm_df(const fs_builder &bld, double v) return component(dst, 0); } - /* gen7 does not support DF immediates, so we generate a 64-bit constant by + /* gfx7 does not support DF immediates, so we generate a 64-bit constant by * writing the low 32-bit of the constant to suboffset 0 of a VGRF and * the high 32-bit to suboffset 4 and then applying a stride of 0. * * Alternatively, we could also produce a normal VGRF (without stride 0) * by writing to all the channels in the VGRF, however, that would hit the - * gen7 bug where we have to split writes that span more than 1 register + * gfx7 bug where we have to split writes that span more than 1 register * into instructions with a width of 4 (otherwise the write to the second * register written runs into an execmask hardware bug) which isn't very * nice. diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index f7dd51d2789..36eaf9eb6a5 100644 --- a/src/intel/compiler/brw_fs_reg_allocate.cpp +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp @@ -109,8 +109,8 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) * to write into. We currently always ask for 4 registers, but we may * convert that to use less some day. * - * Additionally, on gen5 we need aligned pairs of registers for the PLN - * instruction, and on gen4 we need 8 contiguous regs for workaround simd16 + * Additionally, on gfx5 we need aligned pairs of registers for the PLN + * instruction, and on gfx4 we need 8 contiguous regs for workaround simd16 * texturing. */ const int class_count = MAX_VGRF_SIZE; @@ -525,7 +525,7 @@ private: * Sets the mrf_used array to indicate which MRFs are used by the shader IR * * This is used in assign_regs() to decide which of the GRFs that we use as - * MRFs on gen7 get normally register allocated, and in register spilling to + * MRFs on gfx7 get normally register allocated, and in register spilling to * see if we can actually use MRFs to do spills without overwriting normal MRF * contents. */ @@ -1140,8 +1140,8 @@ fs_reg_alloc::spill_reg(unsigned spill_reg) /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done * using up to 11 MRFs starting from either m1 or m2, and fb writes can use - * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or - * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst + * up to m13 (gfx6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or + * m15 (gfx4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst * depth), starting from m1. In summary: We may not be able to spill in * SIMD16 mode, because we'd stomp the FB writes. */ diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 85c0071e290..0d00e1a7139 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -63,7 +63,7 @@ fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components, * Apply workarounds for Gen6 gather with UINT/SINT */ void -fs_visitor::emit_gen6_gather_wa(uint8_t wa, fs_reg dst) +fs_visitor::emit_gfx6_gather_wa(uint8_t wa, fs_reg dst) { if (!wa) return; @@ -153,7 +153,7 @@ fs_visitor::interp_reg(int location, int channel) /** Emits the interpolation for the varying inputs. */ void -fs_visitor::emit_interpolation_setup_gen4() +fs_visitor::emit_interpolation_setup_gfx4() { struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); @@ -267,7 +267,7 @@ fs_visitor::emit_shader_float_controls_execution_mode() /** Emits the interpolation for the varying inputs. */ void -fs_visitor::emit_interpolation_setup_gen6() +fs_visitor::emit_interpolation_setup_gfx6() { fs_builder abld = bld.annotate("compute pixel centers"); @@ -318,7 +318,7 @@ fs_visitor::emit_interpolation_setup_gen6() fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)), fs_reg(brw_imm_v(0x11001100))); - /* As of gen6, we can no longer mix float and int sources. We have + /* As of gfx6, we can no longer mix float and int sources. We have * to turn the integer pixel centers into floats for their actual * use. */ @@ -479,7 +479,7 @@ fs_visitor::emit_fb_writes() fs_inst *inst = NULL; if (source_depth_to_render_target && devinfo->ver == 6) { - /* For outputting oDepth on gen6, SIMD8 writes have to be used. This + /* For outputting oDepth on gfx6, SIMD8 writes have to be used. This * would require SIMD8 moves of each half to message regs, e.g. by using * the SIMD lowering pass. Unfortunately this is more difficult than it * sounds because the SIMD8 single-source message lacks channel selects diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 1d4fccfd676..424a02e6f6e 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -123,16 +123,16 @@ brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \ } /* A macro for fields which moved as of Gen8+. */ -#define F8(name, gen4_high, gen4_low, gen8_high, gen8_low, \ - gen12_high, gen12_low) \ +#define F8(name, gfx4_high, gfx4_low, gfx8_high, gfx8_low, \ + gfx12_high, gfx12_low) \ FF(name, \ - /* 4: */ gen4_high, gen4_low, \ - /* 4.5: */ gen4_high, gen4_low, \ - /* 5: */ gen4_high, gen4_low, \ - /* 6: */ gen4_high, gen4_low, \ - /* 7: */ gen4_high, gen4_low, \ - /* 8: */ gen8_high, gen8_low, \ - /* 12: */ gen12_high, gen12_low); + /* 4: */ gfx4_high, gfx4_low, \ + /* 4.5: */ gfx4_high, gfx4_low, \ + /* 5: */ gfx4_high, gfx4_low, \ + /* 6: */ gfx4_high, gfx4_low, \ + /* 7: */ gfx4_high, gfx4_low, \ + /* 8: */ gfx8_high, gfx8_low, \ + /* 12: */ gfx12_high, gfx12_low); /* Macro for fields that gained extra discontiguous MSBs in Gen12 (specified * by hi12ex-lo12ex). @@ -444,8 +444,8 @@ static inline void \ brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \ brw_inst *inst, enum brw_reg_type type) \ { \ - UNUSED enum gen10_align1_3src_exec_type exec_type = \ - (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ + UNUSED enum gfx10_align1_3src_exec_type exec_type = \ + (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ inst); \ if (brw_reg_type_is_floating_point(type)) { \ assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ @@ -460,8 +460,8 @@ static inline enum brw_reg_type \ brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \ const brw_inst *inst) \ { \ - enum gen10_align1_3src_exec_type exec_type = \ - (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ + enum gfx10_align1_3src_exec_type exec_type = \ + (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ inst); \ unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \ return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ @@ -603,9 +603,9 @@ brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \ return brw_inst_bits(inst, high, low); \ } -FJ(gen6_jump_count, 63, 48, devinfo->ver == 6) -FJ(gen4_jump_count, 111, 96, devinfo->ver < 6) -FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->ver < 6) +FJ(gfx6_jump_count, 63, 48, devinfo->ver == 6) +FJ(gfx4_jump_count, 111, 96, devinfo->ver < 6) +FC(gfx4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->ver < 6) /** @} */ /** @@ -1354,14 +1354,14 @@ brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, inst->data = (inst->data & ~mask) | (value << low); } -#define FC(name, high, low, gen12_high, gen12_low, assertions) \ +#define FC(name, high, low, gfx12_high, gfx12_low, assertions) \ static inline void \ brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \ brw_compact_inst *inst, unsigned v) \ { \ assert(assertions); \ if (devinfo->ver >= 12) \ - brw_compact_inst_set_bits(inst, gen12_high, gen12_low, v); \ + brw_compact_inst_set_bits(inst, gfx12_high, gfx12_low, v); \ else \ brw_compact_inst_set_bits(inst, high, low, v); \ } \ @@ -1371,7 +1371,7 @@ brw_compact_inst_##name(const struct gen_device_info *devinfo, \ { \ assert(assertions); \ if (devinfo->ver >= 12) \ - return brw_compact_inst_bits(inst, gen12_high, gen12_low); \ + return brw_compact_inst_bits(inst, gfx12_high, gfx12_low); \ else \ return brw_compact_inst_bits(inst, high, low); \ } @@ -1379,8 +1379,8 @@ brw_compact_inst_##name(const struct gen_device_info *devinfo, \ /* A simple macro for fields which stay in the same place on all generations * except for Gen12. */ -#define F(name, high, low, gen12_high, gen12_low) \ - FC(name, high, low, gen12_high, gen12_low, true) +#define F(name, high, low, gfx12_high, gfx12_low) \ + FC(name, high, low, gfx12_high, gfx12_low, true) F(src1_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) F(src0_reg_nr, /* 4+ */ 55, 48, /* 12+ */ 47, 40) diff --git a/src/intel/compiler/brw_interpolation_map.c b/src/intel/compiler/brw_interpolation_map.c index 7759f06dbc9..a1e3170e668 100644 --- a/src/intel/compiler/brw_interpolation_map.c +++ b/src/intel/compiler/brw_interpolation_map.c @@ -36,7 +36,7 @@ static char const *get_qual_name(int mode) } static void -gen4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, +gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, const struct brw_vue_map *vue_map, unsigned location, unsigned slot_count, enum glsl_interp_mode interp) @@ -79,12 +79,12 @@ brw_setup_vue_interpolation(const struct brw_vue_map *vue_map, nir_shader *nir, unsigned location = var->data.location; unsigned slot_count = glsl_count_attribute_slots(var->type, false); - gen4_frag_prog_set_interp_modes(prog_data, vue_map, location, slot_count, + gfx4_frag_prog_set_interp_modes(prog_data, vue_map, location, slot_count, var->data.interpolation); if (location == VARYING_SLOT_COL0 || location == VARYING_SLOT_COL1) { location = location + VARYING_SLOT_BFC0 - VARYING_SLOT_COL0; - gen4_frag_prog_set_interp_modes(prog_data, vue_map, location, + gfx4_frag_prog_set_interp_modes(prog_data, vue_map, location, slot_count, var->data.interpolation); } } diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h index 3f7d9e3e074..ed6ef034e40 100644 --- a/src/intel/compiler/brw_ir_vec4.h +++ b/src/intel/compiler/brw_ir_vec4.h @@ -281,9 +281,9 @@ public: enum brw_urb_write_flags urb_write_flags; - unsigned sol_binding; /**< gen6: SOL binding table index */ - bool sol_final_write; /**< gen6: send commit message */ - unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */ + unsigned sol_binding; /**< gfx6: SOL binding table index */ + bool sol_final_write; /**< gfx6: send commit message */ + unsigned sol_vertex; /**< gfx6: used for setting dst index in SVB header */ bool is_send_from_grf() const; unsigned size_read(unsigned arg) const; diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 48ff8881a2e..2090426ec41 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -542,8 +542,8 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler, * using nir_lower_vars_to_explicit_types and nir_lower_explicit_io in * brw_postprocess_nir. * - * We haven't plumbed through the indirect scratch messages on gen6 or - * earlier so doing indirects via scratch doesn't work there. On gen7 and + * We haven't plumbed through the indirect scratch messages on gfx6 or + * earlier so doing indirects via scratch doesn't work there. On gfx7 and * earlier the scratch space size is limited to 12kB. If we allowed * indirects as scratch all the time, we may easily exceed this limit * without having any fallback. diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index 35def259f94..f55febc9f88 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -61,7 +61,7 @@ struct gen_device_info; /** * First GRF used for the MRF hack. * - * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We + * On gfx7, MRFs are no longer used, and contiguous GRFs are used instead. We * haven't converted our compiler to be aware of this, so it asks for MRFs and * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The * register allocators have to be careful of this to avoid corrupting the "MRF"s @@ -418,7 +418,7 @@ brw_reg(enum brw_reg_file file, else if (file == BRW_ARCHITECTURE_REGISTER_FILE) assert(nr <= BRW_ARF_TIMESTAMP); /* Asserting on the MRF register number requires to know the hardware gen - * (gen6 has 24 MRF registers), which we don't know here, so we assert + * (gfx6 has 24 MRF registers), which we don't know here, so we assert * for that in the generators and in brw_eu_emit.c */ diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index d99314afe80..b81fde56cf9 100644 --- a/src/intel/compiler/brw_reg_type.c +++ b/src/intel/compiler/brw_reg_type.c @@ -91,7 +91,7 @@ enum hw_imm_type { static const struct hw_type { enum hw_reg_type reg_type; enum hw_imm_type imm_type; -} gen4_hw_type[] = { +} gfx4_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F }, @@ -104,7 +104,7 @@ static const struct hw_type { [BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID }, [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, -}, gen6_hw_type[] = { +}, gfx6_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F }, @@ -118,7 +118,7 @@ static const struct hw_type { [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV }, -}, gen7_hw_type[] = { +}, gfx7_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, [BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, INVALID }, @@ -133,7 +133,7 @@ static const struct hw_type { [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV }, -}, gen8_hw_type[] = { +}, gfx8_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, [BRW_REGISTER_TYPE_DF] = { GFX7_HW_REG_TYPE_DF, GFX8_HW_IMM_TYPE_DF }, @@ -151,7 +151,7 @@ static const struct hw_type { [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID }, [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V }, [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV }, -}, gen11_hw_type[] = { +}, gfx11_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, [BRW_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID }, @@ -167,7 +167,7 @@ static const struct hw_type { [BRW_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID }, [BRW_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V }, [BRW_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV }, -}, gen12_hw_type[] = { +}, gfx12_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, [BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) }, @@ -219,19 +219,19 @@ enum hw_3src_reg_type { static const struct hw_3src_type { enum hw_3src_reg_type reg_type; - enum gen10_align1_3src_exec_type exec_type; -} gen6_hw_3src_type[] = { + enum gfx10_align1_3src_exec_type exec_type; +} gfx6_hw_3src_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, [BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, -}, gen7_hw_3src_type[] = { +}, gfx7_hw_3src_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, [BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, [BRW_REGISTER_TYPE_D] = { GFX7_3SRC_TYPE_D }, [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, [BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF }, -}, gen8_hw_3src_type[] = { +}, gfx8_hw_3src_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, [BRW_REGISTER_TYPE_F] = { GFX7_3SRC_TYPE_F }, @@ -239,7 +239,7 @@ static const struct hw_3src_type { [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, [BRW_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF }, [BRW_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF }, -}, gen10_hw_3src_align1_type[] = { +}, gfx10_hw_3src_align1_type[] = { #define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, @@ -253,7 +253,7 @@ static const struct hw_3src_type { [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) }, [BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) }, [BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) }, -}, gen11_hw_3src_type[] = { +}, gfx11_hw_3src_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, [BRW_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) }, @@ -266,7 +266,7 @@ static const struct hw_3src_type { [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) }, [BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) }, [BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) }, -}, gen12_hw_3src_type[] = { +}, gfx12_hw_3src_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, [BRW_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), }, @@ -294,23 +294,23 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo, const struct hw_type *table; if (devinfo->ver >= 12) { - assert(type < ARRAY_SIZE(gen12_hw_type)); - table = gen12_hw_type; + assert(type < ARRAY_SIZE(gfx12_hw_type)); + table = gfx12_hw_type; } else if (devinfo->ver >= 11) { - assert(type < ARRAY_SIZE(gen11_hw_type)); - table = gen11_hw_type; + assert(type < ARRAY_SIZE(gfx11_hw_type)); + table = gfx11_hw_type; } else if (devinfo->ver >= 8) { - assert(type < ARRAY_SIZE(gen8_hw_type)); - table = gen8_hw_type; + assert(type < ARRAY_SIZE(gfx8_hw_type)); + table = gfx8_hw_type; } else if (devinfo->ver >= 7) { - assert(type < ARRAY_SIZE(gen7_hw_type)); - table = gen7_hw_type; + assert(type < ARRAY_SIZE(gfx7_hw_type)); + table = gfx7_hw_type; } else if (devinfo->ver >= 6) { - assert(type < ARRAY_SIZE(gen6_hw_type)); - table = gen6_hw_type; + assert(type < ARRAY_SIZE(gfx6_hw_type)); + table = gfx6_hw_type; } else { - assert(type < ARRAY_SIZE(gen4_hw_type)); - table = gen4_hw_type; + assert(type < ARRAY_SIZE(gfx4_hw_type)); + table = gfx4_hw_type; } if (file == BRW_IMMEDIATE_VALUE) { @@ -334,17 +334,17 @@ brw_hw_type_to_reg_type(const struct gen_device_info *devinfo, const struct hw_type *table; if (devinfo->ver >= 12) { - table = gen12_hw_type; + table = gfx12_hw_type; } else if (devinfo->ver >= 11) { - table = gen11_hw_type; + table = gfx11_hw_type; } else if (devinfo->ver >= 8) { - table = gen8_hw_type; + table = gfx8_hw_type; } else if (devinfo->ver >= 7) { - table = gen7_hw_type; + table = gfx7_hw_type; } else if (devinfo->ver >= 6) { - table = gen6_hw_type; + table = gfx6_hw_type; } else { - table = gen4_hw_type; + table = gfx4_hw_type; } if (file == BRW_IMMEDIATE_VALUE) { @@ -374,14 +374,14 @@ brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo, const struct hw_3src_type *table; if (devinfo->ver >= 8) { - assert(type < ARRAY_SIZE(gen8_hw_3src_type)); - table = gen8_hw_3src_type; + assert(type < ARRAY_SIZE(gfx8_hw_3src_type)); + table = gfx8_hw_3src_type; } else if (devinfo->ver >= 7) { - assert(type < ARRAY_SIZE(gen7_hw_3src_type)); - table = gen7_hw_3src_type; + assert(type < ARRAY_SIZE(gfx7_hw_3src_type)); + table = gfx7_hw_3src_type; } else { - assert(type < ARRAY_SIZE(gen6_hw_3src_type)); - table = gen6_hw_3src_type; + assert(type < ARRAY_SIZE(gfx6_hw_3src_type)); + table = gfx6_hw_3src_type; } assert(table[type].reg_type != (enum hw_3src_reg_type)INVALID); @@ -397,14 +397,14 @@ brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo, enum brw_reg_type type) { if (devinfo->ver >= 12) { - assert(type < ARRAY_SIZE(gen12_hw_3src_type)); - return gen12_hw_3src_type[type].reg_type; + assert(type < ARRAY_SIZE(gfx12_hw_3src_type)); + return gfx12_hw_3src_type[type].reg_type; } else if (devinfo->ver >= 11) { - assert(type < ARRAY_SIZE(gen11_hw_3src_type)); - return gen11_hw_3src_type[type].reg_type; + assert(type < ARRAY_SIZE(gfx11_hw_3src_type)); + return gfx11_hw_3src_type[type].reg_type; } else { - assert(type < ARRAY_SIZE(gen10_hw_3src_align1_type)); - return gen10_hw_3src_align1_type[type].reg_type; + assert(type < ARRAY_SIZE(gfx10_hw_3src_align1_type)); + return gfx10_hw_3src_align1_type[type].reg_type; } } @@ -419,11 +419,11 @@ brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo, const struct hw_3src_type *table = NULL; if (devinfo->ver >= 8) { - table = gen8_hw_3src_type; + table = gfx8_hw_3src_type; } else if (devinfo->ver >= 7) { - table = gen7_hw_3src_type; + table = gfx7_hw_3src_type; } else if (devinfo->ver >= 6) { - table = gen6_hw_3src_type; + table = gfx6_hw_3src_type; } for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) { @@ -442,9 +442,9 @@ enum brw_reg_type brw_a1_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo, unsigned hw_type, unsigned exec_type) { - const struct hw_3src_type *table = (devinfo->ver >= 12 ? gen12_hw_3src_type : - devinfo->ver >= 11 ? gen11_hw_3src_type : - gen10_hw_3src_align1_type); + const struct hw_3src_type *table = (devinfo->ver >= 12 ? gfx12_hw_3src_type : + devinfo->ver >= 11 ? gfx11_hw_3src_type : + gfx10_hw_3src_align1_type); for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) { if (table[i].reg_type == hw_type && diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 41b36145596..f2dc657fa1e 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -63,8 +63,8 @@ class schedule_node : public exec_node { public: schedule_node(backend_instruction *inst, instruction_scheduler *sched); - void set_latency_gen4(); - void set_latency_gen7(bool is_haswell); + void set_latency_gfx4(); + void set_latency_gfx7(bool is_haswell); backend_instruction *inst; schedule_node **children; @@ -115,7 +115,7 @@ exit_unblocked_time(const schedule_node *n) } void -schedule_node::set_latency_gen4() +schedule_node::set_latency_gfx4() { int chans = 8; int math_latency = 22; @@ -153,7 +153,7 @@ schedule_node::set_latency_gen4() } void -schedule_node::set_latency_gen7(bool is_haswell) +schedule_node::set_latency_gfx7(bool is_haswell) { switch (inst->opcode) { case BRW_OPCODE_MAD: @@ -935,9 +935,9 @@ schedule_node::schedule_node(backend_instruction *inst, if (!sched->post_reg_alloc) this->latency = 1; else if (devinfo->ver >= 6) - set_latency_gen7(devinfo->is_haswell); + set_latency_gfx7(devinfo->is_haswell); else - set_latency_gen4(); + set_latency_gfx4(); } void @@ -1784,7 +1784,7 @@ instruction_scheduler::schedule_instructions(bblock_t *block) cand_generation++; /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+ - * but it's more limited pre-gen6, so if we send something off to it then + * but it's more limited pre-gfx6, so if we send something off to it then * the next math instruction isn't going to make progress until the first * is done. */ diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index b33b7b74d2c..dfe21a5a1ad 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -360,21 +360,21 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) return "pack"; case SHADER_OPCODE_GEN4_SCRATCH_READ: - return "gen4_scratch_read"; + return "gfx4_scratch_read"; case SHADER_OPCODE_GEN4_SCRATCH_WRITE: - return "gen4_scratch_write"; + return "gfx4_scratch_write"; case SHADER_OPCODE_GEN7_SCRATCH_READ: - return "gen7_scratch_read"; + return "gfx7_scratch_read"; case SHADER_OPCODE_SCRATCH_HEADER: return "scratch_header"; case SHADER_OPCODE_URB_WRITE_SIMD8: - return "gen8_urb_write_simd8"; + return "gfx8_urb_write_simd8"; case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT: - return "gen8_urb_write_simd8_per_slot"; + return "gfx8_urb_write_simd8_per_slot"; case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: - return "gen8_urb_write_simd8_masked"; + return "gfx8_urb_write_simd8_masked"; case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: - return "gen8_urb_write_simd8_masked_per_slot"; + return "gfx8_urb_write_simd8_masked_per_slot"; case SHADER_OPCODE_URB_READ_SIMD8: return "urb_read_simd8"; case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: @@ -442,9 +442,9 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: return "uniform_pull_const"; case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: - return "uniform_pull_const_gen7"; + return "uniform_pull_const_gfx7"; case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: - return "varying_pull_const_gen4"; + return "varying_pull_const_gfx4"; case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: return "varying_pull_const_logical"; @@ -469,7 +469,7 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) case VS_OPCODE_PULL_CONSTANT_LOAD: return "pull_constant_load"; case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: - return "pull_constant_load_gen7"; + return "pull_constant_load_gfx7"; case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: return "unpack_flags_simd4x2"; diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index e1db9ab98ff..5bf82412a26 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -920,7 +920,7 @@ vec4_visitor::move_push_constants_to_pull_constants() int pull_constant_loc[this->uniforms]; /* Only allow 32 registers (256 uniform components) as push constants, - * which is the limit on gen6. + * which is the limit on gfx6. * * If changing this value, note the limitation about total_regs in * brw_curbe.c. @@ -1304,7 +1304,7 @@ vec4_visitor::opt_register_coalesce() break; if (devinfo->ver == 6) { - /* gen6 math instructions must have the destination be + /* gfx6 math instructions must have the destination be * VGRF, so no compute-to-MRF for them. */ if (scan_inst->is_math()) { @@ -1812,7 +1812,7 @@ vec4_visitor::setup_uniforms(int reg) { prog_data->base.dispatch_grf_start_reg = reg; - /* The pre-gen6 VS requires that some push constants get loaded no + /* The pre-gfx6 VS requires that some push constants get loaded no * matter what, or the GPU would hang. */ if (devinfo->ver < 6 && this->uniforms == 0) { @@ -2189,7 +2189,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo, unsigned lowered_width = MIN2(16, inst->exec_size); /* We need to split some cases of double-precision instructions that write - * 2 registers. We only need to care about this in gen7 because that is the + * 2 registers. We only need to care about this in gfx7 because that is the * only hardware that implements fp64 in Align16. */ if (devinfo->ver == 7 && inst->size_written > REG_SIZE) { @@ -2212,7 +2212,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo, lowered_width = MIN2(lowered_width, 4); /* Interleaved attribute setups use a vertical stride of 0, which - * makes them hit the associated instruction decompression bug in gen7. + * makes them hit the associated instruction decompression bug in gfx7. * Split them to prevent this. */ if (inst->src[i].file == ATTR && @@ -2224,7 +2224,7 @@ get_lowered_simd_width(const struct gen_device_info *devinfo, /* IvyBridge can manage a maximum of 4 DFs per SIMD4x2 instruction, since * it doesn't support compression in Align16 mode, no matter if it has * force_writemask_all enabled or disabled (the latter is affected by the - * compressed instruction bug in gen7, which is another reason to enforce + * compressed instruction bug in gfx7, which is another reason to enforce * this limit). */ if (devinfo->ver == 7 && !devinfo->is_haswell && @@ -2384,7 +2384,7 @@ scalarize_predicate(brw_predicate predicate, unsigned writemask) * handful of additional swizzles natively. */ static bool -is_gen7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) +is_gfx7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) { switch (inst->src[arg].swizzle) { case BRW_SWIZZLE_XXXX: @@ -2438,7 +2438,7 @@ vec4_visitor::is_supported_64bit_region(vec4_instruction *inst, unsigned arg) case BRW_SWIZZLE_YXWZ: return true; default: - return devinfo->ver == 7 && is_gen7_supported_64bit_swizzle(inst, arg); + return devinfo->ver == 7 && is_gfx7_supported_64bit_swizzle(inst, arg); } } @@ -2599,7 +2599,7 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, hw_reg->width = BRW_WIDTH_2; if (is_supported_64bit_region(inst, arg) && - !is_gen7_supported_64bit_swizzle(inst, arg)) { + !is_gfx7_supported_64bit_swizzle(inst, arg)) { /* Supported 64-bit swizzles are those such that their first two * components, when expanded to 32-bit swizzles, match the semantics * of the original 64-bit swizzle with 2-wide row regioning. @@ -2614,9 +2614,9 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, * 1. An unsupported swizzle, which should be single-value thanks to the * scalarization pass. * - * 2. A gen7 supported swizzle. These can be single-value or double-value + * 2. A gfx7 supported swizzle. These can be single-value or double-value * swizzles. If the latter, they are never cross-dvec2 channels. For - * these we always need to activate the gen7 vstride=0 exploit. + * these we always need to activate the gfx7 vstride=0 exploit. */ unsigned swizzle0 = BRW_GET_SWZ(reg.swizzle, 0); unsigned swizzle1 = BRW_GET_SWZ(reg.swizzle, 1); @@ -2631,15 +2631,15 @@ vec4_visitor::apply_logical_swizzle(struct brw_reg *hw_reg, swizzle1 -= 2; } - /* All gen7-specific supported swizzles require the vstride=0 exploit */ - if (devinfo->ver == 7 && is_gen7_supported_64bit_swizzle(inst, arg)) + /* All gfx7-specific supported swizzles require the vstride=0 exploit */ + if (devinfo->ver == 7 && is_gfx7_supported_64bit_swizzle(inst, arg)) hw_reg->vstride = BRW_VERTICAL_STRIDE_0; /* Any 64-bit source with an offset at 16B is intended to address the * second half of a register and needs a vertical stride of 0 so we: * * 1. Don't violate register region restrictions. - * 2. Activate the gen7 instruction decompresion bug exploit when + * 2. Activate the gfx7 instruction decompresion bug exploit when * execsize > 4 */ if (hw_reg->subnr % REG_SIZE == 16) { diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h index 94a4dde554c..9cfb48596a2 100644 --- a/src/intel/compiler/brw_vec4.h +++ b/src/intel/compiler/brw_vec4.h @@ -270,7 +270,7 @@ public: src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate, src_reg surface); - void emit_gen6_gather_wa(uint8_t wa, dst_reg dst); + void emit_gfx6_gather_wa(uint8_t wa, dst_reg dst); void emit_ndc_computation(); void emit_psiz_and_flags(dst_reg reg); diff --git a/src/intel/compiler/brw_vec4_builder.h b/src/intel/compiler/brw_vec4_builder.h index e970cf35bea..d746adc942b 100644 --- a/src/intel/compiler/brw_vec4_builder.h +++ b/src/intel/compiler/brw_vec4_builder.h @@ -455,7 +455,7 @@ namespace brw { * * CMP null src0 src1 * - * Original gen4 does type conversion to the destination type + * Original gfx4 does type conversion to the destination type * before comparison, producing garbage results for floating * point comparisons. * @@ -480,7 +480,7 @@ namespace brw { * * CMPN null src0 src1 * - * Original gen4 does type conversion to the destination type + * Original gfx4 does type conversion to the destination type * before comparison, producing garbage results for floating * point comparisons. * @@ -587,14 +587,14 @@ namespace brw { src_reg fix_math_operand(const src_reg &src) const { - /* The gen6 math instruction ignores the source modifiers -- + /* The gfx6 math instruction ignores the source modifiers -- * swizzle, abs, negate, and at least some parts of the register * region description. * * Rather than trying to enumerate all these cases, *always* expand the - * operand to a temp GRF for gen6. + * operand to a temp GRF for gfx6. * - * For gen7, keep the operand as-is, except if immediate, which gen7 still + * For gfx7, keep the operand as-is, except if immediate, which gfx7 still * can't use. */ if (shader->devinfo->ver == 6 || diff --git a/src/intel/compiler/brw_vec4_copy_propagation.cpp b/src/intel/compiler/brw_vec4_copy_propagation.cpp index bd7d8641f9a..ddd239cf83c 100644 --- a/src/intel/compiler/brw_vec4_copy_propagation.cpp +++ b/src/intel/compiler/brw_vec4_copy_propagation.cpp @@ -346,7 +346,7 @@ try_copy_propagate(const struct gen_device_info *devinfo, bool has_source_modifiers = value.negate || value.abs; - /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on + /* gfx6 math and gfx7+ SENDs from GRFs ignore source modifiers on * instructions. */ if (has_source_modifiers && !inst->can_do_source_mods(devinfo)) diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index efd007c4093..b947b960de6 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -29,12 +29,12 @@ using namespace brw; static void -generate_math1_gen4(struct brw_codegen *p, +generate_math1_gfx4(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src) { - gen4_math(p, + gfx4_math(p, dst, brw_math_function(inst->opcode), inst->base_mrf, @@ -43,7 +43,7 @@ generate_math1_gen4(struct brw_codegen *p, } static void -check_gen6_math_src_arg(struct brw_reg src) +check_gfx6_math_src_arg(struct brw_reg src) { /* Source swizzles are ignored. */ assert(!src.abs); @@ -52,7 +52,7 @@ check_gen6_math_src_arg(struct brw_reg src) } static void -generate_math_gen6(struct brw_codegen *p, +generate_math_gfx6(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, @@ -61,17 +61,17 @@ generate_math_gen6(struct brw_codegen *p, /* Can't do writemask because math can't be align16. */ assert(dst.writemask == WRITEMASK_XYZW); /* Source swizzles are ignored. */ - check_gen6_math_src_arg(src0); + check_gfx6_math_src_arg(src0); if (src1.file == BRW_GENERAL_REGISTER_FILE) - check_gen6_math_src_arg(src1); + check_gfx6_math_src_arg(src1); brw_set_default_access_mode(p, BRW_ALIGN_1); - gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1); + gfx6_math(p, dst, brw_math_function(inst->opcode), src0, src1); brw_set_default_access_mode(p, BRW_ALIGN_16); } static void -generate_math2_gen4(struct brw_codegen *p, +generate_math2_gfx4(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, @@ -96,7 +96,7 @@ generate_math2_gen4(struct brw_codegen *p, brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); brw_pop_insn_state(p); - gen4_math(p, + gfx4_math(p, dst, brw_math_function(inst->opcode), inst->base_mrf, @@ -261,11 +261,11 @@ generate_tex(struct brw_codegen *p, } /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type - * is set as part of the message descriptor. On gen4, the PRM seems to + * is set as part of the message descriptor. On gfx4, the PRM seems to * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is * gone from the message descriptor entirely and you just get UINT32 all - * the time regasrdless. Since we can really only do non-UINT32 on gen4, + * the time regasrdless. Since we can really only do non-UINT32 on gfx4, * just stomp it to UINT32 all the time. */ if (inst->opcode == SHADER_OPCODE_TXS) @@ -321,7 +321,7 @@ generate_tex(struct brw_codegen *p, brw_pop_insn_state(p); if (inst->base_mrf != -1) - gen6_resolve_implied_move(p, &src, inst->base_mrf); + gfx6_resolve_implied_move(p, &src, inst->base_mrf); /* dst = send(offset, a0.0 | ) */ brw_send_indirect_message( @@ -725,7 +725,7 @@ generate_gs_ff_sync(struct brw_codegen *p, static void generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst) { - /* In gen6, PrimitiveID is delivered in R0.1 of the payload */ + /* In gfx6, PrimitiveID is delivered in R0.1 of the payload */ struct brw_reg src = brw_vec8_grf(0, 0); brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); @@ -1149,7 +1149,7 @@ generate_scratch_read(struct brw_codegen *p, const struct gen_device_info *devinfo = p->devinfo; struct brw_reg header = brw_vec8_grf(0, 0); - gen6_resolve_implied_move(p, &header, inst->base_mrf); + gfx6_resolve_implied_move(p, &header, inst->base_mrf); generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1), index); @@ -1205,7 +1205,7 @@ generate_scratch_write(struct brw_codegen *p, */ brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); - gen6_resolve_implied_move(p, &header, inst->base_mrf); + gfx6_resolve_implied_move(p, &header, inst->base_mrf); generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1), index); @@ -1225,7 +1225,7 @@ generate_scratch_write(struct brw_codegen *p, brw_set_default_predicate_control(p, inst->predicate); - /* Pre-gen6, we have to specify write commits to ensure ordering + /* Pre-gfx6, we have to specify write commits to ensure ordering * between reads and writes within a thread. Afterwards, that's * guaranteed and write commits only matter for inter-thread * synchronization. @@ -1280,7 +1280,7 @@ generate_pull_constant_load(struct brw_codegen *p, struct brw_reg header = brw_vec8_grf(0, 0); - gen6_resolve_implied_move(p, &header, inst->base_mrf); + gfx6_resolve_implied_move(p, &header, inst->base_mrf); if (devinfo->ver >= 6) { if (offset.file == BRW_IMMEDIATE_VALUE) { @@ -1350,7 +1350,7 @@ generate_get_buffer_size(struct brw_codegen *p, } static void -generate_pull_constant_load_gen7(struct brw_codegen *p, +generate_pull_constant_load_gfx7(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg surf_index, @@ -1681,9 +1681,9 @@ generate_code(struct brw_codegen *p, case BRW_OPCODE_IF: if (!inst->src[0].is_null()) { - /* The instruction has an embedded compare (only allowed on gen6) */ + /* The instruction has an embedded compare (only allowed on gfx6) */ assert(devinfo->ver == 6); - gen6_IF(p, inst->conditional_mod, src[0], src[1]); + gfx6_IF(p, inst->conditional_mod, src[0], src[1]); } else { brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8); brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate); @@ -1724,12 +1724,12 @@ generate_code(struct brw_codegen *p, case SHADER_OPCODE_COS: assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); if (devinfo->ver >= 7) { - gen6_math(p, dst, brw_math_function(inst->opcode), src[0], + gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], brw_null_reg()); } else if (devinfo->ver == 6) { - generate_math_gen6(p, inst, dst, src[0], brw_null_reg()); + generate_math_gfx6(p, inst, dst, src[0], brw_null_reg()); } else { - generate_math1_gen4(p, inst, dst, src[0]); + generate_math1_gfx4(p, inst, dst, src[0]); send_count++; } break; @@ -1739,11 +1739,11 @@ generate_code(struct brw_codegen *p, case SHADER_OPCODE_INT_REMAINDER: assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); if (devinfo->ver >= 7) { - gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); + gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); } else if (devinfo->ver == 6) { - generate_math_gen6(p, inst, dst, src[0], src[1]); + generate_math_gfx6(p, inst, dst, src[0], src[1]); } else { - generate_math2_gen4(p, inst, dst, src[0], src[1]); + generate_math2_gfx4(p, inst, dst, src[0], src[1]); send_count++; } break; @@ -1790,7 +1790,7 @@ generate_code(struct brw_codegen *p, break; case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: - generate_pull_constant_load_gen7(p, inst, dst, src[0], src[1]); + generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]); send_count++; break; diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp index 43d7510003b..4154a8b5882 100644 --- a/src/intel/compiler/brw_vec4_gs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp @@ -664,7 +664,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, nir->info.gs.uses_end_primitive ? 1 : 0; } } else { - /* There are no control data bits in gen6. */ + /* There are no control data bits in gfx6. */ c.control_data_bits_per_vertex = 0; } c.control_data_header_size_bits = @@ -755,10 +755,10 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, * number of output vertices. So we'll just calculate the amount of space * we need, and if it's too large, fail to compile. * - * The above is for gen7+ where we have a single URB entry that will hold - * all the output. In gen6, we will have to allocate URB entries for every + * The above is for gfx7+ where we have a single URB entry that will hold + * all the output. In gfx6, we will have to allocate URB entries for every * vertex we emit, so our URB entries only need to be large enough to hold - * a single vertex. Also, gen6 does not have a control data header. + * a single vertex. Also, gfx6 does not have a control data header. */ unsigned output_size_bytes; if (compiler->devinfo->ver >= 7) { @@ -789,8 +789,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, return NULL; - /* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and - * a multiple of 128 bytes in gen6. + /* URB entry sizes are stored as a multiple of 64 bytes in gfx7+ and + * a multiple of 128 bytes in gfx6. */ if (compiler->devinfo->ver >= 7) { prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64; @@ -931,7 +931,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, nir, mem_ctx, false /* no_spills */, shader_time_index, debug_enabled); else - gs = new brw::gen6_gs_visitor(compiler, log_data, &c, prog_data, prog, + gs = new brw::gfx6_gs_visitor(compiler, log_data, &c, prog_data, prog, nir, mem_ctx, false /* no_spills */, shader_time_index, debug_enabled); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 81e97687693..966bc223f84 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -285,7 +285,7 @@ setup_imm_df(const vec4_builder &bld, double v) const gen_device_info *devinfo = bld.shader->devinfo; assert(devinfo->ver == 7); - /* gen7.5 does not support DF immediates straighforward but the DIM + /* gfx7.5 does not support DF immediates straighforward but the DIM * instruction allows to set the 64-bit immediate value. */ if (devinfo->is_haswell) { @@ -295,7 +295,7 @@ setup_imm_df(const vec4_builder &bld, double v) return swizzle(src_reg(dst), BRW_SWIZZLE_XXXX); } - /* gen7 does not support DF immediates */ + /* gfx7 does not support DF immediates */ union { double d; struct { diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 769c45512e3..2f8efd02c97 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -403,7 +403,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, 2 + has_primitive_id + key->input_vertices <= (devinfo->ver >= 12 ? 63 : 31)) { /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the * "Instance" field limits the number of output vertices to [1, 16] on - * gen11 and below, or [1, 32] on gen12 and above. Secondly, the + * gfx11 and below, or [1, 32] on gfx12 and above. Secondly, the * "Dispatch GRF Start Register for URB Data" field is limited to [0, * 31] - which imposes a limit on the input vertices. */ diff --git a/src/intel/compiler/brw_vec4_visitor.cpp b/src/intel/compiler/brw_vec4_visitor.cpp index d797bf3b6ad..1bafb4ab198 100644 --- a/src/intel/compiler/brw_vec4_visitor.cpp +++ b/src/intel/compiler/brw_vec4_visitor.cpp @@ -235,7 +235,7 @@ vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, * * CMP null src0 src1 * - * Original gen4 does type conversion to the destination type before + * Original gfx4 does type conversion to the destination type before * comparison, producing garbage results for floating point comparisons. * * The destination type doesn't matter on newer generations, so we set the @@ -311,14 +311,14 @@ vec4_visitor::fix_math_operand(const src_reg &src) if (devinfo->ver < 6 || src.file == BAD_FILE) return src; - /* The gen6 math instruction ignores the source modifiers -- + /* The gfx6 math instruction ignores the source modifiers -- * swizzle, abs, negate, and at least some parts of the register * region description. * * Rather than trying to enumerate all these cases, *always* expand the - * operand to a temp GRF for gen6. + * operand to a temp GRF for gfx6. * - * For gen7, keep the operand as-is, except if immediate, which gen7 still + * For gfx7, keep the operand as-is, except if immediate, which gfx7 still * can't use. */ @@ -383,7 +383,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0) * code, I chose instead to remain in align16 mode in defiance of the hw * docs). * - * I've [chadv] experimentally confirmed that, on gen7 hardware and the + * I've [chadv] experimentally confirmed that, on gfx7 hardware and the * simulator, emitting a f32to16 in align16 mode with UD as destination * data type is safe. The behavior differs from that specified in the PRM * in that the upper word of each destination channel is cleared to 0. @@ -450,7 +450,7 @@ vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0) * emitting align1 instructions for unpackHalf2x16 failed to pass the * Piglit tests, so I gave up. * - * I've verified that, on gen7 hardware and the simulator, it is safe to + * I've verified that, on gfx7 hardware and the simulator, it is safe to * emit f16to32 in align16 mode with UD as source data type. */ @@ -1006,7 +1006,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op, } if (devinfo->ver == 6 && op == ir_tg4) { - emit_gen6_gather_wa(key_tex->gen6_gather_wa[surface], inst->dst); + emit_gfx6_gather_wa(key_tex->gfx6_gather_wa[surface], inst->dst); } if (op == ir_query_levels) { @@ -1022,7 +1022,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op, * Apply workarounds for Gen6 gather with UINT/SINT */ void -vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst) +vec4_visitor::emit_gfx6_gather_wa(uint8_t wa, dst_reg dst) { if (!wa) return; @@ -1285,7 +1285,7 @@ vec4_visitor::emit_vertex() int max_usable_mrf = FIRST_SPILL_MRF(devinfo->ver); /* The following assertion verifies that max_usable_mrf causes an - * even-numbered amount of URB write data, which will meet gen6's + * even-numbered amount of URB write data, which will meet gfx6's * requirements for length alignment. */ assert ((max_usable_mrf - base_mrf) % 2 == 0); @@ -1344,7 +1344,7 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst, */ int message_header_scale = 2; - /* Pre-gen6, the message header uses byte offsets instead of vec4 + /* Pre-gfx6, the message header uses byte offsets instead of vec4 * (16-byte) offset units. */ if (devinfo->ver < 6) diff --git a/src/intel/compiler/brw_wm_iz.cpp b/src/intel/compiler/brw_wm_iz.cpp index 8b280d8f050..d4ef05a4a8d 100644 --- a/src/intel/compiler/brw_wm_iz.cpp +++ b/src/intel/compiler/brw_wm_iz.cpp @@ -119,7 +119,7 @@ static const struct { * \param line_aa BRW_WM_AA_NEVER, BRW_WM_AA_ALWAYS or BRW_WM_AA_SOMETIMES * \param lookup bitmask of BRW_WM_IZ_* flags */ -void fs_visitor::setup_fs_payload_gen4() +void fs_visitor::setup_fs_payload_gfx4() { assert(stage == MESA_SHADER_FRAGMENT); assert(dispatch_width <= 16); diff --git a/src/intel/compiler/gfx6_gs_visitor.cpp b/src/intel/compiler/gfx6_gs_visitor.cpp index 535c277b1d2..3d5786a8bde 100644 --- a/src/intel/compiler/gfx6_gs_visitor.cpp +++ b/src/intel/compiler/gfx6_gs_visitor.cpp @@ -35,7 +35,7 @@ namespace brw { void -gen6_gs_visitor::emit_prolog() +gfx6_gs_visitor::emit_prolog() { vec4_gs_visitor::emit_prolog(); @@ -44,7 +44,7 @@ gen6_gs_visitor::emit_prolog() * can write to the URB simultaneously and the FF_SYNC message provides the * synchronization mechanism for this, so using this message effectively * stalls the thread until it is its turn to write to the URB. Because of - * this, the best way to implement geometry shader algorithms in gen6 is to + * this, the best way to implement geometry shader algorithms in gfx6 is to * execute the algorithm before the FF_SYNC message to maximize parallelism. * * To achieve this we buffer the geometry shader outputs for each emitted @@ -60,7 +60,7 @@ gen6_gs_visitor::emit_prolog() * flags for the next vertex come right after the data items and flags for * the previous vertex. */ - this->current_annotation = "gen6 prolog"; + this->current_annotation = "gfx6 prolog"; this->vertex_output = src_reg(this, glsl_type::uint_type, (prog_data->vue_map.num_slots + 1) * @@ -137,9 +137,9 @@ gen6_gs_visitor::emit_prolog() } void -gen6_gs_visitor::gs_emit_vertex(int stream_id) +gfx6_gs_visitor::gs_emit_vertex(int stream_id) { - this->current_annotation = "gen6 emit vertex"; + this->current_annotation = "gfx6 emit vertex"; /* Buffer all output slots for this vertex in vertex_output */ for (int slot = 0; slot < prog_data->vue_map.num_slots; ++slot) { @@ -201,9 +201,9 @@ gen6_gs_visitor::gs_emit_vertex(int stream_id) } void -gen6_gs_visitor::gs_end_primitive() +gfx6_gs_visitor::gs_end_primitive() { - this->current_annotation = "gen6 end primitive"; + this->current_annotation = "gfx6 end primitive"; /* Calling EndPrimitive() is optional for point output. In this case we set * the PrimEnd flag when we process EmitVertex(). */ @@ -251,9 +251,9 @@ gen6_gs_visitor::gs_end_primitive() } void -gen6_gs_visitor::emit_urb_write_header(int mrf) +gfx6_gs_visitor::emit_urb_write_header(int mrf) { - this->current_annotation = "gen6 urb header"; + this->current_annotation = "gfx6 urb header"; /* Compute offset of the flags for the current vertex in vertex_output and * write them in dw2 of the message header. * @@ -287,7 +287,7 @@ align_interleaved_urb_mlen(unsigned mlen) } void -gen6_gs_visitor::emit_urb_write_opcode(bool complete, int base_mrf, +gfx6_gs_visitor::emit_urb_write_opcode(bool complete, int base_mrf, int last_mrf, int urb_offset) { vec4_instruction *inst = NULL; @@ -317,7 +317,7 @@ gen6_gs_visitor::emit_urb_write_opcode(bool complete, int base_mrf, } void -gen6_gs_visitor::emit_thread_end() +gfx6_gs_visitor::emit_thread_end() { /* Make sure the current primitive is ended: we know it is not ended when * first_vertex is not zero. This is only relevant for outputs other than @@ -350,7 +350,7 @@ gen6_gs_visitor::emit_thread_end() int max_usable_mrf = FIRST_SPILL_MRF(devinfo->ver); /* Issue the FF_SYNC message and obtain the initial VUE handle. */ - this->current_annotation = "gen6 thread end: ff_sync"; + this->current_annotation = "gfx6 thread end: ff_sync"; vec4_instruction *inst = NULL; if (prog->info.has_transform_feedback_varyings) { @@ -372,12 +372,12 @@ gen6_gs_visitor::emit_thread_end() emit(IF(BRW_PREDICATE_NORMAL)); { /* Loop over all buffered vertices and emit URB write messages */ - this->current_annotation = "gen6 thread end: urb writes init"; + this->current_annotation = "gfx6 thread end: urb writes init"; src_reg vertex(this, glsl_type::uint_type); emit(MOV(dst_reg(vertex), brw_imm_ud(0u))); emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u))); - this->current_annotation = "gen6 thread end: urb writes"; + this->current_annotation = "gfx6 thread end: urb writes"; emit(BRW_OPCODE_DO); { emit(CMP(dst_null_d(), vertex, this->vertex_count, BRW_CONDITIONAL_GE)); @@ -453,7 +453,7 @@ gen6_gs_visitor::emit_thread_end() /* Finally, emit EOT message. * - * In gen6 we need to end the thread differently depending on whether we have + * In gfx6 we need to end the thread differently depending on whether we have * emitted at least one vertex or not. In case we did, the EOT message must * always include the COMPLETE flag or else the GPU hangs. If we have not * produced any output we can't use the COMPLETE flag. @@ -466,7 +466,7 @@ gen6_gs_visitor::emit_thread_end() * which works for both cases by setting the COMPLETE and UNUSED flags in * the EOT message. */ - this->current_annotation = "gen6 thread end: EOT"; + this->current_annotation = "gfx6 thread end: EOT"; if (prog->info.has_transform_feedback_varyings) { /* When emitting EOT, set SONumPrimsWritten Increment Value. */ @@ -483,7 +483,7 @@ gen6_gs_visitor::emit_thread_end() } void -gen6_gs_visitor::setup_payload() +gfx6_gs_visitor::setup_payload() { int attribute_map[BRW_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES]; @@ -522,7 +522,7 @@ gen6_gs_visitor::setup_payload() } void -gen6_gs_visitor::xfb_setup() +gfx6_gs_visitor::xfb_setup() { static const unsigned swizzle_for_offset[4] = { BRW_SWIZZLE4(0, 1, 2, 3), @@ -556,7 +556,7 @@ gen6_gs_visitor::xfb_setup() } void -gen6_gs_visitor::xfb_write() +gfx6_gs_visitor::xfb_write() { unsigned num_verts; @@ -587,7 +587,7 @@ gen6_gs_visitor::xfb_write() unreachable("Unexpected primitive type in Gen6 SOL program."); } - this->current_annotation = "gen6 thread end: svb writes init"; + this->current_annotation = "gfx6 thread end: svb writes init"; emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u))); emit(MOV(dst_reg(this->sol_prim_written), brw_imm_ud(0u))); @@ -604,7 +604,7 @@ gen6_gs_visitor::xfb_write() emit(ADD(dst_reg(sol_temp), this->svbi, brw_imm_ud(num_verts))); /* Compare SVBI calculated number with the maximum value, which is - * in R1.4 (previously saved in this->max_svbi) for gen6. + * in R1.4 (previously saved in this->max_svbi) for gfx6. */ emit(CMP(dst_null_d(), sol_temp, this->max_svbi, BRW_CONDITIONAL_LE)); emit(IF(BRW_PREDICATE_NORMAL)); @@ -636,7 +636,7 @@ gen6_gs_visitor::xfb_write() } void -gen6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) +gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) { unsigned binding; unsigned num_bindings = gs_prog_data->num_transform_feedback_bindings; @@ -654,7 +654,7 @@ gen6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) /* Avoid overwriting MRF 1 as it is used as URB write message header */ dst_reg mrf_reg(MRF, 2); - this->current_annotation = "gen6: emit SOL vertex data"; + this->current_annotation = "gfx6: emit SOL vertex data"; /* For each vertex, generate code to output each varying using the * appropriate binding table entry. */ @@ -712,7 +712,7 @@ gen6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts) } int -gen6_gs_visitor::get_vertex_output_offset_for_varying(int vertex, int varying) +gfx6_gs_visitor::get_vertex_output_offset_for_varying(int vertex, int varying) { /* Find the output slot assigned to this varying. * diff --git a/src/intel/compiler/gfx6_gs_visitor.h b/src/intel/compiler/gfx6_gs_visitor.h index a6fbc2793a7..38ffda0c482 100644 --- a/src/intel/compiler/gfx6_gs_visitor.h +++ b/src/intel/compiler/gfx6_gs_visitor.h @@ -32,10 +32,10 @@ namespace brw { -class gen6_gs_visitor : public vec4_gs_visitor +class gfx6_gs_visitor : public vec4_gs_visitor { public: - gen6_gs_visitor(const struct brw_compiler *comp, + gfx6_gs_visitor(const struct brw_compiler *comp, void *log_data, struct brw_gs_compile *c, struct brw_gs_prog_data *prog_data, diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index d3365c4f0c6..3841e22e8c1 100644 --- a/src/intel/compiler/test_eu_compact.cpp +++ b/src/intel/compiler/test_eu_compact.cpp @@ -252,7 +252,7 @@ gen_f0_0_MOV_GRF_GRF(struct brw_codegen *p) brw_pop_insn_state(p); } -/* The handling of f0.1 vs f0.0 changes between gen6 and gen7. Explicitly test +/* The handling of f0.1 vs f0.0 changes between gfx6 and gfx7. Explicitly test * it, so that we run the fuzzing can run over all the other bits that might * interact with it. */ diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index 08197f21395..34303aa6669 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++ b/src/intel/compiler/test_eu_validate.cpp @@ -153,9 +153,9 @@ TEST_P(validation_test, src1_null_reg) TEST_P(validation_test, math_src0_null_reg) { if (devinfo.ver >= 6) { - gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, null, null); + gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, null, null); } else { - gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, null, BRW_MATH_PRECISION_FULL); + gfx4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, null, BRW_MATH_PRECISION_FULL); } EXPECT_FALSE(validate(p)); @@ -164,11 +164,11 @@ TEST_P(validation_test, math_src0_null_reg) TEST_P(validation_test, math_src1_null_reg) { if (devinfo.ver >= 6) { - gen6_math(p, g0, BRW_MATH_FUNCTION_POW, g0, null); + gfx6_math(p, g0, BRW_MATH_FUNCTION_POW, g0, null); EXPECT_FALSE(validate(p)); } else { /* Math instructions on Gen4/5 are actually SEND messages with payloads. - * src1 is an immediate message descriptor set by gen4_math. + * src1 is an immediate message descriptor set by gfx4_math. */ } } @@ -247,9 +247,9 @@ TEST_P(validation_test, invalid_file_encoding) clear_instructions(p); if (devinfo.ver < 6) { - gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, g0, BRW_MATH_PRECISION_FULL); + gfx4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, g0, BRW_MATH_PRECISION_FULL); } else { - gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); + gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); } brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F); @@ -1016,13 +1016,13 @@ TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers) clear_instructions(p); if (devinfo.ver >= 6) { - gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); + gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); EXPECT_TRUE(validate(p)); clear_instructions(p); - gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); + gfx6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4); EXPECT_FALSE(validate(p)); @@ -1310,7 +1310,7 @@ TEST_P(validation_test, half_float_conversion) unsigned dst_stride; unsigned dst_subnr; bool expected_result_bdw; - bool expected_result_chv_gen9; + bool expected_result_chv_gfx9; } inst[] = { #define INST_C(dst_type, src_type, dst_stride, dst_subnr, expected_result) \ { \ @@ -1322,14 +1322,14 @@ TEST_P(validation_test, half_float_conversion) expected_result, \ } #define INST_S(dst_type, src_type, dst_stride, dst_subnr, \ - expected_result_bdw, expected_result_chv_gen9) \ + expected_result_bdw, expected_result_chv_gfx9) \ { \ BRW_REGISTER_TYPE_##dst_type, \ BRW_REGISTER_TYPE_##src_type, \ BRW_HORIZONTAL_STRIDE_##dst_stride, \ dst_subnr, \ expected_result_bdw, \ - expected_result_chv_gen9, \ + expected_result_chv_gfx9, \ } /* MOV to half-float destination */ @@ -1417,7 +1417,7 @@ TEST_P(validation_test, half_float_conversion) } if (devinfo.is_cherryview || devinfo.ver >= 9) - EXPECT_EQ(inst[i].expected_result_chv_gen9, validate(p)); + EXPECT_EQ(inst[i].expected_result_chv_gfx9, validate(p)); else EXPECT_EQ(inst[i].expected_result_bdw, validate(p)); @@ -1733,12 +1733,12 @@ TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs) #undef INST }; - /* No half-float math in gen8 */ + /* No half-float math in gfx8 */ if (devinfo.ver < 9) return; for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - gen6_math(p, retype(g0, inst[i].dst_type), + gfx6_math(p, retype(g0, inst[i].dst_type), BRW_MATH_FUNCTION_POW, retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); @@ -2034,14 +2034,14 @@ TEST_P(validation_test, mixed_float_align16_math_packed_format) #undef INST }; - /* Align16 Math for mixed float mode is not supported in gen8 */ + /* Align16 Math for mixed float mode is not supported in gfx8 */ if (devinfo.ver < 9 || devinfo.ver >= 11) return; brw_set_default_access_mode(p, BRW_ALIGN_16); for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) { - gen6_math(p, retype(g0, inst[i].dst_type), + gfx6_math(p, retype(g0, inst[i].dst_type), BRW_MATH_FUNCTION_POW, retype(g0, inst[i].src0_type), retype(g0, inst[i].src1_type)); @@ -2819,7 +2819,7 @@ TEST_P(validation_test, qword_low_power_no_depctrl) } } -TEST_P(validation_test, gen11_no_byte_src_1_2) +TEST_P(validation_test, gfx11_no_byte_src_1_2) { static const struct { enum opcode opcode; diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c index e0922e92ed9..c37ef56aee6 100644 --- a/src/intel/dev/gen_device_info.c +++ b/src/intel/dev/gen_device_info.c @@ -83,7 +83,7 @@ gen_device_name_to_pci_device_id(const char *name) return -1; } -static const struct gen_device_info gen_device_info_gen3 = { +static const struct gen_device_info gen_device_info_gfx3 = { .ver = 3, .simulator_id = -1, .cs_prefetch_size = 512, @@ -1236,7 +1236,7 @@ gen_get_device_info_from_pci_id(int pci_id, #undef CHIPSET #define CHIPSET(id, fam_str, name) \ - case id: *devinfo = gen_device_info_gen3; break; + case id: *devinfo = gen_device_info_gfx3; break; #include "pci_ids/i915_pci_ids.h" default: @@ -1300,7 +1300,7 @@ gen_get_device_name(int devid) } /** - * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology + * for gfx8/gfx9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology * (kernel 4.13+) */ static bool @@ -1471,7 +1471,7 @@ gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo) return false; } - /* else use the kernel 4.13+ api for gen8+. For older kernels, topology + /* else use the kernel 4.13+ api for gfx8+. For older kernels, topology * will be wrong, affecting GPU metrics. In this case, fail silently. */ getparam_topology(devinfo, fd); diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h index bf0d04f860d..ce8596ae665 100644 --- a/src/intel/dev/gen_device_info.h +++ b/src/intel/dev/gen_device_info.h @@ -36,10 +36,10 @@ extern "C" { struct drm_i915_query_topology_info; -#define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */ -#define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */ -#define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gen12 */ -#define GEN_DEVICE_MAX_PIXEL_PIPES (3) /* Maximum on gen12 */ +#define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gfx10 */ +#define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gfx11 */ +#define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gfx12 */ +#define GEN_DEVICE_MAX_PIXEL_PIPES (3) /* Maximum on gfx12 */ /** * Intel hardware information and quirks diff --git a/src/intel/genxml/gen_macros.h b/src/intel/genxml/gen_macros.h index afa2ccfceb5..cc2212dc433 100644 --- a/src/intel/genxml/gen_macros.h +++ b/src/intel/genxml/gen_macros.h @@ -61,37 +61,37 @@ /* Prefixing macros */ #if (GFX_VERx10 == 40) # define GENX(X) GFX4_##X -# define genX(x) gen4_##x +# define genX(x) gfx4_##x #elif (GFX_VERx10 == 45) # define GENX(X) GFX45_##X -# define genX(x) gen45_##x +# define genX(x) gfx45_##x #elif (GFX_VERx10 == 50) # define GENX(X) GFX5_##X -# define genX(x) gen5_##x +# define genX(x) gfx5_##x #elif (GFX_VERx10 == 60) # define GENX(X) GFX6_##X -# define genX(x) gen6_##x +# define genX(x) gfx6_##x #elif (GFX_VERx10 == 70) # define GENX(X) GFX7_##X -# define genX(x) gen7_##x +# define genX(x) gfx7_##x #elif (GFX_VERx10 == 75) # define GENX(X) GFX75_##X -# define genX(x) gen75_##x +# define genX(x) gfx75_##x #elif (GFX_VERx10 == 80) # define GENX(X) GFX8_##X -# define genX(x) gen8_##x +# define genX(x) gfx8_##x #elif (GFX_VERx10 == 90) # define GENX(X) GFX9_##X -# define genX(x) gen9_##x +# define genX(x) gfx9_##x #elif (GFX_VERx10 == 110) # define GENX(X) GFX11_##X -# define genX(x) gen11_##x +# define genX(x) gfx11_##x #elif (GFX_VERx10 == 120) # define GENX(X) GFX12_##X -# define genX(x) gen12_##x +# define genX(x) gfx12_##x #elif (GFX_VERx10 == 125) # define GENX(X) GFX125_##X -# define genX(x) gen125_##x +# define genX(x) gfx125_##x #else # error "Need to add prefixing macros for this gen" #endif diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 14b02d9af20..2a2201130f0 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -523,9 +523,9 @@ isl_surf_choose_tiling(const struct isl_device *dev, } if (ISL_GFX_VER(dev) >= 6) { - isl_gen6_filter_tiling(dev, info, &tiling_flags); + isl_gfx6_filter_tiling(dev, info, &tiling_flags); } else { - isl_gen4_filter_tiling(dev, info, &tiling_flags); + isl_gfx4_filter_tiling(dev, info, &tiling_flags); } #define CHOOSE(__tiling) \ @@ -569,13 +569,13 @@ isl_choose_msaa_layout(const struct isl_device *dev, enum isl_msaa_layout *msaa_layout) { if (ISL_GFX_VER(dev) >= 8) { - return isl_gen8_choose_msaa_layout(dev, info, tiling, msaa_layout); + return isl_gfx8_choose_msaa_layout(dev, info, tiling, msaa_layout); } else if (ISL_GFX_VER(dev) >= 7) { - return isl_gen7_choose_msaa_layout(dev, info, tiling, msaa_layout); + return isl_gfx7_choose_msaa_layout(dev, info, tiling, msaa_layout); } else if (ISL_GFX_VER(dev) >= 6) { - return isl_gen6_choose_msaa_layout(dev, info, tiling, msaa_layout); + return isl_gfx6_choose_msaa_layout(dev, info, tiling, msaa_layout); } else { - return isl_gen4_choose_msaa_layout(dev, info, tiling, msaa_layout); + return isl_gfx4_choose_msaa_layout(dev, info, tiling, msaa_layout); } } @@ -717,7 +717,7 @@ isl_choose_array_pitch_span(const struct isl_device *dev, return ISL_ARRAY_PITCH_SPAN_COMPACT; case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: - /* Each array image in the gen6 stencil of HiZ surface is compact in the + /* Each array image in the gfx6 stencil of HiZ surface is compact in the * sense that every LOD is a compact array of the same size as LOD0. */ return ISL_ARRAY_PITCH_SPAN_COMPACT; @@ -756,12 +756,12 @@ isl_choose_image_alignment_el(const struct isl_device *dev, /* HiZ surfaces on Sandy Bridge are packed tightly. */ *image_align_el = isl_extent3d(1, 1, 1); } else if (ISL_GFX_VER(dev) < 12) { - /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the + /* On gfx7+, HiZ surfaces are always aligned to 16x8 pixels in the * primary surface which works out to 2x2 HiZ elments. */ *image_align_el = isl_extent3d(2, 2, 1); } else { - /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the + /* On gfx12+, HiZ surfaces are always aligned to 16x16 pixels in the * primary surface which works out to 2x4 HiZ elments. * TODO: Verify */ @@ -771,22 +771,22 @@ isl_choose_image_alignment_el(const struct isl_device *dev, } if (ISL_GFX_VER(dev) >= 12) { - isl_gen12_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx12_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } else if (ISL_GFX_VER(dev) >= 9) { - isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } else if (ISL_GFX_VER(dev) >= 8) { - isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } else if (ISL_GFX_VER(dev) >= 7) { - isl_gen7_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx7_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } else if (ISL_GFX_VER(dev) >= 6) { - isl_gen6_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx6_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } else { - isl_gen4_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx4_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } } @@ -991,7 +991,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, * surface elements. */ static uint32_t -isl_calc_array_pitch_el_rows_gen4_2d( +isl_calc_array_pitch_el_rows_gfx4_2d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_tile_info *tile_info, @@ -1096,7 +1096,7 @@ isl_calc_array_pitch_el_rows_gen4_2d( * ISL_DIM_LAYOUT_GEN4_2D. */ static void -isl_calc_phys_slice0_extent_sa_gen4_2d( +isl_calc_phys_slice0_extent_sa_gfx4_2d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_msaa_layout msaa_layout, @@ -1165,7 +1165,7 @@ isl_calc_phys_slice0_extent_sa_gen4_2d( } static void -isl_calc_phys_total_extent_el_gen4_2d( +isl_calc_phys_total_extent_el_gfx4_2d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_tile_info *tile_info, @@ -1179,11 +1179,11 @@ isl_calc_phys_total_extent_el_gen4_2d( const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); struct isl_extent2d phys_slice0_sa; - isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout, + isl_calc_phys_slice0_extent_sa_gfx4_2d(dev, info, msaa_layout, image_align_sa, phys_level0_sa, &phys_slice0_sa); *array_pitch_el_rows = - isl_calc_array_pitch_el_rows_gen4_2d(dev, info, tile_info, + isl_calc_array_pitch_el_rows_gfx4_2d(dev, info, tile_info, image_align_sa, phys_level0_sa, array_pitch_span, &phys_slice0_sa); @@ -1199,7 +1199,7 @@ isl_calc_phys_total_extent_el_gen4_2d( * ISL_DIM_LAYOUT_GEN4_3D. */ static void -isl_calc_phys_total_extent_el_gen4_3d( +isl_calc_phys_total_extent_el_gfx4_3d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_extent3d *image_align_sa, @@ -1263,7 +1263,7 @@ isl_calc_phys_total_extent_el_gen4_3d( * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ. */ static void -isl_calc_phys_total_extent_el_gen6_stencil_hiz( +isl_calc_phys_total_extent_el_gfx6_stencil_hiz( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_tile_info *tile_info, @@ -1324,7 +1324,7 @@ isl_calc_phys_total_extent_el_gen6_stencil_hiz( * ISL_DIM_LAYOUT_GEN9_1D. */ static void -isl_calc_phys_total_extent_el_gen9_1d( +isl_calc_phys_total_extent_el_gfx9_1d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_extent3d *image_align_sa, @@ -1375,13 +1375,13 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev, switch (dim_layout) { case ISL_DIM_LAYOUT_GEN9_1D: assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); - isl_calc_phys_total_extent_el_gen9_1d(dev, info, + isl_calc_phys_total_extent_el_gfx9_1d(dev, info, image_align_sa, phys_level0_sa, array_pitch_el_rows, total_extent_el); return; case ISL_DIM_LAYOUT_GEN4_2D: - isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout, + isl_calc_phys_total_extent_el_gfx4_2d(dev, info, tile_info, msaa_layout, image_align_sa, phys_level0_sa, array_pitch_span, array_pitch_el_rows, @@ -1389,7 +1389,7 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev, return; case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); - isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev, info, tile_info, + isl_calc_phys_total_extent_el_gfx6_stencil_hiz(dev, info, tile_info, image_align_sa, phys_level0_sa, array_pitch_el_rows, @@ -1397,7 +1397,7 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev, return; case ISL_DIM_LAYOUT_GEN4_3D: assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); - isl_calc_phys_total_extent_el_gen4_3d(dev, info, + isl_calc_phys_total_extent_el_gfx4_3d(dev, info, image_align_sa, phys_level0_sa, array_pitch_el_rows, total_extent_el); @@ -1736,7 +1736,7 @@ isl_surf_init_s(const struct isl_device *dev, * surfaces are also restricted to a maximum size in bytes. This * maximum is 2 GB for all products and all surface types." * - * This comment is applicable to all Pre-gen9 platforms. + * This comment is applicable to all Pre-gfx9 platforms. */ if (size_B > (uint64_t) 1 << 31) return false; @@ -1750,7 +1750,7 @@ isl_surf_init_s(const struct isl_device *dev, if (size_B > (uint64_t) 1 << 38) return false; } else { - /* gen11+ platforms raised this limit to 2^44 bytes. */ + /* gfx11+ platforms raised this limit to 2^44 bytes. */ if (size_B > (uint64_t) 1 << 44) return false; } @@ -2047,7 +2047,7 @@ isl_surf_supports_ccs(const struct isl_device *dev, return false; /* The PRM doesn't say this explicitly, but fast-clears don't appear to - * work for 3D textures until gen9 where the layout of 3D textures + * work for 3D textures until gfx9 where the layout of 3D textures * changes to match 2D array textures. */ if (ISL_GFX_VER(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D) @@ -2058,7 +2058,7 @@ isl_surf_supports_ccs(const struct isl_device *dev, * * "Support is for non-mip-mapped and non-array surface types only." * - * This restriction is lifted on gen8+. Technically, it may be possible + * This restriction is lifted on gfx8+. Technically, it may be possible * to create a CCS for an arrayed or mipmapped image and only enable * CCS_D when rendering to the base slice. However, there is no * documentation tell us what the hardware would do in that case or what @@ -2193,36 +2193,36 @@ isl_surf_get_ccs_surf(const struct isl_device *dev, #define isl_genX_call(dev, func, ...) \ switch (ISL_GFX_VERX10(dev)) { \ case 40: \ - isl_gen4_##func(__VA_ARGS__); \ + isl_gfx4_##func(__VA_ARGS__); \ break; \ case 45: \ - /* G45 surface state is the same as gen5 */ \ + /* G45 surface state is the same as gfx5 */ \ case 50: \ - isl_gen5_##func(__VA_ARGS__); \ + isl_gfx5_##func(__VA_ARGS__); \ break; \ case 60: \ - isl_gen6_##func(__VA_ARGS__); \ + isl_gfx6_##func(__VA_ARGS__); \ break; \ case 70: \ - isl_gen7_##func(__VA_ARGS__); \ + isl_gfx7_##func(__VA_ARGS__); \ break; \ case 75: \ - isl_gen75_##func(__VA_ARGS__); \ + isl_gfx75_##func(__VA_ARGS__); \ break; \ case 80: \ - isl_gen8_##func(__VA_ARGS__); \ + isl_gfx8_##func(__VA_ARGS__); \ break; \ case 90: \ - isl_gen9_##func(__VA_ARGS__); \ + isl_gfx9_##func(__VA_ARGS__); \ break; \ case 110: \ - isl_gen11_##func(__VA_ARGS__); \ + isl_gfx11_##func(__VA_ARGS__); \ break; \ case 120: \ - isl_gen12_##func(__VA_ARGS__); \ + isl_gfx12_##func(__VA_ARGS__); \ break; \ case 125: \ - isl_gen125_##func(__VA_ARGS__); \ + isl_gfx125_##func(__VA_ARGS__); \ break; \ default: \ assert(!"Unknown hardware generation"); \ @@ -2310,7 +2310,7 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch, * ISL_DIM_LAYOUT_GEN4_2D. */ static void -get_image_offset_sa_gen4_2d(const struct isl_surf *surf, +get_image_offset_sa_gfx4_2d(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t *x_offset_sa, uint32_t *y_offset_sa) @@ -2352,7 +2352,7 @@ get_image_offset_sa_gen4_2d(const struct isl_surf *surf, * ISL_DIM_LAYOUT_GEN4_3D. */ static void -get_image_offset_sa_gen4_3d(const struct isl_surf *surf, +get_image_offset_sa_gfx4_3d(const struct isl_surf *surf, uint32_t level, uint32_t logical_z_offset_px, uint32_t *x_offset_sa, uint32_t *y_offset_sa) @@ -2405,7 +2405,7 @@ get_image_offset_sa_gen4_3d(const struct isl_surf *surf, } static void -get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf *surf, +get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t *x_offset_sa, @@ -2468,7 +2468,7 @@ get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf *surf, * ISL_DIM_LAYOUT_GEN9_1D. */ static void -get_image_offset_sa_gen9_1d(const struct isl_surf *surf, +get_image_offset_sa_gfx9_1d(const struct isl_surf *surf, uint32_t level, uint32_t layer, uint32_t *x_offset_sa, uint32_t *y_offset_sa) @@ -2519,21 +2519,21 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf, switch (surf->dim_layout) { case ISL_DIM_LAYOUT_GEN9_1D: - get_image_offset_sa_gen9_1d(surf, level, logical_array_layer, + get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer, x_offset_sa, y_offset_sa); break; case ISL_DIM_LAYOUT_GEN4_2D: - get_image_offset_sa_gen4_2d(surf, level, logical_array_layer + get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer + logical_z_offset_px, x_offset_sa, y_offset_sa); break; case ISL_DIM_LAYOUT_GEN4_3D: - get_image_offset_sa_gen4_3d(surf, level, logical_array_layer + + get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer + logical_z_offset_px, x_offset_sa, y_offset_sa); break; case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: - get_image_offset_sa_gen6_stencil_hiz(surf, level, logical_array_layer + + get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer + logical_z_offset_px, x_offset_sa, y_offset_sa); break; @@ -2752,10 +2752,10 @@ uint32_t isl_surf_get_depth_format(const struct isl_device *dev, const struct isl_surf *surf) { - /* Support for separate stencil buffers began in gen5. Support for - * interleaved depthstencil buffers ceased in gen7. The intermediate gens, - * those that supported separate and interleaved stencil, were gen5 and - * gen6. + /* Support for separate stencil buffers began in gfx5. Support for + * interleaved depthstencil buffers ceased in gfx7. The intermediate gens, + * those that supported separate and interleaved stencil, were gfx5 and + * gfx6. * * For a list of all available formats, see the Sandybridge PRM >> Volume * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 359f93e9086..716dc01464b 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -548,8 +548,8 @@ enum isl_dim_layout { /** * Special layout used for HiZ and stencil on Sandy Bridge to work around - * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers - * work the same as on gen7+ except that they don't technically support + * the hardware's lack of mipmap support. On gfx6, HiZ and stencil buffers + * work the same as on gfx7+ except that they don't technically support * mipmapping. That does not, however, stop us from doing it. As far as * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a * single miplevel 2D (possibly array) image. The dimensions of that image @@ -1418,7 +1418,7 @@ struct isl_surf_fill_state_info { uint64_t clear_address; /** - * Surface write disables for gen4-5 + * Surface write disables for gfx4-5 */ isl_channel_mask_t write_disables; diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c index 3c29a0df3c6..8a4c10e4c1f 100644 --- a/src/intel/isl/isl_drm.c +++ b/src/intel/isl/isl_drm.c @@ -132,7 +132,7 @@ uint32_t isl_drm_modifier_get_score(const struct gen_device_info *devinfo, uint64_t modifier) { - /* FINISHME: Add gen12 modifiers */ + /* FINISHME: Add gfx12 modifiers */ switch (modifier) { default: return 0; diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c index 45956dc47bd..36c026ff63f 100644 --- a/src/intel/isl/isl_format.c +++ b/src/intel/isl/isl_format.c @@ -69,9 +69,9 @@ struct surface_format_info { * * Y*: 45 * Y+: 45 (g45/gm45) - * Y~: 50 (gen5) - * Y^: 60 (gen6) - * Y#: 70 (gen7) + * Y~: 50 (gfx5) + * Y^: 60 (gfx6) + * Y#: 70 (gfx7) * * The abbreviations in the header below are: * smpl - Sampling Engine @@ -83,7 +83,7 @@ struct surface_format_info { * VB - Input Vertex Buffer * SO - Steamed Output Vertex Buffers (transform feedback) * color - Color Processing - * ccs_e - Lossless Compression Support (gen9+ only) + * ccs_e - Lossless Compression Support (gfx9+ only) * sf - Surface Format * * See page 88 of the Sandybridge PRM VOL4_Part1 PDF. @@ -297,7 +297,7 @@ static const struct surface_format_info format_info[] = { SF( x, x, x, x, x, x, x, x, x, x, x, x, PLANAR_420_8) /* The format enum for R8G8B8_UNORM_SRGB first shows up in the HSW PRM but * empirical testing indicates that it doesn't actually sRGB decode and - * acts identical to R8G8B8_UNORM. It does work on gen8+. + * acts identical to R8G8B8_UNORM. It does work on gfx8+. */ SF( 80, 80, x, x, x, x, x, x, x, x, x, x, R8G8B8_UNORM_SRGB) SF( 80, 80, x, x, x, x, x, x, x, x, x, x, ETC1_RGB8) diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c index f9a519fb137..db7c3d411e7 100644 --- a/src/intel/isl/isl_gfx12.c +++ b/src/intel/isl/isl_gfx12.c @@ -26,7 +26,7 @@ #include "isl_priv.h" void -isl_gen12_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx12_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, @@ -66,7 +66,7 @@ isl_gen12_choose_image_alignment_el(const struct isl_device *dev, } else if (isl_surf_usage_is_stencil(info->usage)) { *image_align_el = isl_extent3d(16, 8, 1); } else { - isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } } diff --git a/src/intel/isl/isl_gfx12.h b/src/intel/isl/isl_gfx12.h index 53983e694b9..0cc2f9cd63e 100644 --- a/src/intel/isl/isl_gfx12.h +++ b/src/intel/isl/isl_gfx12.h @@ -31,7 +31,7 @@ extern "C" { #endif void -isl_gen12_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx12_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx4.c b/src/intel/isl/isl_gfx4.c index 062593bc74a..144fb7fac67 100644 --- a/src/intel/isl/isl_gfx4.c +++ b/src/intel/isl/isl_gfx4.c @@ -25,7 +25,7 @@ #include "isl_priv.h" bool -isl_gen4_choose_msaa_layout(const struct isl_device *dev, +isl_gfx4_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) @@ -38,7 +38,7 @@ isl_gen4_choose_msaa_layout(const struct isl_device *dev, } void -isl_gen4_filter_tiling(const struct isl_device *dev, +isl_gfx4_filter_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, isl_tiling_flags_t *flags) { @@ -56,7 +56,7 @@ isl_gen4_filter_tiling(const struct isl_device *dev, * BWT014 The Depth Buffer Must be Tiled, it cannot be linear. This * field must be set to 1 on DevBW-A. [DevBW -A,B] * - * In testing, the linear configuration doesn't seem to work on gen4. + * In testing, the linear configuration doesn't seem to work on gfx4. */ *flags &= (ISL_GFX_VER(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ? ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT); @@ -96,7 +96,7 @@ isl_gen4_filter_tiling(const struct isl_device *dev, } void -isl_gen4_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx4_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, @@ -108,7 +108,7 @@ isl_gen4_choose_image_alignment_el(const struct isl_device *dev, assert(!isl_tiling_is_std_y(tiling)); /* Note that neither the surface's horizontal nor vertical image alignment - * is programmable on gen4 nor gen5. + * is programmable on gfx4 nor gfx5. * * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4 * Alignment Unit Size: diff --git a/src/intel/isl/isl_gfx4.h b/src/intel/isl/isl_gfx4.h index dc24b53f190..38b8dfdce79 100644 --- a/src/intel/isl/isl_gfx4.h +++ b/src/intel/isl/isl_gfx4.h @@ -31,18 +31,18 @@ extern "C" { #endif bool -isl_gen4_choose_msaa_layout(const struct isl_device *dev, +isl_gfx4_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout); void -isl_gen4_filter_tiling(const struct isl_device *dev, +isl_gfx4_filter_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, isl_tiling_flags_t *flags); void -isl_gen4_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx4_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx6.c b/src/intel/isl/isl_gfx6.c index b6657dd7a74..e3c6ccec2a7 100644 --- a/src/intel/isl/isl_gfx6.c +++ b/src/intel/isl/isl_gfx6.c @@ -25,7 +25,7 @@ #include "isl_priv.h" bool -isl_gen6_choose_msaa_layout(const struct isl_device *dev, +isl_gfx6_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) @@ -66,7 +66,7 @@ isl_gen6_choose_msaa_layout(const struct isl_device *dev, } void -isl_gen6_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx6_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx6.h b/src/intel/isl/isl_gfx6.h index 591f977cab4..932246ca777 100644 --- a/src/intel/isl/isl_gfx6.h +++ b/src/intel/isl/isl_gfx6.h @@ -31,13 +31,13 @@ extern "C" { #endif bool -isl_gen6_choose_msaa_layout(const struct isl_device *dev, +isl_gfx6_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout); void -isl_gen6_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx6_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx7.c b/src/intel/isl/isl_gfx7.c index 07c5401941e..f80ba544cbc 100644 --- a/src/intel/isl/isl_gfx7.c +++ b/src/intel/isl/isl_gfx7.c @@ -25,7 +25,7 @@ #include "isl_priv.h" static bool -gen7_format_needs_valign2(const struct isl_device *dev, +gfx7_format_needs_valign2(const struct isl_device *dev, enum isl_format format) { assert(ISL_GFX_VER(dev) == 7); @@ -46,7 +46,7 @@ gen7_format_needs_valign2(const struct isl_device *dev, } bool -isl_gen7_choose_msaa_layout(const struct isl_device *dev, +isl_gfx7_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) @@ -103,7 +103,7 @@ isl_gen7_choose_msaa_layout(const struct isl_device *dev, */ /* Multisampling requires vertical alignment of four. */ - if (info->samples > 1 && gen7_format_needs_valign2(dev, info->format)) + if (info->samples > 1 && gfx7_format_needs_valign2(dev, info->format)) return false; /* More obvious restrictions */ @@ -189,7 +189,7 @@ isl_gen7_choose_msaa_layout(const struct isl_device *dev, * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT. */ void -isl_gen6_filter_tiling(const struct isl_device *dev, +isl_gfx6_filter_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, isl_tiling_flags_t *flags) { @@ -286,7 +286,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev, /* workaround */ if (ISL_GFX_VER(dev) == 7 && - gen7_format_needs_valign2(dev, info->format) && + gfx7_format_needs_valign2(dev, info->format) && (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && info->samples == 1) { /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1, @@ -333,7 +333,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev, } void -isl_gen7_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx7_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, @@ -418,7 +418,7 @@ isl_gen7_choose_image_alignment_el(const struct isl_device *dev, (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)) require_valign4 = true; - assert(!(require_valign4 && gen7_format_needs_valign2(dev, info->format))); + assert(!(require_valign4 && gfx7_format_needs_valign2(dev, info->format))); /* We default to VALIGN_2 because it uses the least memory. */ const uint32_t valign = require_valign4 ? 4 : 2; diff --git a/src/intel/isl/isl_gfx7.h b/src/intel/isl/isl_gfx7.h index bf53a99cdf4..28b65eb6f19 100644 --- a/src/intel/isl/isl_gfx7.h +++ b/src/intel/isl/isl_gfx7.h @@ -31,18 +31,18 @@ extern "C" { #endif void -isl_gen6_filter_tiling(const struct isl_device *dev, +isl_gfx6_filter_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, isl_tiling_flags_t *flags); bool -isl_gen7_choose_msaa_layout(const struct isl_device *dev, +isl_gfx7_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout); void -isl_gen7_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx7_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx8.c b/src/intel/isl/isl_gfx8.c index d2ab1cb2eba..2139e2a6e95 100644 --- a/src/intel/isl/isl_gfx8.c +++ b/src/intel/isl/isl_gfx8.c @@ -25,7 +25,7 @@ #include "isl_priv.h" bool -isl_gen8_choose_msaa_layout(const struct isl_device *dev, +isl_gfx8_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) @@ -88,7 +88,7 @@ isl_gen8_choose_msaa_layout(const struct isl_device *dev, } void -isl_gen8_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx8_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx8.h b/src/intel/isl/isl_gfx8.h index 8fc8209de2e..12cb5b91754 100644 --- a/src/intel/isl/isl_gfx8.h +++ b/src/intel/isl/isl_gfx8.h @@ -31,13 +31,13 @@ extern "C" { #endif bool -isl_gen8_choose_msaa_layout(const struct isl_device *dev, +isl_gfx8_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout); void -isl_gen8_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx8_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_gfx9.c b/src/intel/isl/isl_gfx9.c index 77e55b6e768..1f2433800dc 100644 --- a/src/intel/isl/isl_gfx9.c +++ b/src/intel/isl/isl_gfx9.c @@ -30,7 +30,7 @@ * for the standard tiling formats Yf and Ys. */ static void -gen9_calc_std_image_alignment_sa(const struct isl_device *dev, +gfx9_calc_std_image_alignment_sa(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_msaa_layout msaa_layout, @@ -97,7 +97,7 @@ gen9_calc_std_image_alignment_sa(const struct isl_device *dev, } void -isl_gen9_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx9_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, @@ -167,7 +167,7 @@ isl_gen9_choose_image_alignment_el(const struct isl_device *dev, if (isl_tiling_is_std_y(tiling)) { struct isl_extent3d image_align_sa; - gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, + gfx9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, &image_align_sa); *image_align_el = isl_extent3d_sa_to_el(info->format, image_align_sa); @@ -196,6 +196,6 @@ isl_gen9_choose_image_alignment_el(const struct isl_device *dev, return; } - isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout, + isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } diff --git a/src/intel/isl/isl_gfx9.h b/src/intel/isl/isl_gfx9.h index b17bbda9e3f..9e1d8ae3aaf 100644 --- a/src/intel/isl/isl_gfx9.h +++ b/src/intel/isl/isl_gfx9.h @@ -31,7 +31,7 @@ extern "C" { #endif void -isl_gen9_choose_image_alignment_el(const struct isl_device *dev, +isl_gfx9_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h index 9a382711856..fc9d8c591e5 100644 --- a/src/intel/isl/isl_priv.h +++ b/src/intel/isl/isl_priv.h @@ -205,34 +205,34 @@ _isl_memcpy_tiled_to_linear_sse41(uint32_t xt1, uint32_t xt2, #ifdef genX # include "isl_genX_priv.h" #else -# define genX(x) gen4_##x +# define genX(x) gfx4_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen5_##x +# define genX(x) gfx5_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen6_##x +# define genX(x) gfx6_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen7_##x +# define genX(x) gfx7_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen75_##x +# define genX(x) gfx75_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen8_##x +# define genX(x) gfx8_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen9_##x +# define genX(x) gfx9_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen11_##x +# define genX(x) gfx11_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen12_##x +# define genX(x) gfx12_##x # include "isl_genX_priv.h" # undef genX -# define genX(x) gen125_##x +# define genX(x) gfx125_##x # include "isl_genX_priv.h" # undef genX #endif diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 9521b311ff9..75779086fc1 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -335,7 +335,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.Width = info->surf->logical_level0_px.width - 1; s.Height = info->surf->logical_level0_px.height - 1; - /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 + /* In the gfx6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 * (Surface Arrays For all surfaces other than separate stencil buffer): * * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value @@ -477,7 +477,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { - /* For gen9 1-D textures, surface pitch is ignored */ + /* For gfx9 1-D textures, surface pitch is ignored */ s.SurfacePitch = 0; } else { s.SurfacePitch = info->surf->row_pitch_B - 1; @@ -614,7 +614,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * and the data port. Testing seems to indicate that the data port * completely ignores the AuxiliarySurfaceMode field. * - * On gen12 HDC supports compression. + * On gfx12 HDC supports compression. */ if (GFX_VER < 12) assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c index 6e5a76e7736..ead3d802237 100644 --- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c +++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c @@ -101,7 +101,7 @@ t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width, } static void -t_assert_gen4_3d_layer(const struct isl_surf *surf, +t_assert_gfx4_3d_layer(const struct isl_surf *surf, uint32_t level, uint32_t aligned_width, uint32_t aligned_height, @@ -261,15 +261,15 @@ test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void) uint32_t base_y = 0; - t_assert_gen4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y); - t_assert_gen4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y); - t_assert_gen4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y); - t_assert_gen4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y); - t_assert_gen4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y); + t_assert_gfx4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y); + t_assert_gfx4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y); + t_assert_gfx4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y); + t_assert_gfx4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y); + t_assert_gfx4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y); + t_assert_gfx4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y); + t_assert_gfx4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y); + t_assert_gfx4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y); + t_assert_gfx4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y); } int main(void) diff --git a/src/intel/perf/gen_perf.c b/src/intel/perf/gen_perf.c index aee37a59e12..bfc261d68cf 100644 --- a/src/intel/perf/gen_perf.c +++ b/src/intel/perf/gen_perf.c @@ -984,7 +984,7 @@ accumulate_uint40(int a_index, } static void -gen8_read_report_clock_ratios(const uint32_t *report, +gfx8_read_report_clock_ratios(const uint32_t *report, uint64_t *slice_freq_hz, uint64_t *unslice_freq_hz) { @@ -1029,10 +1029,10 @@ gen_perf_query_result_read_frequencies(struct gen_perf_query_result *result, if (devinfo->ver < 8) return; - gen8_read_report_clock_ratios(start, + gfx8_read_report_clock_ratios(start, &result->slice_frequency[0], &result->unslice_frequency[0]); - gen8_read_report_clock_ratios(end, + gfx8_read_report_clock_ratios(end, &result->slice_frequency[1], &result->unslice_frequency[1]); } diff --git a/src/intel/perf/gen_perf_mdapi.c b/src/intel/perf/gen_perf_mdapi.c index 4296d7e2883..5508baba589 100644 --- a/src/intel/perf/gen_perf_mdapi.c +++ b/src/intel/perf/gen_perf_mdapi.c @@ -39,7 +39,7 @@ gen_perf_query_result_write_mdapi(void *data, uint32_t data_size, { switch (devinfo->ver) { case 7: { - struct gen7_mdapi_metrics *mdapi_data = (struct gen7_mdapi_metrics *) data; + struct gfx7_mdapi_metrics *mdapi_data = (struct gfx7_mdapi_metrics *) data; if (data_size < sizeof(*mdapi_data)) return 0; @@ -66,7 +66,7 @@ gen_perf_query_result_write_mdapi(void *data, uint32_t data_size, return sizeof(*mdapi_data); } case 8: { - struct gen8_mdapi_metrics *mdapi_data = (struct gen8_mdapi_metrics *) data; + struct gfx8_mdapi_metrics *mdapi_data = (struct gfx8_mdapi_metrics *) data; if (data_size < sizeof(*mdapi_data)) return 0; @@ -100,7 +100,7 @@ gen_perf_query_result_write_mdapi(void *data, uint32_t data_size, case 9: case 11: case 12:{ - struct gen9_mdapi_metrics *mdapi_data = (struct gen9_mdapi_metrics *) data; + struct gfx9_mdapi_metrics *mdapi_data = (struct gfx9_mdapi_metrics *) data; if (data_size < sizeof(*mdapi_data)) return 0; @@ -245,7 +245,7 @@ gen_perf_register_mdapi_oa_query(struct gen_perf_config *perf, query = gen_perf_append_query_info(perf, 1 + 45 + 16 + 7); query->oa_format = I915_OA_FORMAT_A45_B8_C8; - struct gen7_mdapi_metrics metric_data; + struct gfx7_mdapi_metrics metric_data; query->data_size = sizeof(metric_data); MDAPI_QUERY_ADD_COUNTER(query, metric_data, TotalTime, UINT64); @@ -270,7 +270,7 @@ gen_perf_register_mdapi_oa_query(struct gen_perf_config *perf, query = gen_perf_append_query_info(perf, 2 + 36 + 16 + 16); query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8; - struct gen8_mdapi_metrics metric_data; + struct gfx8_mdapi_metrics metric_data; query->data_size = sizeof(metric_data); MDAPI_QUERY_ADD_COUNTER(query, metric_data, TotalTime, UINT64); @@ -307,7 +307,7 @@ gen_perf_register_mdapi_oa_query(struct gen_perf_config *perf, query = gen_perf_append_query_info(perf, 2 + 36 + 16 + 16 + 16 + 2); query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8; - struct gen9_mdapi_metrics metric_data; + struct gfx9_mdapi_metrics metric_data; query->data_size = sizeof(metric_data); MDAPI_QUERY_ADD_COUNTER(query, metric_data, TotalTime, UINT64); diff --git a/src/intel/perf/gen_perf_mdapi.h b/src/intel/perf/gen_perf_mdapi.h index 9e518b5da95..5e9b2884994 100644 --- a/src/intel/perf/gen_perf_mdapi.h +++ b/src/intel/perf/gen_perf_mdapi.h @@ -37,7 +37,7 @@ struct gen_perf_query_result; * Data format expected by MDAPI. */ -struct gen7_mdapi_metrics { +struct gfx7_mdapi_metrics { uint64_t TotalTime; uint64_t ACounters[45]; @@ -55,7 +55,7 @@ struct gen7_mdapi_metrics { #define GTDI_QUERY_BDW_METRICS_OA_COUNT 36 #define GTDI_QUERY_BDW_METRICS_OA_40b_COUNT 32 #define GTDI_QUERY_BDW_METRICS_NOA_COUNT 16 -struct gen8_mdapi_metrics { +struct gfx8_mdapi_metrics { uint64_t TotalTime; uint64_t GPUTicks; uint64_t OaCntr[GTDI_QUERY_BDW_METRICS_OA_COUNT]; @@ -81,7 +81,7 @@ struct gen8_mdapi_metrics { #define GTDI_MAX_READ_REGS 16 -struct gen9_mdapi_metrics { +struct gfx9_mdapi_metrics { uint64_t TotalTime; uint64_t GPUTicks; uint64_t OaCntr[GTDI_QUERY_BDW_METRICS_OA_COUNT]; @@ -110,7 +110,7 @@ struct gen9_mdapi_metrics { }; /* Add new definition */ -#define gen11_mdapi_metrics gen9_mdapi_metrics +#define gfx11_mdapi_metrics gfx9_mdapi_metrics struct mdapi_pipeline_metrics { uint64_t IAVertices; @@ -138,17 +138,17 @@ static inline void gen_perf_query_mdapi_write_marker(void *data, uint32_t data_s { switch (devinfo->ver) { case 8: { - if (data_size < sizeof(struct gen8_mdapi_metrics)) + if (data_size < sizeof(struct gfx8_mdapi_metrics)) return; - struct gen8_mdapi_metrics *mdapi_data = data; + struct gfx8_mdapi_metrics *mdapi_data = data; mdapi_data->MarkerUser = value; break; } case 9: case 11: { - if (data_size < sizeof(struct gen9_mdapi_metrics)) + if (data_size < sizeof(struct gfx9_mdapi_metrics)) return; - struct gen9_mdapi_metrics *mdapi_data = data; + struct gfx9_mdapi_metrics *mdapi_data = data; mdapi_data->MarkerUser = value; break; } diff --git a/src/intel/perf/gen_perf_regs.h b/src/intel/perf/gen_perf_regs.h index ad76507457e..67e7ece4143 100644 --- a/src/intel/perf/gen_perf_regs.h +++ b/src/intel/perf/gen_perf_regs.h @@ -40,7 +40,7 @@ #define GFX9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0) /* Programmable perf 64bits counters (used for GTRequestQueueFull counter on - * gen7-11) + * gfx7-11) */ #define PERF_CNT_1_DW0 0x91b8 #define PERF_CNT_2_DW0 0x91c0 diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c index 1433f7a5a84..20e7504bd66 100644 --- a/src/intel/tools/aub_write.c +++ b/src/intel/tools/aub_write.c @@ -467,23 +467,23 @@ get_context_init(const struct gen_device_info *devinfo, uint32_t *data, uint32_t *size) { - static const gen_context_init_t gen8_contexts[] = { - [I915_ENGINE_CLASS_RENDER] = gen8_render_context_init, - [I915_ENGINE_CLASS_COPY] = gen8_blitter_context_init, - [I915_ENGINE_CLASS_VIDEO] = gen8_video_context_init, + static const gen_context_init_t gfx8_contexts[] = { + [I915_ENGINE_CLASS_RENDER] = gfx8_render_context_init, + [I915_ENGINE_CLASS_COPY] = gfx8_blitter_context_init, + [I915_ENGINE_CLASS_VIDEO] = gfx8_video_context_init, }; - static const gen_context_init_t gen10_contexts[] = { - [I915_ENGINE_CLASS_RENDER] = gen10_render_context_init, - [I915_ENGINE_CLASS_COPY] = gen10_blitter_context_init, - [I915_ENGINE_CLASS_VIDEO] = gen10_video_context_init, + static const gen_context_init_t gfx10_contexts[] = { + [I915_ENGINE_CLASS_RENDER] = gfx10_render_context_init, + [I915_ENGINE_CLASS_COPY] = gfx10_blitter_context_init, + [I915_ENGINE_CLASS_VIDEO] = gfx10_video_context_init, }; assert(devinfo->ver >= 8); if (devinfo->ver <= 10) - gen8_contexts[engine_class](params, data, size); + gfx8_contexts[engine_class](params, data, size); else - gen10_contexts[engine_class](params, data, size); + gfx10_contexts[engine_class](params, data, size); } static uint64_t diff --git a/src/intel/tools/aubinator_viewer_decoder.cpp b/src/intel/tools/aubinator_viewer_decoder.cpp index dc10f1df235..61f6b17f5c1 100644 --- a/src/intel/tools/aubinator_viewer_decoder.cpp +++ b/src/intel/tools/aubinator_viewer_decoder.cpp @@ -618,7 +618,7 @@ decode_3dstate_sampler_state_pointers(struct aub_viewer_decode_ctx *ctx, } static void -decode_3dstate_sampler_state_pointers_gen6(struct aub_viewer_decode_ctx *ctx, +decode_3dstate_sampler_state_pointers_gfx6(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) { @@ -864,7 +864,7 @@ struct custom_decoder { { "3DSTATE_SAMPLER_STATE_POINTERS_DS", decode_3dstate_sampler_state_pointers, AUB_DECODE_STAGE_DS, }, { "3DSTATE_SAMPLER_STATE_POINTERS_HS", decode_3dstate_sampler_state_pointers, AUB_DECODE_STAGE_HS, }, { "3DSTATE_SAMPLER_STATE_POINTERS_PS", decode_3dstate_sampler_state_pointers, AUB_DECODE_STAGE_PS, }, - { "3DSTATE_SAMPLER_STATE_POINTERS", decode_3dstate_sampler_state_pointers_gen6 }, + { "3DSTATE_SAMPLER_STATE_POINTERS", decode_3dstate_sampler_state_pointers_gfx6 }, { "3DSTATE_VIEWPORT_STATE_POINTERS_CC", decode_3dstate_viewport_state_pointers_cc }, { "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", decode_3dstate_viewport_state_pointers_sf_clip }, diff --git a/src/intel/tools/gfx10_context.h b/src/intel/tools/gfx10_context.h index a45b0f50f64..13c016a2fa3 100644 --- a/src/intel/tools/gfx10_context.h +++ b/src/intel/tools/gfx10_context.h @@ -24,7 +24,7 @@ #ifndef GFX10_CONTEXT_H #define GFX10_CONTEXT_H -static inline void gen10_render_context_init(const struct gen_context_parameters *params, +static inline void gfx10_render_context_init(const struct gen_context_parameters *params, uint32_t *data, uint32_t *size) { *size = CONTEXT_RENDER_SIZE; @@ -75,7 +75,7 @@ static inline void gen10_render_context_init(const struct gen_context_parameters *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */; } -static inline void gen10_blitter_context_init(const struct gen_context_parameters *params, +static inline void gfx10_blitter_context_init(const struct gen_context_parameters *params, uint32_t *data, uint32_t *size) { *size = CONTEXT_OTHER_SIZE; @@ -125,7 +125,7 @@ static inline void gen10_blitter_context_init(const struct gen_context_parameter *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */; } -static inline void gen10_video_context_init(const struct gen_context_parameters *params, +static inline void gfx10_video_context_init(const struct gen_context_parameters *params, uint32_t *data, uint32_t *size) { *size = CONTEXT_OTHER_SIZE; diff --git a/src/intel/tools/gfx8_context.h b/src/intel/tools/gfx8_context.h index fbfe473ce9b..7357ea44d90 100644 --- a/src/intel/tools/gfx8_context.h +++ b/src/intel/tools/gfx8_context.h @@ -24,7 +24,7 @@ #ifndef GFX8_CONTEXT_H #define GFX8_CONTEXT_H -static inline void gen8_render_context_init(const struct gen_context_parameters *params, +static inline void gfx8_render_context_init(const struct gen_context_parameters *params, uint32_t *data, uint32_t *size) { *size = CONTEXT_RENDER_SIZE; @@ -73,7 +73,7 @@ static inline void gen8_render_context_init(const struct gen_context_parameters *data++ = MI_BATCH_BUFFER_END; } -static inline void gen8_blitter_context_init(const struct gen_context_parameters *params, +static inline void gfx8_blitter_context_init(const struct gen_context_parameters *params, uint32_t *data, uint32_t *size) { *size = CONTEXT_OTHER_SIZE; @@ -115,7 +115,7 @@ static inline void gen8_blitter_context_init(const struct gen_context_parameters *data++ = MI_BATCH_BUFFER_END; } -static inline void gen8_video_context_init(const struct gen_context_parameters *params, +static inline void gfx8_video_context_init(const struct gen_context_parameters *params, uint32_t *data, uint32_t *size) { *size = CONTEXT_OTHER_SIZE; diff --git a/src/intel/tools/i965_asm.c b/src/intel/tools/i965_asm.c index 4181690568e..6fae53c2eec 100644 --- a/src/intel/tools/i965_asm.c +++ b/src/intel/tools/i965_asm.c @@ -153,7 +153,7 @@ i965_postprocess_labels() if (p->devinfo->ver >= 7) { brw_inst_set_jip(p->devinfo, inst, relative_offset); } else if (p->devinfo->ver == 6) { - brw_inst_set_gen6_jump_count(p->devinfo, inst, relative_offset); + brw_inst_set_gfx6_jump_count(p->devinfo, inst, relative_offset); } break; case BRW_OPCODE_BREAK: diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y index 290b495d013..4e191acc459 100644 --- a/src/intel/tools/i965_gram.y +++ b/src/intel/tools/i965_gram.y @@ -829,7 +829,7 @@ mathinstruction: predicate MATH saturate math_function execsize dst src srcimm instoptions { brw_set_default_access_mode(p, $9.access_mode); - gen6_math(p, $6, $4, $7, $8); + gfx6_math(p, $6, $4, $7, $8); i965_asm_set_instruction_options(p, $9); brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5); brw_inst_set_saturate(p->devinfo, brw_last_inst, $3); @@ -1137,7 +1137,7 @@ branchinstruction: brw_set_src0(p, brw_last_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $4); brw_inst_set_thread_control(p->devinfo, brw_last_inst, BRW_THREAD_SWITCH); @@ -1181,8 +1181,8 @@ branchinstruction: brw_set_dest(p, brw_last_inst, brw_ip_reg()); brw_set_src0(p, brw_last_inst, brw_ip_reg()); brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $3); - brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $3); + brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $4); if (!p->single_program_flow) brw_inst_set_thread_control(p->devinfo, brw_last_inst, @@ -1232,8 +1232,8 @@ branchinstruction: brw_set_dest(p, brw_last_inst, brw_ip_reg()); brw_set_src0(p, brw_last_inst, brw_ip_reg()); brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5); + brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5); if (!p->single_program_flow) brw_inst_set_thread_control(p->devinfo, brw_last_inst, @@ -1282,7 +1282,7 @@ branchinstruction: brw_set_dest(p, brw_last_inst, brw_ip_reg()); brw_set_src0(p, brw_last_inst, brw_ip_reg()); - brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); brw_set_src1(p, brw_last_inst, brw_imm_d($4)); if (!p->single_program_flow) @@ -1327,8 +1327,8 @@ breakinstruction: brw_set_dest(p, brw_last_inst, brw_ip_reg()); brw_set_src0(p, brw_last_inst, brw_ip_reg()); brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5); + brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5); brw_pop_insn_state(p); } @@ -1383,8 +1383,8 @@ breakinstruction: brw_set_src0(p, brw_last_inst, brw_ip_reg()); brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5); + brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, $5); brw_pop_insn_state(p); } @@ -1435,8 +1435,8 @@ loopinstruction: brw_set_dest(p, brw_last_inst, brw_ip_reg()); brw_set_src0(p, brw_last_inst, brw_ip_reg()); brw_set_src1(p, brw_last_inst, brw_imm_d(0x0)); - brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4); - brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, 0); + brw_inst_set_gfx4_jump_count(p->devinfo, brw_last_inst, $4); + brw_inst_set_gfx4_pop_count(p->devinfo, brw_last_inst, 0); brw_pop_insn_state(p); } diff --git a/src/intel/tools/intel_noop_drm_shim.c b/src/intel/tools/intel_noop_drm_shim.c index a9c8cd57d7e..0486303962e 100644 --- a/src/intel/tools/intel_noop_drm_shim.c +++ b/src/intel/tools/intel_noop_drm_shim.c @@ -160,17 +160,17 @@ i915_ioctl_get_param(int fd, unsigned long request, void *arg) return 0; case I915_PARAM_NUM_FENCES_AVAIL: - *gp->value = 8; /* gen2/3 value, unused in brw/iris */ + *gp->value = 8; /* gfx2/3 value, unused in brw/iris */ return 0; case I915_PARAM_HAS_BLT: - *gp->value = 1; /* gen2/3 value, unused in brw/iris */ + *gp->value = 1; /* gfx2/3 value, unused in brw/iris */ return 0; case I915_PARAM_HAS_BSD: case I915_PARAM_HAS_LLC: case I915_PARAM_HAS_VEBOX: - *gp->value = 0; /* gen2/3 value, unused in brw/iris */ + *gp->value = 0; /* gfx2/3 value, unused in brw/iris */ return 0; case I915_PARAM_HAS_GEM: diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO index b4da05de2b1..4c41e251888 100644 --- a/src/intel/vulkan/TODO +++ b/src/intel/vulkan/TODO @@ -6,7 +6,7 @@ Missing Features: - Sparse memory Performance: - - Multi-{sampled/gen8,LOD} HiZ + - Multi-{sampled/gfx8,LOD} HiZ - MSAA fast clears - Pushing pieces of UBOs? - Enable guardband clipping diff --git a/src/intel/vulkan/anv_batch_chain.c b/src/intel/vulkan/anv_batch_chain.c index 642ba0a08fd..9add43fe947 100644 --- a/src/intel/vulkan/anv_batch_chain.c +++ b/src/intel/vulkan/anv_batch_chain.c @@ -569,8 +569,8 @@ static void emit_batch_buffer_start(struct anv_cmd_buffer *cmd_buffer, struct anv_bo *bo, uint32_t offset) { - /* In gen8+ the address field grew to two dwords to accomodate 48 bit - * offsets. The high 16 bits are in the last dword, so we can use the gen8 + /* In gfx8+ the address field grew to two dwords to accomodate 48 bit + * offsets. The high 16 bits are in the last dword, so we can use the gfx8 * version in either case, as long as we set the instruction length in the * header accordingly. This means that we always emit three dwords here * and all the padding and adjustment we do in this file works for all @@ -580,14 +580,14 @@ emit_batch_buffer_start(struct anv_cmd_buffer *cmd_buffer, #define GFX7_MI_BATCH_BUFFER_START_length 2 #define GFX7_MI_BATCH_BUFFER_START_length_bias 2 - const uint32_t gen7_length = + const uint32_t gfx7_length = GFX7_MI_BATCH_BUFFER_START_length - GFX7_MI_BATCH_BUFFER_START_length_bias; - const uint32_t gen8_length = + const uint32_t gfx8_length = GFX8_MI_BATCH_BUFFER_START_length - GFX8_MI_BATCH_BUFFER_START_length_bias; anv_batch_emit(&cmd_buffer->batch, GFX8_MI_BATCH_BUFFER_START, bbs) { bbs.DWordLength = cmd_buffer->device->info.ver < 8 ? - gen7_length : gen8_length; + gfx7_length : gfx8_length; bbs.SecondLevelBatchBuffer = Firstlevelbatch; bbs.AddressSpaceIndicator = ASI_PPGTT; bbs.BatchBufferStartAddress = (struct anv_address) { bo, offset }; diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 3b636620389..d974d868ed0 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -98,25 +98,25 @@ anv_device_init_blorp(struct anv_device *device) device->blorp.upload_shader = upload_blorp_shader; switch (device->info.verx10) { case 70: - device->blorp.exec = gen7_blorp_exec; + device->blorp.exec = gfx7_blorp_exec; break; case 75: - device->blorp.exec = gen75_blorp_exec; + device->blorp.exec = gfx75_blorp_exec; break; case 80: - device->blorp.exec = gen8_blorp_exec; + device->blorp.exec = gfx8_blorp_exec; break; case 90: - device->blorp.exec = gen9_blorp_exec; + device->blorp.exec = gfx9_blorp_exec; break; case 110: - device->blorp.exec = gen11_blorp_exec; + device->blorp.exec = gfx11_blorp_exec; break; case 120: - device->blorp.exec = gen12_blorp_exec; + device->blorp.exec = gfx12_blorp_exec; break; case 125: - device->blorp.exec = gen125_blorp_exec; + device->blorp.exec = gfx125_blorp_exec; break; default: unreachable("Unknown hardware generation"); diff --git a/src/intel/vulkan/anv_descriptor_set.c b/src/intel/vulkan/anv_descriptor_set.c index 33c1965341c..f59608cd921 100644 --- a/src/intel/vulkan/anv_descriptor_set.c +++ b/src/intel/vulkan/anv_descriptor_set.c @@ -95,7 +95,7 @@ anv_descriptor_data_for_type(const struct anv_physical_device *device, unreachable("Unsupported descriptor type"); } - /* On gen8 and above when we have softpin enabled, we also need to push + /* On gfx8 and above when we have softpin enabled, we also need to push * SSBO address ranges so that we can use A64 messages in the shader. */ if (device->has_a64_buffer_access && diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 84daba2caca..204aa2ea50d 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -811,7 +811,7 @@ anv_physical_device_try_create(struct anv_instance *instance, /* We've had bindless samplers since Ivy Bridge (forever in Vulkan terms) * because it's just a matter of setting the sampler address in the sample * message header. However, we've not bothered to wire it up for vec4 so - * we leave it disabled on gen7. + * we leave it disabled on gfx7. */ device->has_bindless_samplers = device->info.ver >= 8; @@ -1486,7 +1486,7 @@ void anv_GetPhysicalDeviceFeatures2( (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext; features->rectangularLines = true; features->bresenhamLines = true; - /* Support for Smooth lines with MSAA was removed on gen11. From the + /* Support for Smooth lines with MSAA was removed on gfx11. From the * BSpec section "Multisample ModesState" table for "AA Line Support * Requirements": * @@ -1958,7 +1958,7 @@ anv_get_physical_device_properties_1_1(struct anv_physical_device *pdevice, VK_SUBGROUP_FEATURE_QUAD_BIT; if (pdevice->info.ver >= 8) { /* TODO: There's no technical reason why these can't be made to - * work on gen7 but they don't at the moment so it's best to leave + * work on gfx7 but they don't at the moment so it's best to leave * the feature disabled than enabled and broken. */ p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_ARITHMETIC_BIT | @@ -2716,7 +2716,7 @@ anv_device_init_border_colors(struct anv_device *device) anv_state_pool_emit_data(&device->dynamic_state_pool, sizeof(border_colors), 512, border_colors); } else { - static const struct gen8_border_color border_colors[] = { + static const struct gfx8_border_color border_colors[] = { [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = { .float32 = { 0.0, 0.0, 0.0, 0.0 } }, [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = { .float32 = { 0.0, 0.0, 0.0, 1.0 } }, [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = { .float32 = { 1.0, 1.0, 1.0, 1.0 } }, @@ -3186,7 +3186,7 @@ VkResult anv_CreateDevice( anv_state_reserved_pool_init(&device->custom_border_colors, &device->dynamic_state_pool, MAX_CUSTOM_BORDER_COLORS, - sizeof(struct gen8_border_color), 64); + sizeof(struct gfx8_border_color), 64); } result = anv_state_pool_init(&device->instruction_state_pool, device, diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c index cc5ba6ebbfe..fcb0842c143 100644 --- a/src/intel/vulkan/anv_formats.c +++ b/src/intel/vulkan/anv_formats.c @@ -1113,8 +1113,8 @@ anv_get_image_format_properties( } /* From the bspec section entitled "Surface Layout and Tiling", - * pre-gen9 has a 2 GB limitation of the size in bytes, - * gen9 and gen10 have a 256 GB limitation and gen11+ + * pre-gfx9 has a 2 GB limitation of the size in bytes, + * gfx9 and gfx10 have a 256 GB limitation and gfx11+ * has a 16 TB limitation. */ uint64_t maxResourceSize = 0; diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 39e6b261242..e1e44127acd 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -54,13 +54,13 @@ void genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer); -void genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer); +void genX(cmd_buffer_emit_gfx7_depth_flush)(struct anv_cmd_buffer *cmd_buffer); -void genX(cmd_buffer_set_binding_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, +void genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, int vb_index, struct anv_address vb_address, uint32_t vb_size); -void genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, +void genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, uint32_t access_type, uint64_t vb_used); diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 2cdc9051f86..588e14d61a7 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -261,7 +261,7 @@ anv_image_plane_needs_shadow_surface(const struct gen_device_info *devinfo, (vk_create_flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) && vk_tiling == VK_IMAGE_TILING_OPTIMAL) { /* We must fallback to a linear surface because we may not be able to - * correctly handle the offsets if tiled. (On gen9, + * correctly handle the offsets if tiled. (On gfx9, * RENDER_SURFACE_STATE::X/Y Offset are sufficient). To prevent garbage * performance while texturing, we maintain a tiled shadow surface. */ @@ -277,7 +277,7 @@ anv_image_plane_needs_shadow_surface(const struct gen_device_info *devinfo, if (devinfo->ver <= 7 && plane_format.aspect == VK_IMAGE_ASPECT_STENCIL_BIT && (vk_plane_usage & VK_IMAGE_USAGE_SAMPLED_BIT)) { - /* gen7 can't sample from W-tiled surfaces. */ + /* gfx7 can't sample from W-tiled surfaces. */ return true; } @@ -333,7 +333,7 @@ anv_formats_ccs_e_compatible(const struct gen_device_info *devinfo, * * * 1 or 4 dwords (depending on hardware generation) for the clear color * * 1 dword for the anv_fast_clear_type of the clear color - * * On gen9+, 1 dword per level and layer of the image (3D levels count + * * On gfx9+, 1 dword per level and layer of the image (3D levels count * multiple layers) in level-major order for compression state. * * For the purpose of discoverability, the algorithm used to manage @@ -361,7 +361,7 @@ anv_formats_ccs_e_compatible(const struct gen_device_info *devinfo, * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for * details on exactly what is allowed in what layouts. * - * On gen7-9, we do not have a concept of indirect clear colors in hardware. + * On gfx7-9, we do not have a concept of indirect clear colors in hardware. * In order to deal with this, we have to do some clear color management. * * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear @@ -434,7 +434,7 @@ add_aux_surface_if_supported(struct anv_device *device, */ assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)); - /* Allow the user to control HiZ enabling. Disable by default on gen7 + /* Allow the user to control HiZ enabling. Disable by default on gfx7 * because resolves are not currently implemented pre-BDW. */ if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) { @@ -443,7 +443,7 @@ add_aux_surface_if_supported(struct anv_device *device, } if (device->info.ver == 7) { - anv_perf_warn(device, &image->base, "Implement gen7 HiZ"); + anv_perf_warn(device, &image->base, "Implement gfx7 HiZ"); return VK_SUCCESS; } @@ -453,7 +453,7 @@ add_aux_surface_if_supported(struct anv_device *device, } if (device->info.ver == 8 && image->samples > 1) { - anv_perf_warn(device, &image->base, "Enable gen8 multisampled HiZ"); + anv_perf_warn(device, &image->base, "Enable gfx8 multisampled HiZ"); return VK_SUCCESS; } @@ -2033,7 +2033,7 @@ anv_image_fill_surface_state(struct anv_device *device, surface = &image->planes[plane].shadow_surface; } - /* For texturing from stencil on gen7, we have to sample from a shadow + /* For texturing from stencil on gfx7, we have to sample from a shadow * surface because we don't support W-tiling in the sampler. */ if (anv_surface_is_valid(&image->planes[plane].shadow_surface) && @@ -2178,7 +2178,7 @@ anv_image_fill_surface_state(struct anv_device *device, .x_offset_sa = tile_x_sa, .y_offset_sa = tile_y_sa); - /* With the exception of gen8, the bottom 12 bits of the MCS base address + /* With the exception of gfx8, the bottom 12 bits of the MCS base address * are used to store other information. This should be ok, however, * because the surface buffer addresses are always 4K page aligned. */ diff --git a/src/intel/vulkan/anv_measure.c b/src/intel/vulkan/anv_measure.c index b3dd5e71e26..2ac654b7c05 100644 --- a/src/intel/vulkan/anv_measure.c +++ b/src/intel/vulkan/anv_measure.c @@ -40,25 +40,25 @@ anv_measure_device_init(struct anv_physical_device *device) { switch (device->info.verx10) { case 125: - device->cmd_emit_timestamp = &gen125_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx125_cmd_emit_timestamp; break; case 120: - device->cmd_emit_timestamp = &gen12_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx12_cmd_emit_timestamp; break; case 110: - device->cmd_emit_timestamp = &gen11_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx11_cmd_emit_timestamp; break; case 90: - device->cmd_emit_timestamp = &gen9_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx9_cmd_emit_timestamp; break; case 80: - device->cmd_emit_timestamp = &gen8_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx8_cmd_emit_timestamp; break; case 75: - device->cmd_emit_timestamp = &gen75_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx75_cmd_emit_timestamp; break; case 70: - device->cmd_emit_timestamp = &gen7_cmd_emit_timestamp; + device->cmd_emit_timestamp = &gfx7_cmd_emit_timestamp; break; default: assert(false); diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index 11af2ff1c64..6d202a6a015 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -1184,7 +1184,7 @@ build_def_array_select(nir_builder *b, nir_ssa_def **srcs, nir_ssa_def *idx, } static void -lower_gen7_tex_swizzle(nir_builder *b, nir_tex_instr *tex, unsigned plane, +lower_gfx7_tex_swizzle(nir_builder *b, nir_tex_instr *tex, unsigned plane, struct apply_pipeline_layout_state *state) { assert(state->pdevice->info.ver == 7 && !state->pdevice->info.is_haswell); @@ -1260,7 +1260,7 @@ lower_tex(nir_builder *b, nir_tex_instr *tex, * before we lower the derefs away so we can still find the descriptor. */ if (state->pdevice->info.ver == 7 && !state->pdevice->info.is_haswell) - lower_gen7_tex_swizzle(b, tex, plane, state); + lower_gfx7_tex_swizzle(b, tex, plane, state); b->cursor = nir_before_instr(&tex->instr); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 20c3806a1fc..36675010767 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -240,7 +240,7 @@ struct gen_perf_query_result; */ #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */ -/* For gen12 we set the streamout buffers using 4 separate commands +/* For gfx12 we set the streamout buffers using 4 separate commands * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the @@ -895,7 +895,7 @@ struct anv_physical_device { /** Amount of "GPU memory" we want to advertise * * Clearly, this value is bogus since Intel is a UMA architecture. On - * gen7 platforms, we are limited by GTT size unless we want to implement + * gfx7 platforms, we are limited by GTT size unless we want to implement * fine-grained tracking and GTT splitting. On Broadwell and above we are * practically unlimited. However, we will never report more than 3/4 of * the total system ram to try and avoid running out of RAM. @@ -2672,7 +2672,7 @@ struct anv_surface_state { * * This field is ANV_NULL_ADDRESS if and only if no aux surface exists. * - * With the exception of gen8, the bottom 12 bits of this address' offset + * With the exception of gfx8, the bottom 12 bits of this address' offset * include extra aux information. */ struct anv_address aux_address; @@ -2779,7 +2779,7 @@ struct anv_cmd_graphics_state { struct anv_buffer *index_buffer; uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */ uint32_t index_offset; - } gen7; + } gfx7; }; /** State tracking for compute pipeline @@ -2831,7 +2831,7 @@ struct anv_cmd_state { unsigned char push_sha1s[MESA_SHADER_STAGES][20]; /** - * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top + * Whether or not the gfx8 PMA fix is enabled. We ensure that, at the top * of any command buffer it is disabled by disabling it in EndCommandBuffer * and before invoking the secondary in ExecuteCommands. */ @@ -3023,10 +3023,10 @@ anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer, VkResult anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer); -void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer); -void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer, +void gfx8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer); +void gfx8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer, bool depth_clamp_enable); -void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer); +void gfx7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer); void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer, struct anv_render_pass *pass, @@ -3393,17 +3393,17 @@ struct anv_graphics_pipeline { uint32_t depth_stencil_state[3]; uint32_t clip[4]; uint32_t xfb_bo_pitch[4]; - } gen7; + } gfx7; struct { uint32_t sf[4]; uint32_t raster[5]; uint32_t wm_depth_stencil[3]; - } gen8; + } gfx8; struct { uint32_t wm_depth_stencil[4]; - } gen9; + } gfx9; }; struct anv_compute_pipeline { @@ -4271,7 +4271,7 @@ struct hsw_border_color { uint32_t _pad1[108]; }; -struct gen8_border_color { +struct gfx8_border_color { union { float float32[4]; uint32_t uint32[4]; @@ -4532,28 +4532,28 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(anv_performance_configuration_intel, base, VK_OBJECT_TYPE_PERFORMANCE_CONFIGURATION_INTEL) #define anv_genX(devinfo, thing) ({ \ - __typeof(&gen9_##thing) genX_thing; \ + __typeof(&gfx9_##thing) genX_thing; \ switch ((devinfo)->verx10) { \ case 70: \ - genX_thing = &gen7_##thing; \ + genX_thing = &gfx7_##thing; \ break; \ case 75: \ - genX_thing = &gen75_##thing; \ + genX_thing = &gfx75_##thing; \ break; \ case 80: \ - genX_thing = &gen8_##thing; \ + genX_thing = &gfx8_##thing; \ break; \ case 90: \ - genX_thing = &gen9_##thing; \ + genX_thing = &gfx9_##thing; \ break; \ case 110: \ - genX_thing = &gen11_##thing; \ + genX_thing = &gfx11_##thing; \ break; \ case 120: \ - genX_thing = &gen12_##thing; \ + genX_thing = &gfx12_##thing; \ break; \ case 125: \ - genX_thing = &gen125_##thing; \ + genX_thing = &gfx125_##thing; \ break; \ default: \ unreachable("Unknown hardware generation"); \ @@ -4565,25 +4565,25 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(anv_performance_configuration_intel, base, #ifdef genX # include "anv_genX.h" #else -# define genX(x) gen7_##x +# define genX(x) gfx7_##x # include "anv_genX.h" # undef genX -# define genX(x) gen75_##x +# define genX(x) gfx75_##x # include "anv_genX.h" # undef genX -# define genX(x) gen8_##x +# define genX(x) gfx8_##x # include "anv_genX.h" # undef genX -# define genX(x) gen9_##x +# define genX(x) gfx9_##x # include "anv_genX.h" # undef genX -# define genX(x) gen11_##x +# define genX(x) gfx11_##x # include "anv_genX.h" # undef genX -# define genX(x) gen12_##x +# define genX(x) gfx12_##x # include "anv_genX.h" # undef genX -# define genX(x) gen125_##x +# define genX(x) gfx125_##x # include "anv_genX.h" # undef genX #endif diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index ea0abb128fb..7166409ed39 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -174,7 +174,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch, .bo = addrs[i].buffer, .offset = addrs[i].offset, }; - genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer, + genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, i, anv_addr, sizes[i]); } @@ -184,7 +184,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch, * really matter for blorp because we never call apply_pipe_flushes after * this point. */ - genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(cmd_buffer, SEQUENTIAL, + genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL, (1 << num_vbs) - 1); } @@ -257,7 +257,7 @@ genX(blorp_exec)(struct blorp_batch *batch, genX(flush_pipeline_select_3d)(cmd_buffer); - genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer); + genX(cmd_buffer_emit_gfx7_depth_flush)(cmd_buffer); /* BLORP doesn't do anything fancy with depth such as discards, so we want * the PMA fix off. Also, off is always the safe option. diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 431a0c76970..15a85d13af8 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -93,7 +93,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline * mode by putting the pipeline temporarily in 3D mode. */ - uint32_t gen12_wa_pipeline = cmd_buffer->state.current_pipeline; + uint32_t gfx12_wa_pipeline = cmd_buffer->state.current_pipeline; genX(flush_pipeline_select_3d)(cmd_buffer); #endif @@ -145,7 +145,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) sba.DynamicStateBufferSizeModifyEnable = true; sba.InstructionBuffersizeModifyEnable = true; # else - /* On gen7, we have upper bounds instead. According to the docs, + /* On gfx7, we have upper bounds instead. According to the docs, * setting an upper bound of zero means that no bounds checking is * performed so, in theory, we should be able to leave them zero. * However, border color is broken and the GPU bounds-checks anyway. @@ -189,8 +189,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) * * Put the pipeline back into its current mode. */ - if (gen12_wa_pipeline != UINT32_MAX) - genX(flush_pipeline_select)(cmd_buffer, gen12_wa_pipeline); + if (gfx12_wa_pipeline != UINT32_MAX) + genX(flush_pipeline_select)(cmd_buffer, gfx12_wa_pipeline); #endif /* After re-setting the surface state base address, we have to do some @@ -399,7 +399,7 @@ anv_can_hiz_clear_ds_view(struct anv_device *device, float depth_clear_value, VkRect2D render_area) { - /* We don't do any HiZ or depth fast-clears on gen7 yet */ + /* We don't do any HiZ or depth fast-clears on gfx7 yet */ if (GFX_VER == 7) return false; @@ -432,9 +432,9 @@ anv_can_hiz_clear_ds_view(struct anv_device *device, if (depth_clear_value != ANV_HZ_FC_VAL) return false; - /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared + /* Only gfx9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared * portion of a HiZ buffer. Testing has revealed that Gen8 only supports - * returning 0.0f. Gens prior to gen8 do not support this feature at all. + * returning 0.0f. Gens prior to gfx8 do not support this feature at all. */ if (GFX_VER == 8 && anv_can_sample_with_hiz(&device->info, iview->image)) return false; @@ -637,7 +637,7 @@ transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer, uint32_t plane = anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_STENCIL_BIT); - /* On gen7, we have to store a texturable version of the stencil buffer in + /* On gfx7, we have to store a texturable version of the stencil buffer in * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and * forth at strategic points. Stencil writes are only allowed in following * layouts: @@ -869,7 +869,7 @@ anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer, if (level > 0 || array_layer > 0) return; - /* On gen8, we don't have a concept of default clear colors because we + /* On gfx8, we don't have a concept of default clear colors because we * can't sample from CCS surfaces. It's enough to just load the fast clear * state into the predicate register. */ @@ -1042,7 +1042,7 @@ genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer, unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size; #if GFX_VER == 7 - /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM + /* On gfx7, the combination of commands used here(MI_LOAD_REGISTER_MEM * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is * in-flight when they are issued even if the memory touched is not * currently active for rendering. The weird bit is that it is not the @@ -1612,9 +1612,9 @@ genX(BeginCommandBuffer)( * blorp at least once per primary command buffer so it shouldn't be * wasted. * - * There is also a workaround on gen8 which requires us to invalidate the + * There is also a workaround on gfx8 which requires us to invalidate the * VF cache occasionally. It's easier if we can assume we start with a - * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).) + * fresh cache (See also genX(cmd_buffer_set_binding_for_gfx8_vb_flush).) */ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT; @@ -2197,7 +2197,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to * a 1." * - * This appears to hang Broadwell, so we restrict it to just gen9. + * This appears to hang Broadwell, so we restrict it to just gfx9. */ if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe); @@ -3317,7 +3317,7 @@ cmd_buffer_emit_clip(struct anv_cmd_buffer *cmd_buffer) GENX(3DSTATE_CLIP_pack)(NULL, dwords, &clip); anv_batch_emit_merge(&cmd_buffer->batch, dwords, - pipeline->gen7.clip); + pipeline->gfx7.clip); } void @@ -3407,7 +3407,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) } #if GFX_VER >= 8 && GFX_VER <= 9 - genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer, vb, + genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, vb, state.BufferStartingAddress, state.BufferSize); #endif @@ -3455,7 +3455,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) * we trust in SurfaceEndAddress = SurfaceBaseAddress = 0 (the * default for an empty SO_BUFFER packet) to disable them. */ - sob.SurfacePitch = pipeline->gen7.xfb_bo_pitch[idx]; + sob.SurfacePitch = pipeline->gfx7.xfb_bo_pitch[idx]; sob.SurfaceEndAddress = anv_address_add(xfb->buffer->address, xfb->offset + xfb->size); #endif @@ -3537,17 +3537,17 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) cmd_buffer_emit_clip(cmd_buffer); if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT) - gen8_cmd_buffer_emit_viewport(cmd_buffer); + gfx8_cmd_buffer_emit_viewport(cmd_buffer); if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | ANV_CMD_DIRTY_PIPELINE)) { - gen8_cmd_buffer_emit_depth_viewport(cmd_buffer, + gfx8_cmd_buffer_emit_depth_viewport(cmd_buffer, pipeline->depth_clamp_enable); } if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR | ANV_CMD_DIRTY_RENDER_TARGETS)) - gen7_cmd_buffer_emit_scissor(cmd_buffer); + gfx7_cmd_buffer_emit_scissor(cmd_buffer); genX(cmd_buffer_flush_dynamic_state)(cmd_buffer); } @@ -3577,7 +3577,7 @@ emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer, #endif }); - genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer, + genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, index, addr, size); } @@ -3627,7 +3627,7 @@ emit_draw_index(struct anv_cmd_buffer *cmd_buffer, uint32_t draw_index) } static void -update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer *cmd_buffer, +update_dirty_vbs_for_gfx8_vb_flush(struct anv_cmd_buffer *cmd_buffer, uint32_t access_type) { struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline; @@ -3640,7 +3640,7 @@ update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer *cmd_buffer, if (vs_prog_data->uses_drawid) vb_used |= 1ull << ANV_DRAWID_VB_INDEX; - genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(cmd_buffer, + genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, access_type == RANDOM, vb_used); } @@ -3700,7 +3700,7 @@ void genX(CmdDraw)( prim.BaseVertexLocation = 0; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); } void genX(CmdDrawIndexed)( @@ -3760,7 +3760,7 @@ void genX(CmdDrawIndexed)( prim.BaseVertexLocation = vertexOffset; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, RANDOM); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, RANDOM); } /* Auto-Draw / Indirect Registers */ @@ -3837,7 +3837,7 @@ void genX(CmdDrawIndirectByteCountEXT)( prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); #endif /* GFX_VERx10 >= 75 */ } @@ -3922,7 +3922,7 @@ void genX(CmdDrawIndirect)( prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); offset += stride; } @@ -3972,7 +3972,7 @@ void genX(CmdDrawIndexedIndirect)( prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, RANDOM); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, RANDOM); offset += stride; } @@ -4125,7 +4125,7 @@ void genX(CmdDrawIndirectCount)( prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, SEQUENTIAL); offset += stride; } @@ -4197,7 +4197,7 @@ void genX(CmdDrawIndexedIndirectCount)( prim.PrimitiveTopologyType = cmd_buffer->state.gfx.primitive_topology; } - update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, RANDOM); + update_dirty_vbs_for_gfx8_vb_flush(cmd_buffer, RANDOM); offset += stride; } @@ -4822,7 +4822,7 @@ genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer) } void -genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer) +genX(cmd_buffer_emit_gfx7_depth_flush)(struct anv_cmd_buffer *cmd_buffer) { if (GFX_VER >= 8) return; @@ -4865,7 +4865,7 @@ genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer) * bindings and flushing if the cache ever ends up with a range in the cache * that would exceed 4 GiB. This is implemented in three parts: * - * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called + * 1. genX(cmd_buffer_set_binding_for_gfx8_vb_flush)() which must be called * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the * tracking code of the new binding. If this new binding would cause * the cache to have a too-large range on the next draw call, a pipeline @@ -4874,14 +4874,14 @@ genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer) * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to * empty whenever we emit a VF invalidate. * - * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called + * 3. genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)() must be called * after every 3DPRIMITIVE and copies the bound range into the dirty * range for each used buffer. This has to be a separate step because * we don't always re-bind all buffers and so 1. can't know which * buffers are actually bound. */ void -genX(cmd_buffer_set_binding_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, +genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, int vb_index, struct anv_address vb_address, uint32_t vb_size) @@ -4930,7 +4930,7 @@ genX(cmd_buffer_set_binding_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_buffer } void -genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, +genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, uint32_t access_type, uint64_t vb_used) { @@ -5066,7 +5066,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) /* FIXME: Width and Height are wrong */ - genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer); + genX(cmd_buffer_emit_gfx7_depth_flush)(cmd_buffer); uint32_t *dw = anv_batch_emit_dwords(&cmd_buffer->batch, device->isl_dev.ds.size / 4); @@ -5208,7 +5208,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, * different views. If the client asks for instancing, we need to use the * Instance Data Step Rate to ensure that we repeat the client's * per-instance data once for each view. Since this bit is in - * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top + * VERTEX_BUFFER_STATE on gfx7, we need to dirty vertex buffers at the top * of each subpass. */ if (GFX_VER == 7) @@ -5874,7 +5874,7 @@ cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer) } #if GFX_VER == 7 - /* On gen7, we have to store a texturable version of the stencil buffer in + /* On gfx7, we have to store a texturable version of the stencil buffer in * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and * forth at strategic points. Stencil writes are only allowed in following * layouts: @@ -6221,7 +6221,7 @@ void genX(CmdWaitEvents)( } } #else - anv_finishme("Implement events on gen7"); + anv_finishme("Implement events on gfx7"); #endif genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask, diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index eea05a21d42..3a48fd94327 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -78,7 +78,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, genX(cmd_buffer_config_l3)(cmd_buffer, cfg); } - genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer, 32, src, size); + genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size); genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); genX(flush_pipeline_select_3d)(cmd_buffer); @@ -242,7 +242,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, prim.BaseVertexLocation = 0; } - genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(cmd_buffer, SEQUENTIAL, + genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL, 1ull << 32); cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE; diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 24b09a8df1c..8b36f26469b 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -528,7 +528,7 @@ anv_raster_polygon_mode(struct anv_graphics_pipeline *pipeline, #if GFX_VER <= 7 static uint32_t -gen7_ms_rast_mode(struct anv_graphics_pipeline *pipeline, +gfx7_ms_rast_mode(struct anv_graphics_pipeline *pipeline, const VkPipelineInputAssemblyStateCreateInfo *ia_info, const VkPipelineRasterizationStateCreateInfo *rs_info, const VkPipelineMultisampleStateCreateInfo *ms_info) @@ -647,9 +647,9 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, */ #if GFX_VER >= 8 if (raster_mode == VK_POLYGON_MODE_LINE) { - /* Unfortunately, configuring our line rasterization hardware on gen8 + /* Unfortunately, configuring our line rasterization hardware on gfx8 * and later is rather painful. Instead of giving us bits to tell the - * hardware what line mode to use like we had on gen7, we now have an + * hardware what line mode to use like we had on gfx7, we now have an * arcane combination of API Mode and MSAA enable bits which do things * in a table which are expected to magically put the hardware into the * right mode for your API. Sadly, Vulkan isn't any of the APIs the @@ -686,7 +686,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, raster.ForceMultisampling = false; #else raster.MultisampleRasterizationMode = - gen7_ms_rast_mode(pipeline, ia_info, rs_info, ms_info); + gfx7_ms_rast_mode(pipeline, ia_info, rs_info, ms_info); #endif if (raster_mode == VK_POLYGON_MODE_LINE && @@ -742,11 +742,11 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, #endif #if GFX_VER >= 8 - GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf); - GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster); + GENX(3DSTATE_SF_pack)(NULL, pipeline->gfx8.sf, &sf); + GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gfx8.raster, &raster); #else # undef raster - GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf); + GENX(3DSTATE_SF_pack)(NULL, &pipeline->gfx7.sf, &sf); #endif } @@ -1029,11 +1029,11 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline, const struct anv_subpass *subpass) { #if GFX_VER == 7 -# define depth_stencil_dw pipeline->gen7.depth_stencil_state +# define depth_stencil_dw pipeline->gfx7.depth_stencil_state #elif GFX_VER == 8 -# define depth_stencil_dw pipeline->gen8.wm_depth_stencil +# define depth_stencil_dw pipeline->gfx8.wm_depth_stencil #else -# define depth_stencil_dw pipeline->gen9.wm_depth_stencil +# define depth_stencil_dw pipeline->gfx9.wm_depth_stencil #endif if (pCreateInfo == NULL) { @@ -1388,7 +1388,7 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline, BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) != 0 : 0; #endif - GENX(3DSTATE_CLIP_pack)(NULL, pipeline->gen7.clip, &clip); + GENX(3DSTATE_CLIP_pack)(NULL, pipeline->gfx7.clip, &clip); } static void @@ -1425,10 +1425,10 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, so.Buffer2SurfacePitch = xfb_info->buffers[2].stride; so.Buffer3SurfacePitch = xfb_info->buffers[3].stride; #else - pipeline->gen7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride; - pipeline->gen7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride; - pipeline->gen7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride; - pipeline->gen7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride; + pipeline->gfx7.xfb_bo_pitch[0] = xfb_info->buffers[0].stride; + pipeline->gfx7.xfb_bo_pitch[1] = xfb_info->buffers[1].stride; + pipeline->gfx7.xfb_bo_pitch[2] = xfb_info->buffers[2].stride; + pipeline->gfx7.xfb_bo_pitch[3] = xfb_info->buffers[3].stride; /* On Gen7, the SO buffer enables live in 3DSTATE_STREAMOUT which * is a bit inconvenient because we don't know what buffers will @@ -1637,7 +1637,7 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline) * which the VUE handle reference count would overflow resulting in * internal reference counting bugs. My (Jason's) best guess is that * this bug cropped back up on SKL GT4 when we suddenly had more - * threads in play than any previous gen9 hardware. + * threads in play than any previous gfx9 hardware. * * What we do know for sure is that setting this bit when * tessellation shaders are in use fixes a GPU hang in Batman: Arkham @@ -1982,7 +1982,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline, struct anv_subpass *subp wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE; } wm.MultisampleRasterizationMode = - gen7_ms_rast_mode(pipeline, ia, raster, multisample); + gfx7_ms_rast_mode(pipeline, ia, raster, multisample); #endif wm.LineStippleEnable = line && line->stippledLineEnable; @@ -2002,7 +2002,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) { anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) { #if GFX_VER == 7 - /* Even if no fragments are ever dispatched, gen7 hardware hangs if + /* Even if no fragments are ever dispatched, gfx7 hardware hangs if * we don't at least set the maximum number of threads. */ ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1; @@ -2186,7 +2186,7 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline, const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); /* This computes the KillPixel portion of the computation for whether or - * not we want to enable the PMA fix on gen8 or gen9. It's given by this + * not we want to enable the PMA fix on gfx8 or gfx9. It's given by this * chunk of the giant formula: * * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels || @@ -2339,7 +2339,7 @@ genX(graphics_pipeline_create)( * Stall" bit set. */ if (!device->info.is_haswell && !device->info.is_baytrail) - gen7_emit_vs_workaround_flush(brw); + gfx7_emit_vs_workaround_flush(brw); #endif emit_3dstate_vs(pipeline); @@ -2385,7 +2385,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline, anv_batch_emit(&pipeline->base.batch, GENX(CFE_STATE), cfe) { cfe.MaximumNumberofThreads = devinfo->max_cs_threads * subslices - 1; - /* TODO: Enable gen12-hp scratch support*/ + /* TODO: Enable gfx12-hp scratch support*/ assert(get_scratch_space(cs_bin) == 0); } } @@ -2484,7 +2484,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline, * preemption. * * We still have issues with mid-thread preemption (it was already - * disabled by the kernel on gen11, due to missing workarounds). It's + * disabled by the kernel on gfx11, due to missing workarounds). It's * possible that we are just missing some workarounds, and could enable * it later, but for now let's disable it to fix a GPU in compute in Car * Chase (and possibly more). diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index cd9f6944462..d8c60ef4bdd 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -711,7 +711,7 @@ VkResult genX(CreateSampler)( (VkSamplerCustomBorderColorCreateInfoEXT *) ext; if (sampler->custom_border_color.map == NULL) break; - struct gen8_border_color *cbc = sampler->custom_border_color.map; + struct gfx8_border_color *cbc = sampler->custom_border_color.map; if (custom_border_color->format == VK_FORMAT_B4G4R4A4_UNORM_PACK16) { /* B4G4R4A4_UNORM_PACK16 is treated as R4G4B4A4_UNORM_PACK16 with * a swizzle, but this does not carry over to the sampler for diff --git a/src/intel/vulkan/gfx7_cmd_buffer.c b/src/intel/vulkan/gfx7_cmd_buffer.c index c13f306c360..06a4965014c 100644 --- a/src/intel/vulkan/gfx7_cmd_buffer.c +++ b/src/intel/vulkan/gfx7_cmd_buffer.c @@ -46,7 +46,7 @@ clamp_int64(int64_t x, int64_t min, int64_t max) } void -gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) +gfx7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) { struct anv_framebuffer *fb = cmd_buffer->state.framebuffer; uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count; @@ -165,9 +165,9 @@ void genX(CmdBindIndexBuffer)( cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER; if (GFX_VERx10 == 75) cmd_buffer->state.restart_index = restart_index_for_type(indexType); - cmd_buffer->state.gfx.gen7.index_buffer = buffer; - cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type(indexType); - cmd_buffer->state.gfx.gen7.index_offset = offset; + cmd_buffer->state.gfx.gfx7.index_buffer = buffer; + cmd_buffer->state.gfx.gfx7.index_type = vk_to_gen_index_type(indexType); + cmd_buffer->state.gfx.gfx7.index_offset = offset; } static uint32_t @@ -225,7 +225,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) }; GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); - anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf); + anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf); } if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | @@ -297,7 +297,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) struct anv_state ds_state = anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw, - pipeline->gen7.depth_stencil_state, + pipeline->gfx7.depth_stencil_state, GENX(DEPTH_STENCIL_STATE_length), 64); anv_batch_emit(&cmd_buffer->batch, @@ -306,11 +306,11 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) } } - if (cmd_buffer->state.gfx.gen7.index_buffer && + if (cmd_buffer->state.gfx.gfx7.index_buffer && cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | ANV_CMD_DIRTY_INDEX_BUFFER)) { - struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer; - uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset; + struct anv_buffer *buffer = cmd_buffer->state.gfx.gfx7.index_buffer; + uint32_t offset = cmd_buffer->state.gfx.gfx7.index_offset; #if GFX_VERx10 == 75 anv_batch_emit(&cmd_buffer->batch, GFX75_3DSTATE_VF, vf) { @@ -323,7 +323,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) #if GFX_VERx10 != 75 ib.CutIndexEnable = pipeline->primitive_restart; #endif - ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type; + ib.IndexFormat = cmd_buffer->state.gfx.gfx7.index_type; ib.MOCS = anv_mocs(cmd_buffer->device, buffer->address.bo, ISL_SURF_USAGE_INDEX_BUFFER_BIT); @@ -359,5 +359,5 @@ void genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) { - /* The NP PMA fix doesn't exist on gen7 */ + /* The NP PMA fix doesn't exist on gfx7 */ } diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c index a1ade7d2bde..cd5eb1a8ddc 100644 --- a/src/intel/vulkan/gfx8_cmd_buffer.c +++ b/src/intel/vulkan/gfx8_cmd_buffer.c @@ -35,7 +35,7 @@ #if GFX_VER == 8 void -gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) +gfx8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) { struct anv_framebuffer *fb = cmd_buffer->state.framebuffer; uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count; @@ -47,8 +47,8 @@ gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) for (uint32_t i = 0; i < count; i++) { const VkViewport *vp = &viewports[i]; - /* The gen7 state struct has just the matrix and guardband fields, the - * gen8 struct adds the min/max viewport fields. */ + /* The gfx7 state struct has just the matrix and guardband fields, the + * gfx8 struct adds the min/max viewport fields. */ struct GENX(SF_CLIP_VIEWPORT) sfv = { .ViewportMatrixElementm00 = vp->width / 2, .ViewportMatrixElementm11 = vp->height / 2, @@ -92,7 +92,7 @@ gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) } void -gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer, +gfx8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer, bool depth_clamp_enable) { uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count; @@ -436,7 +436,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) sf.LineWidth = d->line_width, #endif GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); - anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf); + anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx8.sf); } if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | @@ -454,12 +454,12 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) }; GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster); anv_batch_emit_merge(&cmd_buffer->batch, raster_dw, - pipeline->gen8.raster); + pipeline->gfx8.raster); } - /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to - * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split - * across different state packets for gen8 and gen9. We handle that by + /* Stencil reference values moved from COLOR_CALC_STATE in gfx8 to + * 3DSTATE_WM_DEPTH_STENCIL in gfx9. That means the dirty bits gets split + * across different state packets for gfx8 and gfx9. We handle that by * using a big old #if switch here. */ #if GFX_VER == 8 @@ -526,7 +526,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) &wm_depth_stencil); anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw, - pipeline->gen8.wm_depth_stencil); + pipeline->gfx8.wm_depth_stencil); genX(cmd_buffer_enable_pma_fix)(cmd_buffer, want_depth_pma_fix(cmd_buffer)); @@ -595,7 +595,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil); anv_batch_emit_merge(&cmd_buffer->batch, dwords, - pipeline->gen9.wm_depth_stencil); + pipeline->gfx9.wm_depth_stencil); genX(cmd_buffer_enable_pma_fix)(cmd_buffer, want_stencil_pma_fix(cmd_buffer)); diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build index 7328275264d..7171532382c 100644 --- a/src/intel/vulkan/meson.build +++ b/src/intel/vulkan/meson.build @@ -25,10 +25,10 @@ anv_entrypoints = custom_target( command : [ prog_python, '@INPUT0@', '--xml', '@INPUT1@', '--proto', '--weak', '--out-h', '@OUTPUT0@', '--out-c', '@OUTPUT1@', '--prefix', 'anv', - '--device-prefix', 'gen7', '--device-prefix', 'gen75', - '--device-prefix', 'gen8', '--device-prefix', 'gen9', - '--device-prefix', 'gen11', '--device-prefix', 'gen12', - '--device-prefix', 'gen125', + '--device-prefix', 'gfx7', '--device-prefix', 'gfx75', + '--device-prefix', 'gfx8', '--device-prefix', 'gfx9', + '--device-prefix', 'gfx11', '--device-prefix', 'gfx12', + '--device-prefix', 'gfx125', ], ) diff --git a/src/mesa/drivers/dri/i965/brw_batch.c b/src/mesa/drivers/dri/i965/brw_batch.c index 147afdd3b70..5868f9abae3 100644 --- a/src/mesa/drivers/dri/i965/brw_batch.c +++ b/src/mesa/drivers/dri/i965/brw_batch.c @@ -167,7 +167,7 @@ brw_batch_init(struct brw_context *brw) batch->use_batch_first = screen->kernel_features & KERNEL_ALLOWS_EXEC_BATCH_FIRST; - /* PIPE_CONTROL needs a w/a but only on gen6 */ + /* PIPE_CONTROL needs a w/a but only on gfx6 */ batch->valid_reloc_flags = EXEC_OBJECT_WRITE; if (devinfo->ver == 6) batch->valid_reloc_flags |= EXEC_OBJECT_NEEDS_GTT; @@ -619,7 +619,7 @@ brw_finish_batch(struct brw_context *brw) */ if (devinfo->ver >= 7 && !(brw->screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION)) - gen7_restore_default_l3_config(brw); + gfx7_restore_default_l3_config(brw); if (devinfo->is_haswell) { /* From the Haswell PRM, Volume 2b, Command Reference: Instructions, @@ -644,7 +644,7 @@ brw_finish_batch(struct brw_context *brw) /* Do not restore push constant packets during context restore. */ if (devinfo->ver >= 7) - gen7_emit_isp_disable(brw); + gfx7_emit_isp_disable(brw); /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2 * requires our batch size to be QWord aligned, so we pad it out if diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c index 9bd61b23f51..fa76ef0c1cb 100644 --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c @@ -246,7 +246,7 @@ const struct brw_tracked_state brw_gs_binding_table = { * which points at the batchbuffer containing the streamed batch state. */ static void -gen4_upload_binding_table_pointers(struct brw_context *brw) +gfx4_upload_binding_table_pointers(struct brw_context *brw) { BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); @@ -266,7 +266,7 @@ const struct brw_tracked_state brw_binding_table_pointers = { BRW_NEW_BINDING_TABLE_POINTERS | BRW_NEW_STATE_BASE_ADDRESS, }, - .emit = gen4_upload_binding_table_pointers, + .emit = gfx4_upload_binding_table_pointers, }; /** @@ -276,7 +276,7 @@ const struct brw_tracked_state brw_binding_table_pointers = { * which points at the batchbuffer containing the streamed batch state. */ static void -gen6_upload_binding_table_pointers(struct brw_context *brw) +gfx6_upload_binding_table_pointers(struct brw_context *brw) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | @@ -293,7 +293,7 @@ gen6_upload_binding_table_pointers(struct brw_context *brw) ADVANCE_BATCH(); } -const struct brw_tracked_state gen6_binding_table_pointers = { +const struct brw_tracked_state gfx6_binding_table_pointers = { .dirty = { .mesa = 0, .brw = BRW_NEW_BATCH | @@ -301,7 +301,7 @@ const struct brw_tracked_state gen6_binding_table_pointers = { BRW_NEW_BINDING_TABLE_POINTERS | BRW_NEW_STATE_BASE_ADDRESS, }, - .emit = gen6_upload_binding_table_pointers, + .emit = gfx6_upload_binding_table_pointers, }; /** @} */ diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index fc4d9e67fc1..6c0ff012cd5 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -79,32 +79,32 @@ brw_blorp_init(struct brw_context *brw) switch (devinfo->ver) { case 4: if (devinfo->is_g4x) { - brw->blorp.exec = gen45_blorp_exec; + brw->blorp.exec = gfx45_blorp_exec; } else { - brw->blorp.exec = gen4_blorp_exec; + brw->blorp.exec = gfx4_blorp_exec; } break; case 5: - brw->blorp.exec = gen5_blorp_exec; + brw->blorp.exec = gfx5_blorp_exec; break; case 6: - brw->blorp.exec = gen6_blorp_exec; + brw->blorp.exec = gfx6_blorp_exec; break; case 7: if (devinfo->is_haswell) { - brw->blorp.exec = gen75_blorp_exec; + brw->blorp.exec = gfx75_blorp_exec; } else { - brw->blorp.exec = gen7_blorp_exec; + brw->blorp.exec = gfx7_blorp_exec; } break; case 8: - brw->blorp.exec = gen8_blorp_exec; + brw->blorp.exec = gfx8_blorp_exec; break; case 9: - brw->blorp.exec = gen9_blorp_exec; + brw->blorp.exec = gfx9_blorp_exec; break; case 11: - brw->blorp.exec = gen11_blorp_exec; + brw->blorp.exec = gfx11_blorp_exec; break; default: @@ -183,7 +183,7 @@ blorp_surf_for_miptree(struct brw_context *brw, (surf->aux_addr.buffer == NULL)); if (!is_render_target && brw->screen->devinfo.ver == 9) - gen9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage); + gfx9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage); /* ISL wants real levels, not offset ones. */ *level -= mt->first_level; @@ -657,7 +657,7 @@ try_blorp_blit(struct brw_context *brw, break; case GL_STENCIL_BUFFER_BIT: /* Blorp doesn't support combined depth stencil which is all we have - * prior to gen6. + * prior to gfx6. */ if (devinfo->ver < 6) return false; diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index de214e6e1e5..35822ab7f56 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -111,23 +111,23 @@ brw_hiz_exec(struct brw_context *brw, struct brw_mipmap_tree *mt, unsigned int level, unsigned int start_layer, unsigned int num_layers, enum isl_aux_op op); -void gen4_blorp_exec(struct blorp_batch *batch, +void gfx4_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen45_blorp_exec(struct blorp_batch *batch, +void gfx45_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen5_blorp_exec(struct blorp_batch *batch, +void gfx5_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen6_blorp_exec(struct blorp_batch *batch, +void gfx6_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen7_blorp_exec(struct blorp_batch *batch, +void gfx7_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen75_blorp_exec(struct blorp_batch *batch, +void gfx75_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen8_blorp_exec(struct blorp_batch *batch, +void gfx8_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen9_blorp_exec(struct blorp_batch *batch, +void gfx9_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); -void gen11_blorp_exec(struct blorp_batch *batch, +void gfx11_blorp_exec(struct blorp_batch *batch, const struct blorp_params *params); #ifdef __cplusplus diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 8821cd93d0b..a10ea17cea4 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -85,7 +85,7 @@ noop_scissor(struct gl_framebuffer *fb) } /** - * Implements fast depth clears on gen6+. + * Implements fast depth clears on gfx6+. * * Fast clears basically work by setting a flag in each of the subspans * represented in the HiZ buffer that says "When you need the depth values for diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index a4ee4c655ac..d4d33aa8f31 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -364,9 +364,9 @@ brw_init_driver_functions(struct brw_context *brw, if (devinfo->ver >= 8 || devinfo->is_haswell) hsw_init_queryobj_functions(functions); else if (devinfo->ver >= 6) - gen6_init_queryobj_functions(functions); + gfx6_init_queryobj_functions(functions); else - gen4_init_queryobj_functions(functions); + gfx4_init_queryobj_functions(functions); brw_init_compute_functions(functions); brw_init_conditional_render_functions(functions); @@ -382,10 +382,10 @@ brw_init_driver_functions(struct brw_context *brw, functions->PauseTransformFeedback = hsw_pause_transform_feedback; functions->ResumeTransformFeedback = hsw_resume_transform_feedback; } else if (devinfo->ver >= 7) { - functions->BeginTransformFeedback = gen7_begin_transform_feedback; - functions->EndTransformFeedback = gen7_end_transform_feedback; - functions->PauseTransformFeedback = gen7_pause_transform_feedback; - functions->ResumeTransformFeedback = gen7_resume_transform_feedback; + functions->BeginTransformFeedback = gfx7_begin_transform_feedback; + functions->EndTransformFeedback = gfx7_end_transform_feedback; + functions->PauseTransformFeedback = gfx7_pause_transform_feedback; + functions->ResumeTransformFeedback = gfx7_resume_transform_feedback; functions->GetTransformFeedbackVertexCount = brw_get_transform_feedback_vertex_count; } else { @@ -398,7 +398,7 @@ brw_init_driver_functions(struct brw_context *brw, } if (devinfo->ver >= 6) - functions->GetSamplePosition = gen6_get_sample_position; + functions->GetSamplePosition = gfx6_get_sample_position; /* GL_ARB_get_program_binary */ brw_program_binary_init(brw->screen->deviceID); @@ -420,8 +420,8 @@ brw_initialize_spirv_supported_capabilities(struct brw_context *brw) const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; - /* The following SPIR-V capabilities are only supported on gen7+. In theory - * you should enable the extension only on gen7+, but just in case let's + /* The following SPIR-V capabilities are only supported on gfx7+. In theory + * you should enable the extension only on gfx7+, but just in case let's * assert it. */ assert(devinfo->ver >= 7); @@ -703,7 +703,7 @@ brw_initialize_context_constants(struct brw_context *brw) */ ctx->Const.UniformBooleanTrue = ~0; - /* From the gen4 PRM, volume 4 page 127: + /* From the gfx4 PRM, volume 4 page 127: * * "For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies * the base address of the first element of the surface, computed in @@ -860,7 +860,7 @@ brw_process_driconf_options(struct brw_context *brw) if (INTEL_DEBUG & DEBUG_NO_HIZ) { brw->has_hiz = false; - /* On gen6, you can only do separate stencil with HIZ. */ + /* On gfx6, you can only do separate stencil with HIZ. */ if (devinfo->ver == 6) brw->has_separate_stencil = false; } @@ -1020,7 +1020,7 @@ brw_create_context(gl_api api, /* Initialize the software rasterizer and helper modules. * - * As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for + * As of GL 3.1 core, the gfx4+ driver doesn't need the swrast context for * software fallbacks (which we have to support on legacy GL to do weird * glDrawPixels(), glBitmap(), and other functions). */ diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 4960cede369..2f8b750054b 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -171,7 +171,7 @@ enum brw_cache_id { BRW_MAX_CACHE }; -enum gen9_astc5x5_wa_tex_type { +enum gfx9_astc5x5_wa_tex_type { GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0, GFX9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1, }; @@ -707,7 +707,7 @@ struct brw_context * * This asks the GPU to write a report of the current OA counter values * into @bo at the given offset and containing the given @report_id - * which we can cross-reference when parsing the report (gen7+ only). + * which we can cross-reference when parsing the report (gfx7+ only). */ void (*emit_mi_report_perf_count)(struct brw_context *brw, struct brw_bo *bo, @@ -725,7 +725,7 @@ struct brw_context uint32_t hw_ctx; /** - * BO for post-sync nonzero writes for gen6 workaround. + * BO for post-sync nonzero writes for gfx6 workaround. * * This buffer also contains a marker + description of the driver. This * buffer is added to all execbufs syscalls so that we can identify the @@ -1109,7 +1109,7 @@ struct brw_context struct brw_ff_gs_prog_data *prog_data; bool prog_active; - /** Offset in the program cache to the CLIP program pre-gen6 */ + /** Offset in the program cache to the CLIP program pre-gfx6 */ uint32_t prog_offset; uint32_t state_offset; @@ -1125,13 +1125,13 @@ struct brw_context struct { struct brw_clip_prog_data *prog_data; - /** Offset in the program cache to the CLIP program pre-gen6 */ + /** Offset in the program cache to the CLIP program pre-gfx6 */ uint32_t prog_offset; - /* Offset in the batch to the CLIP state on pre-gen6. */ + /* Offset in the batch to the CLIP state on pre-gfx6. */ uint32_t state_offset; - /* As of gen6, this is the offset in the batch to the CLIP VP, + /* As of gfx6, this is the offset in the batch to the CLIP VP, * instead of vp_bo. */ uint32_t vp_offset; @@ -1148,7 +1148,7 @@ struct brw_context struct { struct brw_sf_prog_data *prog_data; - /** Offset in the program cache to the CLIP program pre-gen6 */ + /** Offset in the program cache to the CLIP program pre-gfx6 */ uint32_t prog_offset; uint32_t state_offset; uint32_t vp_offset; @@ -1243,7 +1243,7 @@ struct brw_context */ enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS]; - enum gen9_astc5x5_wa_tex_type gen9_astc5x5_wa_tex_mask; + enum gfx9_astc5x5_wa_tex_type gfx9_astc5x5_wa_tex_mask; /** Last rendering scale argument provided to brw_emit_hashing_mode(). */ unsigned current_hash_scale; @@ -1273,7 +1273,7 @@ void brw_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); void brw_prepare_render(struct brw_context *brw); -void gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw, +void gfx9_apply_single_tex_astc5x5_wa(struct brw_context *brw, mesa_format format, enum isl_aux_usage aux_usage); @@ -1305,7 +1305,7 @@ void brw_init_object_purgeable_functions(struct dd_function_table *functions); * brw_queryobj.c */ void brw_init_common_queryobj_functions(struct dd_function_table *functions); -void gen4_init_queryobj_functions(struct dd_function_table *functions); +void gfx4_init_queryobj_functions(struct dd_function_table *functions); void brw_emit_query_begin(struct brw_context *brw); void brw_emit_query_end(struct brw_context *brw); void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q); @@ -1314,7 +1314,7 @@ uint64_t brw_raw_timestamp_delta(struct brw_context *brw, uint64_t time0, uint64_t time1); /** gfx6_queryobj.c */ -void gen6_init_queryobj_functions(struct dd_function_table *functions); +void gfx6_init_queryobj_functions(struct dd_function_table *functions); void brw_write_timestamp(struct brw_context *brw, struct brw_bo *bo, int idx); void brw_write_depth_count(struct brw_context *brw, struct brw_bo *bo, int idx); @@ -1472,16 +1472,16 @@ brw_get_transform_feedback_vertex_count(struct gl_context *ctx, /* gfx7_sol_state.c */ void -gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, +gfx7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, struct gl_transform_feedback_object *obj); void -gen7_end_transform_feedback(struct gl_context *ctx, +gfx7_end_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj); void -gen7_pause_transform_feedback(struct gl_context *ctx, +gfx7_pause_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj); void -gen7_resume_transform_feedback(struct gl_context *ctx, +gfx7_resume_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj); /* hsw_sol.c */ @@ -1521,28 +1521,28 @@ void brw_generate_mipmap(struct gl_context *ctx, GLenum target, struct gl_texture_object *tex_obj); void -gen6_get_sample_position(struct gl_context *ctx, +gfx6_get_sample_position(struct gl_context *ctx, struct gl_framebuffer *fb, GLuint index, GLfloat *result); /* gfx8_multisample_state.c */ -void gen8_emit_3dstate_sample_pattern(struct brw_context *brw); +void gfx8_emit_3dstate_sample_pattern(struct brw_context *brw); /* gfx7_l3_state.c */ void brw_emit_l3_state(struct brw_context *brw); /* gfx7_urb.c */ void -gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, +gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, unsigned hs_size, unsigned ds_size, unsigned gs_size, unsigned fs_size); void -gen6_upload_urb(struct brw_context *brw, unsigned vs_size, +gfx6_upload_urb(struct brw_context *brw, unsigned vs_size, bool gs_present, unsigned gs_size); void -gen7_upload_urb(struct brw_context *brw, unsigned vs_size, +gfx7_upload_urb(struct brw_context *brw, unsigned vs_size, bool gs_present, bool tess_present); /* brw_reset.c */ @@ -1622,13 +1622,13 @@ brw_emit_depthbuffer(struct brw_context *brw); uint32_t get_hw_prim_for_gl_prim(int mode); void -gen6_upload_push_constants(struct brw_context *brw, +gfx6_upload_push_constants(struct brw_context *brw, const struct gl_program *prog, const struct brw_stage_prog_data *prog_data, struct brw_stage_state *stage_state); bool -gen9_use_linear_1d_layout(const struct brw_context *brw, +gfx9_use_linear_1d_layout(const struct brw_context *brw, const struct brw_mipmap_tree *mt); /* brw_queryformat.c */ diff --git a/src/mesa/drivers/dri/i965/brw_copy_image.c b/src/mesa/drivers/dri/i965/brw_copy_image.c index 4ab14ca5005..c7c83720441 100644 --- a/src/mesa/drivers/dri/i965/brw_copy_image.c +++ b/src/mesa/drivers/dri/i965/brw_copy_image.c @@ -45,7 +45,7 @@ copy_miptrees(struct brw_context *brw, const struct gen_device_info *devinfo = &brw->screen->devinfo; if (devinfo->ver <= 5) { - /* On gen4-5, try BLT first. + /* On gfx4-5, try BLT first. * * Gen4-5 have a single ring for both 3D and BLT operations, so there's * no inter-ring synchronization issues like on Gen6+. It is apparently diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index b8164bda189..72cd73f0d59 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -31,11 +31,11 @@ /** @file brw_curbe.c * - * Push constant handling for gen4/5. + * Push constant handling for gfx4/5. * * Push constants are constant values (such as GLSL uniforms) that are * pre-loaded into a shader stage's register space at thread spawn time. On - * gen4 and gen5, we create a blob in memory containing all the push constants + * gfx4 and gfx5, we create a blob in memory containing all the push constants * for all the stages in order. At CMD_CONST_BUFFER time that blob is loaded * into URB space as a constant URB entry (CURBE) so that it can be accessed * quickly at thread setup time. Each individual fixed function unit's state @@ -45,8 +45,8 @@ * how many CURBEs can be loaded into the hardware at once before a pipeline * stall occurs at CMD_CONST_BUFFER time. * - * On gen6+, constant handling becomes a much simpler set of per-unit state. - * See gen6_upload_vec4_push_constants() in gfx6_vs_state.c for that code. + * On gfx6+, constant handling becomes a much simpler set of per-unit state. + * See gfx6_upload_vec4_push_constants() in gfx6_vs_state.c for that code. */ @@ -95,7 +95,7 @@ static void calculate_curbe_offsets( struct brw_context *brw ) total_regs = nr_fp_regs + nr_vp_regs + nr_clip_regs; /* The CURBE allocation size is limited to 32 512-bit units (128 EU - * registers, or 1024 floats). See CS_URB_STATE in the gen4 or gen5 + * registers, or 1024 floats). See CS_URB_STATE in the gfx4 or gfx5 * (volume 1, part 1) PRMs. * * Note that in brw_fs.cpp we're only loading up to 16 EU registers of @@ -295,7 +295,7 @@ brw_upload_constant_buffer(struct brw_context *brw) */ emit: - /* BRW_NEW_URB_FENCE: From the gen4 PRM, volume 1, section 3.9.8 + /* BRW_NEW_URB_FENCE: From the gfx4 PRM, volume 1, section 3.9.8 * (CONSTANT_BUFFER (CURBE Load)): * * "Modifying the CS URB allocation via URB_FENCE invalidates any diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 19c789209a5..de00267fa4e 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -777,7 +777,7 @@ enum brw_wrap_mode { # define GFX6_CLIP_MAX_VP_INDEX_MASK INTEL_MASK(3, 0) #define _3DSTATE_SF 0x7813 /* GFX6+ */ -/* DW1 (for gen6) */ +/* DW1 (for gfx6) */ # define GFX6_SF_NUM_OUTPUTS_SHIFT 22 # define GFX6_SF_SWIZZLE_ENABLE (1 << 21) # define GFX6_SF_POINT_SPRITE_UPPERLEFT (0 << 20) @@ -881,13 +881,13 @@ enum brw_wrap_mode { # define GFX7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 # define GFX7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 # define GFX8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5 -/* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */ +/* DW2-9: Attribute setup (same as DW8-15 of gfx6 _3DSTATE_SF) */ /* DW10: Point sprite texture coordinate enables */ /* DW11: Constant interpolation enables */ /* DW12: attr 0-7 wrap shortest enables */ /* DW13: attr 8-16 wrap shortest enables */ -/* DW4-5: Attribute active components (gen9) */ +/* DW4-5: Attribute active components (gfx9) */ #define GFX9_SBE_ACTIVE_COMPONENT_NONE 0 #define GFX9_SBE_ACTIVE_COMPONENT_XY 1 #define GFX9_SBE_ACTIVE_COMPONENT_XYZ 2 diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index f3c7650944f..c6e144490f1 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -113,7 +113,7 @@ brw_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) } static void -gen6_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) +gfx6_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) { const struct gl_context *ctx = &brw->ctx; uint32_t hw_prim; @@ -430,24 +430,24 @@ brw_disable_rb_aux_buffer(struct brw_context *brw, * ignore the possibility and hope for the best. */ static void -gen9_apply_astc5x5_wa_flush(struct brw_context *brw, - enum gen9_astc5x5_wa_tex_type curr_mask) +gfx9_apply_astc5x5_wa_flush(struct brw_context *brw, + enum gfx9_astc5x5_wa_tex_type curr_mask) { assert(brw->screen->devinfo.ver == 9); - if (((brw->gen9_astc5x5_wa_tex_mask & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) && + if (((brw->gfx9_astc5x5_wa_tex_mask & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) && (curr_mask & GFX9_ASTC5X5_WA_TEX_TYPE_AUX)) || - ((brw->gen9_astc5x5_wa_tex_mask & GFX9_ASTC5X5_WA_TEX_TYPE_AUX) && + ((brw->gfx9_astc5x5_wa_tex_mask & GFX9_ASTC5X5_WA_TEX_TYPE_AUX) && (curr_mask & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5))) { brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); } - brw->gen9_astc5x5_wa_tex_mask = curr_mask; + brw->gfx9_astc5x5_wa_tex_mask = curr_mask; } -static enum gen9_astc5x5_wa_tex_type -gen9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage) +static enum gfx9_astc5x5_wa_tex_type +gfx9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage) { if (aux_usage != ISL_AUX_USAGE_NONE && aux_usage != ISL_AUX_USAGE_MCS) @@ -460,15 +460,15 @@ gen9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage) return 0; } -/* Helper for the gen9 ASTC 5x5 workaround. This version exists for BLORP's +/* Helper for the gfx9 ASTC 5x5 workaround. This version exists for BLORP's * use-cases where only a single texture is bound. */ void -gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw, +gfx9_apply_single_tex_astc5x5_wa(struct brw_context *brw, mesa_format format, enum isl_aux_usage aux_usage) { - gen9_apply_astc5x5_wa_flush(brw, gen9_astc5x5_wa_bits(format, aux_usage)); + gfx9_apply_astc5x5_wa_flush(brw, gfx9_astc5x5_wa_bits(format, aux_usage)); } static void @@ -510,7 +510,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering, int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit; - enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits = 0; + enum gfx9_astc5x5_wa_tex_type astc5x5_wa_bits = 0; if (brw->screen->devinfo.ver == 9) { /* In order to properly implement the ASTC 5x5 workaround for an * arbitrary draw or dispatch call, we have to walk the entire list of @@ -525,10 +525,10 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering, if (!tex_obj || !tex_obj->mt) continue; - astc5x5_wa_bits |= gen9_astc5x5_wa_bits(tex_obj->_Format, + astc5x5_wa_bits |= gfx9_astc5x5_wa_bits(tex_obj->_Format, tex_obj->mt->aux_usage); } - gen9_apply_astc5x5_wa_flush(brw, astc5x5_wa_bits); + gfx9_apply_astc5x5_wa_flush(brw, astc5x5_wa_bits); } /* Resolve depth buffer and render cache of each enabled texture. */ @@ -656,7 +656,7 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw, brw_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format, irb->mt_level, 1, irb->mt_layer, irb->layer_count, - brw->gen9_astc5x5_wa_tex_mask); + brw->gfx9_astc5x5_wa_tex_mask); } } } @@ -925,13 +925,13 @@ brw_finish_drawing(struct gl_context *ctx) * - WA#0798 */ static void -gen9_emit_preempt_wa(struct brw_context *brw, +gfx9_emit_preempt_wa(struct brw_context *brw, const struct _mesa_prim *prim, GLuint num_instances) { bool object_preemption = true; ASSERTED const struct gen_device_info *devinfo = &brw->screen->devinfo; - /* Only apply these workarounds for gen9 */ + /* Only apply these workarounds for gfx9 */ assert(devinfo->ver == 9); /* WaDisableMidObjectPreemptionForGSLineStripAdj @@ -1081,7 +1081,7 @@ brw_draw_single_prim(struct gl_context *ctx, if (devinfo->ver < 6) brw_set_prim(brw, prim); else - gen6_set_prim(brw, prim); + gfx6_set_prim(brw, prim); retry: @@ -1096,7 +1096,7 @@ retry: } if (devinfo->ver == 9) - gen9_emit_preempt_wa(brw, prim, num_instances); + gfx9_emit_preempt_wa(brw, prim, num_instances); brw_emit_prim(brw, prim, brw->primitive, is_indexed, num_instances, base_instance, xfb_obj, stream, is_indirect, diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index e2096dce5aa..f80ae3e383c 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -232,7 +232,7 @@ double_types(int size, GLboolean doubles) * Also included on BDW PRM, Volume 7, page 470, table "Source Element * Formats Supported in VF Unit" * - * Previous PRMs don't include those references, so for gen7 we can't use + * Previous PRMs don't include those references, so for gfx7 we can't use * PASSTHRU formats directly. But in any case, we prefer to return passthru * even in that case, because that reflects what we want to achieve, even * if we would need to workaround on gen < 8. @@ -454,7 +454,7 @@ brw_prepare_vertices(struct brw_context *brw) /* _NEW_POLYGON * - * On gen6+, edge flags don't end up in the VUE (either in or out of the + * On gfx6+, edge flags don't end up in the VUE (either in or out of the * VS). Instead, they're uploaded as the last vertex element, and the data * is passed sideband through the fixed function units. So, we need to * prepare the vertex buffer for it, but it's not present in inputs_read. diff --git a/src/mesa/drivers/dri/i965/brw_fbo.c b/src/mesa/drivers/dri/i965/brw_fbo.c index 7a5f76ab333..160c33d3b68 100644 --- a/src/mesa/drivers/dri/i965/brw_fbo.c +++ b/src/mesa/drivers/dri/i965/brw_fbo.c @@ -905,7 +905,7 @@ brw_blit_framebuffer(struct gl_context *ctx, return; if (devinfo->ver < 6) { - /* On gen4-5, try BLT first. + /* On gfx4-5, try BLT first. * * Gen4-5 have a single ring for both 3D and BLT operations, so there's * no inter-ring synchronization issues like on Gen6+. It is apparently @@ -1061,7 +1061,7 @@ brw_cache_flush_for_render(struct brw_context *brw, struct brw_bo *bo, * * Even though it's not obvious, this can easily happen in practice. * Suppose a client is blending on a surface with sRGB encode enabled on - * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client + * gfx9. This implies that you get AUX_USAGE_CCS_D at best. If the client * then disables sRGB decode and continues blending we will flip on * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is * perfectly valid since CCS_E is a subset of CCS_D). However, this means diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.c b/src/mesa/drivers/dri/i965/brw_ff_gs.c index 4baf292db5e..b9cdd0c1cb3 100644 --- a/src/mesa/drivers/dri/i965/brw_ff_gs.c +++ b/src/mesa/drivers/dri/i965/brw_ff_gs.c @@ -105,7 +105,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw, default: unreachable("Unexpected primitive type in Gen6 SOL program."); } - gen6_sol_program(&c, key, num_verts, check_edge_flag); + gfx6_sol_program(&c, key, num_verts, check_edge_flag); } else { /* On Gen4-5, we use the GS to decompose certain types of primitives. * Note that primitives which don't require a GS program have already @@ -222,7 +222,7 @@ brw_ff_gs_populate_key(struct brw_context *brw, } } } else { - /* Pre-gen6, GS is used to transform QUADLIST, QUADSTRIP, and LINELOOP + /* Pre-gfx6, GS is used to transform QUADLIST, QUADSTRIP, and LINELOOP * into simpler primitives. */ key->need_gs_prog = (brw->primitive == _3DPRIM_QUADLIST || diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.h b/src/mesa/drivers/dri/i965/brw_ff_gs.h index b32b20d89bd..351bdb77097 100644 --- a/src/mesa/drivers/dri/i965/brw_ff_gs.h +++ b/src/mesa/drivers/dri/i965/brw_ff_gs.h @@ -107,7 +107,7 @@ void brw_ff_gs_quads(struct brw_ff_gs_compile *c, void brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key); void brw_ff_gs_lines(struct brw_ff_gs_compile *c); -void gen6_sol_program(struct brw_ff_gs_compile *c, +void gfx6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key, unsigned num_verts, bool check_edge_flag); diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs_emit.c b/src/mesa/drivers/dri/i965/brw_ff_gs_emit.c index 6a7a52e4481..6b5f234adc6 100644 --- a/src/mesa/drivers/dri/i965/brw_ff_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_ff_gs_emit.c @@ -334,7 +334,7 @@ void brw_ff_gs_lines(struct brw_ff_gs_compile *c) * (transform feedback). */ void -gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key, +gfx6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key, unsigned num_verts, bool check_edge_flags) { struct brw_codegen *p = &c->func; diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c b/src/mesa/drivers/dri/i965/brw_formatquery.c index ddf69e708eb..86dd4835135 100644 --- a/src/mesa/drivers/dri/i965/brw_formatquery.c +++ b/src/mesa/drivers/dri/i965/brw_formatquery.c @@ -63,7 +63,7 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum target, * internalformat is RGBA16F, R32F, RG32F, or RGBA32F." * * In brw_render_target_supported, we prevent formats with a size - * greater than 8 bytes from using 8x MSAA on gen7. + * greater than 8 bytes from using 8x MSAA on gfx7. */ samples[0] = 4; return 1; diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index cfab8fb5bd4..346638aab05 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -40,7 +40,7 @@ assign_gs_binding_table_offsets(const struct gen_device_info *devinfo, const struct gl_program *prog, struct brw_gs_prog_data *prog_data) { - /* In gen6 we reserve the first BRW_MAX_SOL_BINDINGS entries for transform + /* In gfx6 we reserve the first BRW_MAX_SOL_BINDINGS entries for transform * feedback surfaces. */ uint32_t reserved = devinfo->ver == 6 ? BRW_MAX_SOL_BINDINGS : 0; diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 5e85f4531de..e86e6fb7764 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -125,7 +125,7 @@ process_glsl_ir(struct brw_context *brw, lower_instructions(shader->ir, instructions_to_lower); - /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, + /* Pre-gfx6 HW can only nest if-statements 16 deep. Beyond this, * if-statements need to be flattened. */ if (devinfo->ver < 6) diff --git a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c index 17e667a8786..8b23cbbfbcd 100644 --- a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c @@ -394,7 +394,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, goto fail; /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although - * on gen7 platforms we also need to create Y-tiled copies of stencil for + * on gfx7 platforms we also need to create Y-tiled copies of stencil for * texturing since the hardware can't sample from W-tiled surfaces. For * everything else, check for corner cases needing special treatment. */ @@ -746,7 +746,7 @@ create_ccs_buf_for_image(struct brw_context *brw, return false; } - /* On gen10+ we start using an extra space in the aux buffer to store the + /* On gfx10+ we start using an extra space in the aux buffer to store the * indirect clear color. However, if we imported an image from the window * system with CCS, we don't have the extra space at the end of the aux * buffer. So create a new bo here that will store that clear color. @@ -845,7 +845,7 @@ brw_miptree_create_for_dri_image(struct brw_context *brw, mt->drm_modifier = image->modifier; /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION - * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has + * for EGL images from non-tile aligned sufaces in gfx4 hw and earlier which has * trouble resolving back to destination image due to alignment issues. */ const struct gen_device_info *devinfo = &brw->screen->devinfo; @@ -1303,7 +1303,7 @@ brw_miptree_copy_slice(struct brw_context *brw, width, height); if (devinfo->ver >= 6) { - /* On gen6 and above, we just use blorp. It's faster than the blitter + /* On gfx6 and above, we just use blorp. It's faster than the blitter * and can handle everything without software fallbacks. */ brw_blorp_copy_miptrees(brw, @@ -1567,7 +1567,7 @@ brw_miptree_alloc_aux(struct brw_context *brw, struct brw_mipmap_tree *mt) * A CCS value of 0 indicates that the corresponding block is in the * pass-through state which is what we want. * - * For CCS_D, do the same thing. On gen9+, this avoids having any + * For CCS_D, do the same thing. On gfx9+, this avoids having any * undefined bits in the aux buffer. */ initial_state = ISL_AUX_STATE_PASS_THROUGH; @@ -1646,7 +1646,7 @@ brw_miptree_sample_with_hiz(struct brw_context *brw, */ return (mt->surf.samples == 1 && mt->target != GL_TEXTURE_3D && - mt->target != GL_TEXTURE_1D /* gen9+ restriction */); + mt->target != GL_TEXTURE_1D /* gfx9+ restriction */); } static bool @@ -1908,12 +1908,12 @@ enum isl_aux_usage brw_miptree_texture_aux_usage(struct brw_context *brw, struct brw_mipmap_tree *mt, enum isl_format view_format, - enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits) + enum gfx9_astc5x5_wa_tex_type astc5x5_wa_bits) { assert(brw->screen->devinfo.ver == 9 || astc5x5_wa_bits == 0); - /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side - * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for + /* On gfx9, ASTC 5x5 textures cannot live in the sampler cache along side + * CCS or HiZ compressed textures. See gfx9_apply_astc5x5_wa_flush() for * details. */ if ((astc5x5_wa_bits & GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) && @@ -1958,11 +1958,11 @@ brw_miptree_texture_aux_usage(struct brw_context *brw, static bool isl_formats_are_fast_clear_compatible(enum isl_format a, enum isl_format b) { - /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear + /* On gfx8 and earlier, the hardware was only capable of handling 0/1 clear * values so sRGB curve application was a no-op for all fast-clearable * formats. * - * On gen9+, the hardware supports arbitrary clear values. For sRGB clear + * On gfx9+, the hardware supports arbitrary clear values. For sRGB clear * values, the hardware interprets the floats, not as what would be * returned from the sampler (or written by the shader), but as being * between format conversion and sRGB curve application. This means that @@ -1978,7 +1978,7 @@ brw_miptree_prepare_texture(struct brw_context *brw, enum isl_format view_format, uint32_t start_level, uint32_t num_levels, uint32_t start_layer, uint32_t num_layers, - enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits) + enum gfx9_astc5x5_wa_tex_type astc5x5_wa_bits) { enum isl_aux_usage aux_usage = brw_miptree_texture_aux_usage(brw, mt, view_format, astc5x5_wa_bits); @@ -2030,7 +2030,7 @@ brw_miptree_render_aux_usage(struct brw_context *brw, return ISL_AUX_USAGE_NONE; } - /* gen9+ hardware technically supports non-0/1 clear colors with sRGB + /* gfx9+ hardware technically supports non-0/1 clear colors with sRGB * formats. However, there are issues with blending where it doesn't * properly apply the sRGB curve to the clear color when blending. */ @@ -2822,7 +2822,7 @@ brw_miptree_map_s8(struct brw_context *brw, * Mapping functions for packed depth/stencil miptrees backed by real separate * miptrees for depth and stencil. * - * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer + * On gfx7, and to support HiZ pre-gfx7, we have to have the stencil buffer * separate from the depth buffer. Yet at the GL API level, we have to expose * packed depth/stencil textures and FBO attachments, and Mesa core expects to * be able to map that memory for texture storage and glReadPixels-type diff --git a/src/mesa/drivers/dri/i965/brw_mipmap_tree.h b/src/mesa/drivers/dri/i965/brw_mipmap_tree.h index 21e50259780..61a25072c9c 100644 --- a/src/mesa/drivers/dri/i965/brw_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/brw_mipmap_tree.h @@ -607,14 +607,14 @@ enum isl_aux_usage brw_miptree_texture_aux_usage(struct brw_context *brw, struct brw_mipmap_tree *mt, enum isl_format view_format, - enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits); + enum gfx9_astc5x5_wa_tex_type astc5x5_wa_bits); void brw_miptree_prepare_texture(struct brw_context *brw, struct brw_mipmap_tree *mt, enum isl_format view_format, uint32_t start_level, uint32_t num_levels, uint32_t start_layer, uint32_t num_layers, - enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits); + enum gfx9_astc5x5_wa_tex_type astc5x5_wa_bits); void brw_miptree_prepare_image(struct brw_context *brw, struct brw_mipmap_tree *mt); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 54e319ae9a9..1f32a413b05 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -572,7 +572,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) * operation and then a dummy DRAW after every MI_SET_CONTEXT and * after any PIPELINE_SELECT that is enabling 3D mode. */ - gen7_emit_cs_stall_flush(brw); + gfx7_emit_cs_stall_flush(brw); BEGIN_BATCH(7); OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2)); @@ -731,7 +731,7 @@ brw_upload_invariant_state(struct brw_context *brw) * Define the base addresses which some state is referenced from. * * This allows us to avoid having to emit relocations for the objects, - * and is actually required for binding table pointers on gen6. + * and is actually required for binding table pointers on gfx6. * * Surface state base address covers binding table pointers and * surface state objects, but not the surfaces that the surface state diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c index c702b6fb509..3621dd134f1 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_query.c +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c @@ -395,7 +395,7 @@ oa_metrics_kernel_support(int fd, const struct gen_device_info *devinfo) } if (devinfo->ver >= 8) { - /* 4.13+ api required for gen8 - gen9 */ + /* 4.13+ api required for gfx8 - gfx9 */ int mask; struct drm_i915_getparam gp = { .param = I915_PARAM_SLICE_MASK, diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index ac1ddaef4ca..7fbcc9b1751 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -116,7 +116,7 @@ brw_emit_depth_stall_flushes(struct brw_context *brw) * to be sent before any combination of VS associated 3DSTATE." */ void -gen7_emit_vs_workaround_flush(struct brw_context *brw) +gfx7_emit_vs_workaround_flush(struct brw_context *brw) { ASSERTED const struct gen_device_info *devinfo = &brw->screen->devinfo; @@ -166,7 +166,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw) * so that it doesn't hang a previous 3DPRIMITIVE. */ void -gen7_emit_isp_disable(struct brw_context *brw) +gfx7_emit_isp_disable(struct brw_context *brw) { brw->vtbl.emit_raw_pipe_control(brw, PIPE_CONTROL_STALL_AT_SCOREBOARD | @@ -185,10 +185,10 @@ gen7_emit_isp_disable(struct brw_context *brw) } /** - * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set. + * Emit a PIPE_CONTROL command for gfx7 with the CS Stall bit set. */ void -gen7_emit_cs_stall_flush(struct brw_context *brw) +gfx7_emit_cs_stall_flush(struct brw_context *brw) { brw_emit_pipe_control_write(brw, PIPE_CONTROL_CS_STALL @@ -199,7 +199,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw) /** * Emits a PIPE_CONTROL with a non-zero post-sync operation, for - * implementing two workarounds on gen6. From section 1.4.7.1 + * implementing two workarounds on gfx6. From section 1.4.7.1 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: * * [DevSNB-C+{W/A}] Before any depth stall flush (including those @@ -342,7 +342,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags) brw->workaround_bo, brw->workaround_bo_offset); } } else { - /* On gen4-5, a regular pipe control seems to suffice. */ + /* On gfx4-5, a regular pipe control seems to suffice. */ brw_emit_pipe_control_flush(brw, flags); } } @@ -398,29 +398,29 @@ brw_init_pipe_control(struct brw_context *brw, { switch (devinfo->ver) { case 11: - brw->vtbl.emit_raw_pipe_control = gen11_emit_raw_pipe_control; + brw->vtbl.emit_raw_pipe_control = gfx11_emit_raw_pipe_control; break; case 9: - brw->vtbl.emit_raw_pipe_control = gen9_emit_raw_pipe_control; + brw->vtbl.emit_raw_pipe_control = gfx9_emit_raw_pipe_control; break; case 8: - brw->vtbl.emit_raw_pipe_control = gen8_emit_raw_pipe_control; + brw->vtbl.emit_raw_pipe_control = gfx8_emit_raw_pipe_control; break; case 7: brw->vtbl.emit_raw_pipe_control = - devinfo->is_haswell ? gen75_emit_raw_pipe_control - : gen7_emit_raw_pipe_control; + devinfo->is_haswell ? gfx75_emit_raw_pipe_control + : gfx7_emit_raw_pipe_control; break; case 6: - brw->vtbl.emit_raw_pipe_control = gen6_emit_raw_pipe_control; + brw->vtbl.emit_raw_pipe_control = gfx6_emit_raw_pipe_control; break; case 5: - brw->vtbl.emit_raw_pipe_control = gen5_emit_raw_pipe_control; + brw->vtbl.emit_raw_pipe_control = gfx5_emit_raw_pipe_control; break; case 4: brw->vtbl.emit_raw_pipe_control = - devinfo->is_g4x ? gen45_emit_raw_pipe_control - : gen4_emit_raw_pipe_control; + devinfo->is_g4x ? gfx45_emit_raw_pipe_control + : gfx4_emit_raw_pipe_control; break; default: unreachable("Unhandled Gen."); @@ -430,7 +430,7 @@ brw_init_pipe_control(struct brw_context *brw, return 0; /* We can't just use brw_state_batch to get a chunk of space for - * the gen6 workaround because it involves actually writing to + * the gfx6 workaround because it involves actually writing to * the buffer, and the kernel doesn't let us write to the batch. */ brw->workaround_bo = brw_bo_alloc(brw->bufmgr, "workaround", 4096, diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.h b/src/mesa/drivers/dri/i965/brw_pipe_control.h index cbcd6b25919..79bbc882424 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.h +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.h @@ -88,8 +88,8 @@ void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags); void brw_emit_mi_flush(struct brw_context *brw); void brw_emit_post_sync_nonzero_flush(struct brw_context *brw); void brw_emit_depth_stall_flushes(struct brw_context *brw); -void gen7_emit_vs_workaround_flush(struct brw_context *brw); -void gen7_emit_cs_stall_flush(struct brw_context *brw); -void gen7_emit_isp_disable(struct brw_context *brw); +void gfx7_emit_vs_workaround_flush(struct brw_context *brw); +void gfx7_emit_cs_stall_flush(struct brw_context *brw); +void gfx7_emit_isp_disable(struct brw_context *brw); #endif diff --git a/src/mesa/drivers/dri/i965/brw_pixel_read.c b/src/mesa/drivers/dri/i965/brw_pixel_read.c index 5cf0ae2f7fd..3444ce3ab1e 100644 --- a/src/mesa/drivers/dri/i965/brw_pixel_read.c +++ b/src/mesa/drivers/dri/i965/brw_pixel_read.c @@ -137,9 +137,9 @@ brw_readpixels_tiled_memcpy(struct gl_context *ctx, /* tiled_to_linear() assumes that if the object is swizzled, it is using * I915_BIT6_SWIZZLE_9_10 for X and I915_BIT6_SWIZZLE_9 for Y. This is only - * true on gen5 and above. + * true on gfx5 and above. * - * The killer on top is that some gen4 have an L-shaped swizzle mode, where + * The killer on top is that some gfx4 have an L-shaped swizzle mode, where * parts of the memory aren't swizzled at all. Userspace just can't handle * that. */ diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c b/src/mesa/drivers/dri/i965/brw_program_cache.c index 1478bd2b1b9..df2b92e0d2c 100644 --- a/src/mesa/drivers/dri/i965/brw_program_cache.c +++ b/src/mesa/drivers/dri/i965/brw_program_cache.c @@ -232,7 +232,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size) cache->map = map; /* Since we have a new BO in place, we need to signal the units - * that depend on it (state base address on gen5+, or unit state before). + * that depend on it (state base address on gfx5+, or unit state before). */ brw->ctx.NewDriverState |= BRW_NEW_PROGRAM_CACHE; brw->batch.state_base_address_emitted = false; diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 5f3b13be399..2964f6b7ffc 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -611,7 +611,7 @@ void brw_init_common_queryobj_functions(struct dd_function_table *functions) } /* Initialize Gen4/5-specific query object functions. */ -void gen4_init_queryobj_functions(struct dd_function_table *functions) +void gfx4_init_queryobj_functions(struct dd_function_table *functions) { functions->BeginQuery = brw_begin_query; functions->EndQuery = brw_end_query; diff --git a/src/mesa/drivers/dri/i965/brw_screen.c b/src/mesa/drivers/dri/i965/brw_screen.c index fa5ef3c51e9..4324da42b0c 100644 --- a/src/mesa/drivers/dri/i965/brw_screen.c +++ b/src/mesa/drivers/dri/i965/brw_screen.c @@ -2111,22 +2111,22 @@ brw_detect_pipelined_so(struct brw_screen *screen) const int* brw_supported_msaa_modes(const struct brw_screen *screen) { - static const int gen9_modes[] = {16, 8, 4, 2, 0, -1}; - static const int gen8_modes[] = {8, 4, 2, 0, -1}; - static const int gen7_modes[] = {8, 4, 0, -1}; - static const int gen6_modes[] = {4, 0, -1}; - static const int gen4_modes[] = {0, -1}; + static const int gfx9_modes[] = {16, 8, 4, 2, 0, -1}; + static const int gfx8_modes[] = {8, 4, 2, 0, -1}; + static const int gfx7_modes[] = {8, 4, 0, -1}; + static const int gfx6_modes[] = {4, 0, -1}; + static const int gfx4_modes[] = {0, -1}; if (screen->devinfo.ver >= 9) { - return gen9_modes; + return gfx9_modes; } else if (screen->devinfo.ver >= 8) { - return gen8_modes; + return gfx8_modes; } else if (screen->devinfo.ver >= 7) { - return gen7_modes; + return gfx7_modes; } else if (screen->devinfo.ver == 6) { - return gen6_modes; + return gfx6_modes; } else { - return gen4_modes; + return gfx4_modes; } } @@ -2354,21 +2354,21 @@ brw_screen_make_configs(__DRIscreen *dri_screen) } if (devinfo->ver >= 9) { - static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16}; - multisample_samples = multisample_samples_gen9; - num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9); + static const uint8_t multisample_samples_gfx9[] = {2, 4, 8, 16}; + multisample_samples = multisample_samples_gfx9; + num_msaa_modes = ARRAY_SIZE(multisample_samples_gfx9); } else if (devinfo->ver == 8) { - static const uint8_t multisample_samples_gen8[] = {2, 4, 8}; - multisample_samples = multisample_samples_gen8; - num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8); + static const uint8_t multisample_samples_gfx8[] = {2, 4, 8}; + multisample_samples = multisample_samples_gfx8; + num_msaa_modes = ARRAY_SIZE(multisample_samples_gfx8); } else if (devinfo->ver == 7) { - static const uint8_t multisample_samples_gen7[] = {4, 8}; - multisample_samples = multisample_samples_gen7; - num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7); + static const uint8_t multisample_samples_gfx7[] = {4, 8}; + multisample_samples = multisample_samples_gfx7; + num_msaa_modes = ARRAY_SIZE(multisample_samples_gfx7); } else if (devinfo->ver == 6) { - static const uint8_t multisample_samples_gen6[] = {4}; - multisample_samples = multisample_samples_gen6; - num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6); + static const uint8_t multisample_samples_gfx6[] = {4}; + multisample_samples = multisample_samples_gfx6; + num_msaa_modes = ARRAY_SIZE(multisample_samples_gfx6); } new_configs = driCreateConfigs(formats[i], @@ -2547,7 +2547,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen) screen->no_hw = devinfo->no_hw; if (devinfo->ver >= 12) { - fprintf(stderr, "gen12 and newer are not supported on i965\n"); + fprintf(stderr, "gfx12 and newer are not supported on i965\n"); return NULL; } @@ -2558,7 +2558,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen) if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->ver < 7) { fprintf(stderr, - "shader_time debugging requires gen7 (Ivybridge) or better.\n"); + "shader_time debugging requires gfx7 (Ivybridge) or better.\n"); intel_debug &= ~DEBUG_SHADER_TIME; } diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 2bcbf13ff75..f1e5b0f78e9 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -81,45 +81,45 @@ extern const struct brw_tracked_state brw_psp_urb_cbs; extern const struct brw_tracked_state brw_indices; extern const struct brw_tracked_state brw_index_buffer; -extern const struct brw_tracked_state gen7_cs_push_constants; -extern const struct brw_tracked_state gen6_binding_table_pointers; -extern const struct brw_tracked_state gen6_gs_binding_table; -extern const struct brw_tracked_state gen6_renderbuffer_surfaces; -extern const struct brw_tracked_state gen6_sampler_state; -extern const struct brw_tracked_state gen6_sol_surface; -extern const struct brw_tracked_state gen6_sf_vp; -extern const struct brw_tracked_state gen6_urb; -extern const struct brw_tracked_state gen7_l3_state; -extern const struct brw_tracked_state gen7_push_constant_space; -extern const struct brw_tracked_state gen7_urb; -extern const struct brw_tracked_state gen8_pma_fix; +extern const struct brw_tracked_state gfx7_cs_push_constants; +extern const struct brw_tracked_state gfx6_binding_table_pointers; +extern const struct brw_tracked_state gfx6_gs_binding_table; +extern const struct brw_tracked_state gfx6_renderbuffer_surfaces; +extern const struct brw_tracked_state gfx6_sampler_state; +extern const struct brw_tracked_state gfx6_sol_surface; +extern const struct brw_tracked_state gfx6_sf_vp; +extern const struct brw_tracked_state gfx6_urb; +extern const struct brw_tracked_state gfx7_l3_state; +extern const struct brw_tracked_state gfx7_push_constant_space; +extern const struct brw_tracked_state gfx7_urb; +extern const struct brw_tracked_state gfx8_pma_fix; extern const struct brw_tracked_state brw_cs_work_groups_surface; -void gen4_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx4_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen45_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx45_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen5_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx5_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen6_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx6_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen7_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx7_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen75_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx75_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen8_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx8_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen9_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx9_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); -void gen11_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, +void gfx11_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm); @@ -145,7 +145,7 @@ brw_depthbuffer_format(struct brw_context *brw); void brw_upload_state_base_address(struct brw_context *brw); /* gfx8_depth_state.c */ -void gen8_write_pma_stall_bits(struct brw_context *brw, +void gfx8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits); /* brw_disk_cache.c */ @@ -279,7 +279,7 @@ brw_upload_cs_push_constants(struct brw_context *brw, /* gfx7_vs_state.c */ void -gen7_upload_constant_state(struct brw_context *brw, +gfx7_upload_constant_state(struct brw_context *brw, const struct brw_stage_state *stage_state, bool active, unsigned opcode); @@ -294,7 +294,7 @@ bool brw_is_drawing_lines(const struct brw_context *brw); /* gfx7_l3_state.c */ void -gen7_restore_default_l3_config(struct brw_context *brw); +gfx7_restore_default_l3_config(struct brw_context *brw); static inline bool use_state_point_size(const struct brw_context *brw) @@ -349,15 +349,15 @@ void brw_copy_pipeline_atoms(struct brw_context *brw, enum brw_pipeline pipeline, const struct brw_tracked_state **atoms, int num_atoms); -void gen4_init_atoms(struct brw_context *brw); -void gen45_init_atoms(struct brw_context *brw); -void gen5_init_atoms(struct brw_context *brw); -void gen6_init_atoms(struct brw_context *brw); -void gen7_init_atoms(struct brw_context *brw); -void gen75_init_atoms(struct brw_context *brw); -void gen8_init_atoms(struct brw_context *brw); -void gen9_init_atoms(struct brw_context *brw); -void gen11_init_atoms(struct brw_context *brw); +void gfx4_init_atoms(struct brw_context *brw); +void gfx45_init_atoms(struct brw_context *brw); +void gfx5_init_atoms(struct brw_context *brw); +void gfx6_init_atoms(struct brw_context *brw); +void gfx7_init_atoms(struct brw_context *brw); +void gfx75_init_atoms(struct brw_context *brw); +void gfx8_init_atoms(struct brw_context *brw); +void gfx9_init_atoms(struct brw_context *brw); +void gfx11_init_atoms(struct brw_context *brw); /* Memory Object Control State: * Specifying zero for L3 means "uncached in L3", at least on Haswell diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 6242d0c2eb5..83b67b6e8d3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -69,7 +69,7 @@ brw_enable_obj_preemption(struct brw_context *brw, bool enable) } static void -brw_upload_gen11_slice_hashing_state(struct brw_context *brw) +brw_upload_gfx11_slice_hashing_state(struct brw_context *brw) { const struct gen_device_info *devinfo = &brw->screen->devinfo; int subslices_delta = @@ -130,7 +130,7 @@ brw_upload_gen11_slice_hashing_state(struct brw_context *brw) OUT_RELOC(brw->batch.state.bo, 0, hash_address | 1); ADVANCE_BATCH(); - /* From gen10/gen11 workaround table in h/w specs: + /* From gfx10/gfx11 workaround table in h/w specs: * * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1 * a value of 0xFFFF" @@ -214,7 +214,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw) } if (devinfo->ver >= 8) { - gen8_emit_3dstate_sample_pattern(brw); + gfx8_emit_3dstate_sample_pattern(brw); BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2)); @@ -259,7 +259,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_enable_obj_preemption(brw, true); if (devinfo->ver == 11) - brw_upload_gen11_slice_hashing_state(brw); + brw_upload_gfx11_slice_hashing_state(brw); } static inline const struct brw_tracked_state * @@ -310,25 +310,25 @@ void brw_init_state( struct brw_context *brw ) brw_init_caches(brw); if (devinfo->ver >= 11) - gen11_init_atoms(brw); + gfx11_init_atoms(brw); else if (devinfo->ver >= 10) unreachable("Gen10 support dropped."); else if (devinfo->ver >= 9) - gen9_init_atoms(brw); + gfx9_init_atoms(brw); else if (devinfo->ver >= 8) - gen8_init_atoms(brw); + gfx8_init_atoms(brw); else if (devinfo->is_haswell) - gen75_init_atoms(brw); + gfx75_init_atoms(brw); else if (devinfo->ver >= 7) - gen7_init_atoms(brw); + gfx7_init_atoms(brw); else if (devinfo->ver >= 6) - gen6_init_atoms(brw); + gfx6_init_atoms(brw); else if (devinfo->ver >= 5) - gen5_init_atoms(brw); + gfx5_init_atoms(brw); else if (devinfo->is_g4x) - gen45_init_atoms(brw); + gfx45_init_atoms(brw); else - gen4_init_atoms(brw); + gfx4_init_atoms(brw); brw_upload_initial_gpu_state(brw); diff --git a/src/mesa/drivers/dri/i965/brw_tex_image.c b/src/mesa/drivers/dri/i965/brw_tex_image.c index 9953ac1ad10..854fdef9b36 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_image.c +++ b/src/mesa/drivers/dri/i965/brw_tex_image.c @@ -240,9 +240,9 @@ brw_texsubimage_tiled_memcpy(struct gl_context * ctx, /* linear_to_tiled() assumes that if the object is swizzled, it is using * I915_BIT6_SWIZZLE_9_10 for X and I915_BIT6_SWIZZLE_9 for Y. This is only - * true on gen5 and above. + * true on gfx5 and above. * - * The killer on top is that some gen4 have an L-shaped swizzle mode, where + * The killer on top is that some gfx4 have an L-shaped swizzle mode, where * parts of the memory aren't swizzled at all. Userspace just can't handle * that. */ @@ -792,9 +792,9 @@ brw_gettexsubimage_tiled_memcpy(struct gl_context *ctx, /* tiled_to_linear() assumes that if the object is swizzled, it is using * I915_BIT6_SWIZZLE_9_10 for X and I915_BIT6_SWIZZLE_9 for Y. This is only - * true on gen5 and above. + * true on gfx5 and above. * - * The killer on top is that some gen4 have an L-shaped swizzle mode, where + * The killer on top is that some gfx4 have an L-shaped swizzle mode, where * parts of the memory aren't swizzled at all. Userspace just can't handle * that. */ diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 5e975661b14..9566670891c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -180,7 +180,7 @@ brw_codegen_wm_prog(struct brw_context *brw, } static uint8_t -gen6_gather_workaround(GLenum internalformat) +gfx6_gather_workaround(GLenum internalformat) { switch (internalformat) { case GL_R8I: return WA_SIGN | WA_8BIT; @@ -279,7 +279,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, * UNORM/FLOAT instead and fix it in the shader. */ if (devinfo->ver == 6 && prog->info.uses_texture_gather) { - key->gen6_gather_wa[s] = gen6_gather_workaround(img->InternalFormat); + key->gfx6_gather_wa[s] = gfx6_gather_workaround(img->InternalFormat); } /* If this is a multisample sampler, and uses the CMS MSAA layout, @@ -289,7 +289,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, struct brw_texture_object *intel_tex = brw_texture_object((struct gl_texture_object *)t); - /* From gen9 onwards some single sampled buffers can also be + /* From gfx9 onwards some single sampled buffers can also be * compressed. These don't need ld2dms sampling along with mcs fetch. */ if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) { @@ -519,7 +519,7 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) } /* _NEW_COLOR | _NEW_BUFFERS */ - /* Pre-gen6, the hardware alpha test always used each render + /* Pre-gfx6, the hardware alpha test always used each render * target's alpha to do alpha test, as opposed to render target 0's alpha * like GL requires. Fix that by building the alpha test into the * shader, and we'll skip enabling the fixed function alpha test. diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 137387a1277..56cd446c63a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -186,7 +186,7 @@ brw_emit_surface_state(struct brw_context *brw, .clear_address = clear_offset, .x_offset_sa = tile_x, .y_offset_sa = tile_y); if (aux_surf) { - /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the + /* On gfx7 and prior, the upper 20 bits of surface state DWORD 6 are the * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits * contain other control information. Since buffer addresses are always * on 4k boundaries (and thus have their lower 12 bits zero), we can use @@ -227,7 +227,7 @@ brw_emit_surface_state(struct brw_context *brw, } static uint32_t -gen6_update_renderbuffer_surface(struct brw_context *brw, +gfx6_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, unsigned unit, uint32_t surf_index) @@ -528,7 +528,7 @@ static void brw_update_texture_surface(struct gl_context *ctx, for_txf ? GL_DECODE_EXT : sampler->Attrib.sRGBDecode); - /* Implement gen6 and gen7 gather work-around */ + /* Implement gfx6 and gfx7 gather work-around */ bool need_green_to_blue = false; if (for_gather) { if (devinfo->ver == 7 && (format == ISL_FORMAT_R32G32_FLOAT || @@ -612,7 +612,7 @@ static void brw_update_texture_surface(struct gl_context *ctx, enum isl_aux_usage aux_usage = brw_miptree_texture_aux_usage(brw, mt, format, - brw->gen9_astc5x5_wa_tex_mask); + brw->gfx9_astc5x5_wa_tex_mask); brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, surf_offset, surf_index, @@ -901,7 +901,7 @@ emit_null_surface_state(struct brw_context *brw, * usable for further buffers when doing ARB_draw_buffer support. */ static uint32_t -gen4_update_renderbuffer_surface(struct brw_context *brw, +gfx4_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, unsigned unit, uint32_t surf_index) @@ -922,7 +922,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, brw_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); if (tile_x != 0 || tile_y != 0) { - /* Original gen4 hardware couldn't draw to a non-tile-aligned + /* Original gfx4 hardware couldn't draw to a non-tile-aligned * destination in a miptree unless you actually setup your renderbuffer * as a miptree and used the fragile lod/array_index/etc. controls to * select the image. So, instead, we just make a new single-level @@ -1020,8 +1020,8 @@ update_renderbuffer_surfaces(struct brw_context *brw) if (brw_renderbuffer(rb)) { surf_offsets[rt_start + i] = devinfo->ver >= 6 ? - gen6_update_renderbuffer_surface(brw, rb, i, rt_start + i) : - gen4_update_renderbuffer_surface(brw, rb, i, rt_start + i); + gfx6_update_renderbuffer_surface(brw, rb, i, rt_start + i) : + gfx4_update_renderbuffer_surface(brw, rb, i, rt_start + i); } else { emit_null_surface_state(brw, fb, &surf_offsets[rt_start + i]); } @@ -1056,7 +1056,7 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = { .emit = update_renderbuffer_surfaces, }; -const struct brw_tracked_state gen6_renderbuffer_surfaces = { +const struct brw_tracked_state gfx6_renderbuffer_surfaces = { .dirty = { .mesa = _NEW_BUFFERS, .brw = BRW_NEW_BATCH | @@ -1119,7 +1119,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) enum isl_aux_usage aux_usage = brw_miptree_texture_aux_usage(brw, irb->mt, format, - brw->gen9_astc5x5_wa_tex_mask); + brw->gfx9_astc5x5_wa_tex_mask); if (brw->draw_aux_usage[i] == ISL_AUX_USAGE_NONE) aux_usage = ISL_AUX_USAGE_NONE; diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index 8d17ceec166..3cdcef9e37c 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -274,7 +274,7 @@ blorp_emit_urb_config(struct blorp_batch *batch, struct brw_context *brw = batch->driver_batch; #if GFX_VER == 6 - gen6_upload_urb(brw, vs_entry_size, false, 0); + gfx6_upload_urb(brw, vs_entry_size, false, 0); #else /* We calculate it now and emit later. */ brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size); @@ -342,7 +342,7 @@ retry: brw_upload_state_base_address(brw); #if GFX_VER >= 8 - gen7_l3_state.emit(brw); + gfx7_l3_state.emit(brw); #endif #if GFX_VER >= 6 @@ -350,7 +350,7 @@ retry: #endif #if GFX_VER == 8 - gen8_write_pma_stall_bits(brw, 0); + gfx8_write_pma_stall_bits(brw, 0); #endif const unsigned scale = params->fast_clear_op ? UINT_MAX : 1; diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 535428d13f8..f9fc39bf680 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -616,7 +616,7 @@ genX(emit_vertices)(struct brw_context *brw) */ #if GFX_VER >= 6 assert(nr_elements <= 34); - const struct brw_vertex_element *gen6_edgeflag_input = NULL; + const struct brw_vertex_element *gfx6_edgeflag_input = NULL; #else assert(nr_elements <= 18); #endif @@ -643,7 +643,7 @@ genX(emit_vertices)(struct brw_context *brw) assert(!(is_passthru_format(format) && uses_edge_flag)); #endif - /* The gen4 driver expects edgeflag to come in as a float, and passes + /* The gfx4 driver expects edgeflag to come in as a float, and passes * that float on to the tests in the clipper. Mesa's current vertex * attribute value for EdgeFlag is stored as a float, which works out. * glEdgeFlagPointer, on the other hand, gives us an unnormalized @@ -655,7 +655,7 @@ genX(emit_vertices)(struct brw_context *brw) */ #if GFX_VER >= 6 if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) { - gen6_edgeflag_input = input; + gfx6_edgeflag_input = input; continue; } #endif @@ -788,16 +788,16 @@ genX(emit_vertices)(struct brw_context *brw) } #if GFX_VER >= 6 - if (gen6_edgeflag_input) { - const struct gl_vertex_format *glformat = gen6_edgeflag_input->glformat; + if (gfx6_edgeflag_input) { + const struct gl_vertex_format *glformat = gfx6_edgeflag_input->glformat; const uint32_t format = brw_get_vertex_surface_type(brw, glformat); struct GENX(VERTEX_ELEMENT_STATE) elem_state = { .Valid = true, - .VertexBufferIndex = gen6_edgeflag_input->buffer, + .VertexBufferIndex = gfx6_edgeflag_input->buffer, .EdgeFlagEnable = true, .SourceElementFormat = format, - .SourceElementOffset = gen6_edgeflag_input->offset, + .SourceElementOffset = gfx6_edgeflag_input->offset, .Component0Control = VFCOMP_STORE_SRC, .Component1Control = VFCOMP_STORE_0, .Component2Control = VFCOMP_STORE_0, @@ -819,7 +819,7 @@ genX(emit_vertices)(struct brw_context *brw) * above so we need to compensate for that in the element indices used * below. */ - if (input == gen6_edgeflag_input) + if (input == gfx6_edgeflag_input) element_index = nr_elements - 1; else element_index = j++; @@ -1798,7 +1798,7 @@ genX(upload_wm)(struct brw_context *brw) UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo; #if GFX_VER == 6 - /* We can't fold this into gen6_upload_wm_push_constants(), because + /* We can't fold this into gfx6_upload_wm_push_constants(), because * according to the SNB PRM, vol 2 part 1 section 7.2.2 * (3DSTATE_CONSTANT_PS [DevSNB]): * @@ -1808,7 +1808,7 @@ genX(upload_wm)(struct brw_context *brw) if (wm_prog_data->base.nr_params != 0) { wmcp.Buffer0Valid = true; /* Pointer to the WM constant buffer. Covered by the set of - * state flags from gen6_upload_wm_push_constants. + * state flags from gfx6_upload_wm_push_constants. */ wmcp.ConstantBody.PointertoConstantBuffer0 = stage_state->push_const_offset; wmcp.ConstantBody.ConstantBuffer0ReadLength = stage_state->push_const_size - 1; @@ -1830,7 +1830,7 @@ genX(upload_wm)(struct brw_context *brw) #endif #if GFX_VER == 4 - /* On gen4, we only have one shader kernel */ + /* On gfx4, we only have one shader kernel */ if (brw_wm_state_has_ksp(wm, 0)) { assert(brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0) == 0); wm.KernelStartPointer0 = KSP(brw, stage_state->prog_offset); @@ -1839,7 +1839,7 @@ genX(upload_wm)(struct brw_context *brw) brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 0); } #elif GFX_VER == 5 - /* On gen5, we have multiple shader kernels but only one GRF start + /* On gfx5, we have multiple shader kernels but only one GRF start * register for all kernels */ wm.KernelStartPointer0 = stage_state->prog_offset + @@ -1856,7 +1856,7 @@ genX(upload_wm)(struct brw_context *brw) wm.DispatchGRFStartRegisterForConstantSetupData0 = wm_prog_data->base.dispatch_grf_start_reg; - /* Dispatch GRF Start should be the same for all shaders on gen5 */ + /* Dispatch GRF Start should be the same for all shaders on gfx5 */ if (brw_wm_state_has_ksp(wm, 1)) { assert(wm_prog_data->base.dispatch_grf_start_reg == brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 1)); @@ -1866,7 +1866,7 @@ genX(upload_wm)(struct brw_context *brw) brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2)); } #elif GFX_VER == 6 - /* On gen6, we have multiple shader kernels and we no longer specify a + /* On gfx6, we have multiple shader kernels and we no longer specify a * register count for each one. */ wm.KernelStartPointer0 = stage_state->prog_offset + @@ -2027,7 +2027,7 @@ genX(upload_wm)(struct brw_context *brw) * seem to have an effect on the HW-assisted coherency mechanism which we * don't need, and the rasterization-related UAV_ONLY flag and the * DISPATCH_ENABLE bit can be set independently from it. - * C.f. gen8_upload_ps_extra(). + * C.f. gfx8_upload_ps_extra(). * * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | * _NEW_COLOR @@ -2156,7 +2156,7 @@ genX(upload_vs_state)(struct brw_context *brw) #endif if (GFX_VER == 7 && devinfo->is_ivybridge) - gen7_emit_vs_workaround_flush(brw); + gfx7_emit_vs_workaround_flush(brw); #if GFX_VER >= 6 brw_batch_emit(brw, GENX(3DSTATE_VS), vs) { @@ -2593,7 +2593,7 @@ genX(upload_gs_state)(struct brw_context *brw) * Stall" bit set. */ if (devinfo->gt == 2 && brw->gs.enabled != active) - gen7_emit_cs_stall_flush(brw); + gfx7_emit_cs_stall_flush(brw); #endif #if GFX_VER >= 6 @@ -2658,10 +2658,10 @@ genX(upload_gs_state)(struct brw_context *brw) gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx); /* GFX6_GS_SPF_MODE and GFX6_GS_VECTOR_MASK_ENABLE are enabled as it - * was previously done for gen6. + * was previously done for gfx6. * * TODO: test with both disabled to see if the HW is behaving - * as expected, like in gen7. + * as expected, like in gfx7. */ gs.SingleProgramFlow = true; gs.VectorMaskEnable = true; @@ -2692,7 +2692,7 @@ genX(upload_gs_state)(struct brw_context *brw) #if GFX_VER <= 6 if (!active && brw->ff_gs.prog_active) { - /* In gen6, transform feedback for the VS stage is done with an + /* In gfx6, transform feedback for the VS stage is done with an * ad-hoc GS program. This function provides the needed 3DSTATE_GS * for this. */ @@ -3094,7 +3094,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw) if (GFX_VERx10 == 70 && !devinfo->is_baytrail && stage_states[MESA_SHADER_VERTEX]->push_constants_dirty) - gen7_emit_vs_workaround_flush(brw); + gfx7_emit_vs_workaround_flush(brw); for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) { struct brw_stage_state *stage_state = stage_states[stage]; @@ -3196,7 +3196,7 @@ genX(upload_vs_push_constants)(struct brw_context *brw) /* BRW_NEW_VS_PROG_DATA */ const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data; - gen6_upload_push_constants(brw, vp, prog_data, stage_state); + gfx6_upload_push_constants(brw, vp, prog_data, stage_state); } static const struct brw_tracked_state genX(vs_push_constants) = { @@ -3222,7 +3222,7 @@ genX(upload_gs_push_constants)(struct brw_context *brw) /* BRW_NEW_GS_PROG_DATA */ struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data; - gen6_upload_push_constants(brw, gp, prog_data, stage_state); + gfx6_upload_push_constants(brw, gp, prog_data, stage_state); } static const struct brw_tracked_state genX(gs_push_constants) = { @@ -3246,7 +3246,7 @@ genX(upload_wm_push_constants)(struct brw_context *brw) /* BRW_NEW_FS_PROG_DATA */ const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data; - gen6_upload_push_constants(brw, fp, prog_data, stage_state); + gfx6_upload_push_constants(brw, fp, prog_data, stage_state); } static const struct brw_tracked_state genX(wm_push_constants) = { @@ -3891,7 +3891,7 @@ genX(upload_ps)(struct brw_context *brw) #endif /* 3DSTATE_PS expects the number of threads per PSD, which is always 64 - * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is + * for pre Gen11 and 128 for gfx11+; On gfx11+ If a programmed value is * k, it implies 2(k+1) threads. It implicitly scales for different GT * levels (which have some # of PSDs). * @@ -4148,7 +4148,7 @@ genX(upload_tes_push_constants)(struct brw_context *brw) /* BRW_NEW_TES_PROG_DATA */ const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data; - gen6_upload_push_constants(brw, tep, prog_data, stage_state); + gfx6_upload_push_constants(brw, tep, prog_data, stage_state); } static const struct brw_tracked_state genX(tes_push_constants) = { @@ -4172,7 +4172,7 @@ genX(upload_tcs_push_constants)(struct brw_context *brw) /* BRW_NEW_TCS_PROG_DATA */ const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data; - gen6_upload_push_constants(brw, tcp, prog_data, stage_state); + gfx6_upload_push_constants(brw, tcp, prog_data, stage_state); } static const struct brw_tracked_state genX(tcs_push_constants) = { @@ -4344,7 +4344,7 @@ genX(upload_cs_state)(struct brw_context *brw) /* We are uploading duplicated copies of push constant uniforms for each * thread. Although the local id data needs to vary per thread, it won't * change for other uniform data. Unfortunately this duplication is - * required for gen7. As of Haswell, this duplication can be avoided, + * required for gfx7. As of Haswell, this duplication can be avoided, * but this older mechanism with duplicated data continues to work. * * FINISHME: As of Haswell, we could make use of the @@ -4927,7 +4927,7 @@ genX(emit_sampler_state_pointers_xs)(UNUSED struct brw_context *brw, /* Ivybridge requires a workaround flush before VS packets. */ if (GFX_VERx10 == 70 && stage_state->stage == MESA_SHADER_VERTEX) { - gen7_emit_vs_workaround_flush(brw); + gfx7_emit_vs_workaround_flush(brw); } brw_batch_emit(brw, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) { @@ -5651,7 +5651,7 @@ genX(init_atoms)(struct brw_context *brw) &genX(cc_vp), - &gen6_urb, + &gfx6_urb, &genX(blend_state), /* must do before cc unit */ &genX(color_calc_state), /* must do before cc unit */ &genX(depth_stencil_state), /* must do before cc unit */ @@ -5669,18 +5669,18 @@ genX(init_atoms)(struct brw_context *brw) &brw_gs_ubo_surfaces, &brw_wm_pull_constants, &brw_wm_ubo_surfaces, - &gen6_renderbuffer_surfaces, + &gfx6_renderbuffer_surfaces, &brw_renderbuffer_read_surfaces, &brw_texture_surfaces, - &gen6_sol_surface, + &gfx6_sol_surface, &brw_vs_binding_table, - &gen6_gs_binding_table, + &gfx6_gs_binding_table, &brw_wm_binding_table, &genX(fs_samplers), &genX(vs_samplers), &genX(gs_samplers), - &gen6_sampler_state, + &gfx6_sampler_state, &genX(multisample_state), &genX(vs_state), @@ -5691,7 +5691,7 @@ genX(init_atoms)(struct brw_context *brw) &genX(scissor_state), - &gen6_binding_table_pointers, + &gfx6_binding_table_pointers, &brw_depthbuffer, @@ -5716,9 +5716,9 @@ genX(init_atoms)(struct brw_context *brw) &genX(cc_vp), &genX(sf_clip_viewport), - &gen7_l3_state, - &gen7_push_constant_space, - &gen7_urb, + &gfx7_l3_state, + &gfx7_push_constant_space, + &gfx7_urb, #if GFX_VERx10 == 75 &genX(cc_and_blend_state), #else @@ -5752,7 +5752,7 @@ genX(init_atoms)(struct brw_context *brw) &brw_gs_ubo_surfaces, &brw_wm_pull_constants, &brw_wm_ubo_surfaces, - &gen6_renderbuffer_surfaces, + &gfx6_renderbuffer_surfaces, &brw_renderbuffer_read_surfaces, &brw_texture_surfaces, @@ -5810,9 +5810,9 @@ genX(init_atoms)(struct brw_context *brw) &genX(cc_vp), &genX(sf_clip_viewport), - &gen7_l3_state, - &gen7_push_constant_space, - &gen7_urb, + &gfx7_l3_state, + &gfx7_push_constant_space, + &gfx7_urb, &genX(blend_state), &genX(color_calc_state), @@ -5841,7 +5841,7 @@ genX(init_atoms)(struct brw_context *brw) &brw_gs_ubo_surfaces, &brw_wm_pull_constants, &brw_wm_ubo_surfaces, - &gen6_renderbuffer_surfaces, + &gfx6_renderbuffer_surfaces, &brw_renderbuffer_read_surfaces, &brw_texture_surfaces, @@ -5894,7 +5894,7 @@ genX(init_atoms)(struct brw_context *brw) &genX(vertices), &genX(cut_index), - &gen8_pma_fix, + &gfx8_pma_fix, }; #endif @@ -5905,7 +5905,7 @@ genX(init_atoms)(struct brw_context *brw) #if GFX_VER >= 7 static const struct brw_tracked_state *compute_atoms[] = { - &gen7_l3_state, + &gfx7_l3_state, &brw_cs_image_surfaces, &genX(cs_push_constants), &genX(cs_pull_constants), diff --git a/src/mesa/drivers/dri/i965/gfx6_constant_state.c b/src/mesa/drivers/dri/i965/gfx6_constant_state.c index 230e14fc8e1..6241502f77a 100644 --- a/src/mesa/drivers/dri/i965/gfx6_constant_state.c +++ b/src/mesa/drivers/dri/i965/gfx6_constant_state.c @@ -114,7 +114,7 @@ brw_populate_constant_data(struct brw_context *brw, /** * Creates a streamed BO containing the push constants for the VS or GS on - * gen6+. + * gfx6+. * * Push constants are constant values (such as GLSL uniforms) that are * pre-loaded into a shader stage's register space at thread spawn time. @@ -125,10 +125,10 @@ brw_populate_constant_data(struct brw_context *brw, * to be usable for the VS. Plus, currently we always use pull constants * instead of push constants when doing variable-index array access. * - * See brw_curbe.c for the equivalent gen4/5 code. + * See brw_curbe.c for the equivalent gfx4/5 code. */ void -gen6_upload_push_constants(struct brw_context *brw, +gfx6_upload_push_constants(struct brw_context *brw, const struct gl_program *prog, const struct brw_stage_prog_data *prog_data, struct brw_stage_state *stage_state) @@ -225,8 +225,8 @@ gen6_upload_push_constants(struct brw_context *brw, * (which is easiest to support using pull constants, and avoids filling * register space with mostly-unused data). * - * Compare this path to brw_curbe.c for gen4/5 push constants, and - * gfx6_vs_state.c for gen6+ push constants. + * Compare this path to brw_curbe.c for gfx4/5 push constants, and + * gfx6_vs_state.c for gfx6+ push constants. */ void brw_upload_pull_constants(struct brw_context *brw, @@ -283,14 +283,14 @@ brw_upload_pull_constants(struct brw_context *brw, } /** - * Creates a region containing the push constants for the CS on gen7+. + * Creates a region containing the push constants for the CS on gfx7+. * * Push constants are constant values (such as GLSL uniforms) that are * pre-loaded into a shader stage's register space at thread spawn time. * * For other stages, see brw_curbe.c:brw_upload_constant_buffer for the - * equivalent gen4/5 code and gfx6_vs_state.c:gen6_upload_push_constants for - * gen6+. + * equivalent gfx4/5 code and gfx6_vs_state.c:gfx6_upload_push_constants for + * gfx6+. */ void brw_upload_cs_push_constants(struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/gfx6_multisample_state.c b/src/mesa/drivers/dri/i965/gfx6_multisample_state.c index df13946643f..b5f2c3b7f89 100644 --- a/src/mesa/drivers/dri/i965/gfx6_multisample_state.c +++ b/src/mesa/drivers/dri/i965/gfx6_multisample_state.c @@ -29,7 +29,7 @@ #include "main/framebuffer.h" void -gen6_get_sample_position(struct gl_context *ctx, +gfx6_get_sample_position(struct gl_context *ctx, struct gl_framebuffer *fb, GLuint index, GLfloat *result) { diff --git a/src/mesa/drivers/dri/i965/gfx6_queryobj.c b/src/mesa/drivers/dri/i965/gfx6_queryobj.c index 6085ffbb4c5..9b403dd4109 100644 --- a/src/mesa/drivers/dri/i965/gfx6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gfx6_queryobj.c @@ -219,7 +219,7 @@ emit_pipeline_stat(struct brw_context *brw, struct brw_bo *bo, * Wait on the query object's BO and calculate the final result. */ static void -gen6_queryobj_get_results(struct gl_context *ctx, +gfx6_queryobj_get_results(struct gl_context *ctx, struct brw_query_object *query) { struct brw_context *brw = brw_context(ctx); @@ -321,7 +321,7 @@ gen6_queryobj_get_results(struct gl_context *ctx, * recording data for the query. */ static void -gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q) +gfx6_begin_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; @@ -410,7 +410,7 @@ gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q) * produce the final result. */ static void -gen6_end_query(struct gl_context *ctx, struct gl_query_object *q) +gfx6_end_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; @@ -495,7 +495,7 @@ flush_batch_if_needed(struct brw_context *brw, struct brw_query_object *query) * Wait for a query result to become available and return it. This is the * backing for glGetQueryObjectiv() with the GL_QUERY_RESULT pname. */ -static void gen6_wait_query(struct gl_context *ctx, struct gl_query_object *q) +static void gfx6_wait_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; @@ -506,7 +506,7 @@ static void gen6_wait_query(struct gl_context *ctx, struct gl_query_object *q) */ flush_batch_if_needed(brw, query); - gen6_queryobj_get_results(ctx, query); + gfx6_queryobj_get_results(ctx, query); } /** @@ -515,7 +515,7 @@ static void gen6_wait_query(struct gl_context *ctx, struct gl_query_object *q) * Checks whether a query result is ready yet. If not, flushes. * This is the backing for glGetQueryObjectiv()'s QUERY_RESULT_AVAILABLE pname. */ -static void gen6_check_query(struct gl_context *ctx, struct gl_query_object *q) +static void gfx6_check_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; @@ -536,12 +536,12 @@ static void gen6_check_query(struct gl_context *ctx, struct gl_query_object *q) flush_batch_if_needed(brw, query); if (!brw_bo_busy(query->bo)) { - gen6_queryobj_get_results(ctx, query); + gfx6_queryobj_get_results(ctx, query); } } static void -gen6_query_counter(struct gl_context *ctx, struct gl_query_object *q) +gfx6_query_counter(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; @@ -550,11 +550,11 @@ gen6_query_counter(struct gl_context *ctx, struct gl_query_object *q) } /* Initialize Gen6+-specific query object functions. */ -void gen6_init_queryobj_functions(struct dd_function_table *functions) +void gfx6_init_queryobj_functions(struct dd_function_table *functions) { - functions->BeginQuery = gen6_begin_query; - functions->EndQuery = gen6_end_query; - functions->CheckQuery = gen6_check_query; - functions->WaitQuery = gen6_wait_query; - functions->QueryCounter = gen6_query_counter; + functions->BeginQuery = gfx6_begin_query; + functions->EndQuery = gfx6_end_query; + functions->CheckQuery = gfx6_check_query; + functions->WaitQuery = gfx6_wait_query; + functions->QueryCounter = gfx6_query_counter; } diff --git a/src/mesa/drivers/dri/i965/gfx6_sampler_state.c b/src/mesa/drivers/dri/i965/gfx6_sampler_state.c index f7b47a2f034..4a5481fe24b 100644 --- a/src/mesa/drivers/dri/i965/gfx6_sampler_state.c +++ b/src/mesa/drivers/dri/i965/gfx6_sampler_state.c @@ -45,7 +45,7 @@ upload_sampler_state_pointers(struct brw_context *brw) ADVANCE_BATCH(); } -const struct brw_tracked_state gen6_sampler_state = { +const struct brw_tracked_state gfx6_sampler_state = { .dirty = { .mesa = 0, .brw = BRW_NEW_BATCH | diff --git a/src/mesa/drivers/dri/i965/gfx6_sol.c b/src/mesa/drivers/dri/i965/gfx6_sol.c index cdfb5686e31..21849b082ee 100644 --- a/src/mesa/drivers/dri/i965/gfx6_sol.c +++ b/src/mesa/drivers/dri/i965/gfx6_sol.c @@ -36,7 +36,7 @@ #include "util/u_memory.h" static void -gen6_update_sol_surfaces(struct brw_context *brw) +gfx6_update_sol_surfaces(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; bool xfb_active = _mesa_is_xfb_active_and_unpaused(ctx); @@ -80,14 +80,14 @@ gen6_update_sol_surfaces(struct brw_context *brw) brw->ctx.NewDriverState |= BRW_NEW_SURFACES; } -const struct brw_tracked_state gen6_sol_surface = { +const struct brw_tracked_state gfx6_sol_surface = { .dirty = { .mesa = 0, .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | BRW_NEW_TRANSFORM_FEEDBACK, }, - .emit = gen6_update_sol_surfaces, + .emit = gfx6_update_sol_surfaces, }; /** @@ -172,7 +172,7 @@ brw_gs_upload_binding_table(struct brw_context *brw) brw->ctx.NewDriverState |= BRW_NEW_BINDING_TABLE_POINTERS; } -const struct brw_tracked_state gen6_gs_binding_table = { +const struct brw_tracked_state gfx6_gs_binding_table = { .dirty = { .mesa = 0, .brw = BRW_NEW_BATCH | diff --git a/src/mesa/drivers/dri/i965/gfx6_urb.c b/src/mesa/drivers/dri/i965/gfx6_urb.c index 2514e0c5f13..89106619edf 100644 --- a/src/mesa/drivers/dri/i965/gfx6_urb.c +++ b/src/mesa/drivers/dri/i965/gfx6_urb.c @@ -47,7 +47,7 @@ * (See the Sandybridge PRM, Volume 2, Part 1, Section 1.4.7: 3DSTATE_URB.) */ void -gen6_upload_urb(struct brw_context *brw, unsigned vs_size, +gfx6_upload_urb(struct brw_context *brw, unsigned vs_size, bool gs_present, unsigned gs_size) { int nr_vs_entries, nr_gs_entries; @@ -136,10 +136,10 @@ upload_urb(struct brw_context *brw) assert(gs_size >= 1); } - gen6_upload_urb(brw, vs_size, gs_present, gs_size); + gfx6_upload_urb(brw, vs_size, gs_present, gs_size); } -const struct brw_tracked_state gen6_urb = { +const struct brw_tracked_state gfx6_urb = { .dirty = { .mesa = 0, .brw = BRW_NEW_BLORP | diff --git a/src/mesa/drivers/dri/i965/gfx7_l3_state.c b/src/mesa/drivers/dri/i965/gfx7_l3_state.c index a707f0a76e7..f9992fb392e 100644 --- a/src/mesa/drivers/dri/i965/gfx7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gfx7_l3_state.c @@ -202,7 +202,7 @@ update_urb_size(struct brw_context *brw, const struct intel_l3_config *cfg) brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE; /* If we change the total URB size, reset the individual stage sizes to - * zero so that, even if there is no URB size change, gen7_upload_urb + * zero so that, even if there is no URB size change, gfx7_upload_urb * still re-emits 3DSTATE_URB_*. */ brw->urb.vsize = 0; @@ -249,7 +249,7 @@ brw_emit_l3_state(struct brw_context *brw) } } -const struct brw_tracked_state gen7_l3_state = { +const struct brw_tracked_state gfx7_l3_state = { .dirty = { .mesa = 0, .brw = BRW_NEW_BATCH | @@ -298,7 +298,7 @@ const struct brw_tracked_state gen7_l3_state = { * be reproduced easily on IVB in our CI system. */ void -gen7_restore_default_l3_config(struct brw_context *brw) +gfx7_restore_default_l3_config(struct brw_context *brw) { const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct intel_l3_config *const cfg = intel_get_default_l3_config(devinfo); diff --git a/src/mesa/drivers/dri/i965/gfx7_sol_state.c b/src/mesa/drivers/dri/i965/gfx7_sol_state.c index d33a3a1bbab..d1a2e5be018 100644 --- a/src/mesa/drivers/dri/i965/gfx7_sol_state.c +++ b/src/mesa/drivers/dri/i965/gfx7_sol_state.c @@ -24,7 +24,7 @@ /** * @file gfx7_sol_state.c * - * Controls the stream output logic (SOL) stage of the gen7 hardware, which is + * Controls the stream output logic (SOL) stage of the gfx7 hardware, which is * used to implement GL_EXT_transform_feedback. */ @@ -36,7 +36,7 @@ #include "main/transformfeedback.h" void -gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, +gfx7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, struct gl_transform_feedback_object *obj) { struct brw_context *brw = brw_context(ctx); @@ -62,7 +62,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, } void -gen7_end_transform_feedback(struct gl_context *ctx, +gfx7_end_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj) { /* After EndTransformFeedback, it's likely that the client program will try @@ -96,7 +96,7 @@ gen7_end_transform_feedback(struct gl_context *ctx, } void -gen7_pause_transform_feedback(struct gl_context *ctx, +gfx7_pause_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj) { struct brw_context *brw = brw_context(ctx); @@ -126,7 +126,7 @@ gen7_pause_transform_feedback(struct gl_context *ctx, } void -gen7_resume_transform_feedback(struct gl_context *ctx, +gfx7_resume_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj) { struct brw_context *brw = brw_context(ctx); diff --git a/src/mesa/drivers/dri/i965/gfx7_urb.c b/src/mesa/drivers/dri/i965/gfx7_urb.c index 487b44634ad..1f1757487f0 100644 --- a/src/mesa/drivers/dri/i965/gfx7_urb.c +++ b/src/mesa/drivers/dri/i965/gfx7_urb.c @@ -60,7 +60,7 @@ * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS. */ static void -gen7_allocate_push_constants(struct brw_context *brw) +gfx7_allocate_push_constants(struct brw_context *brw) { const struct gen_device_info *devinfo = &brw->screen->devinfo; @@ -88,7 +88,7 @@ gen7_allocate_push_constants(struct brw_context *brw) unsigned gs_size = gs_present ? size_per_stage : 0; unsigned fs_size = avail_size - size_per_stage * (stages - 1); - gen7_emit_push_constant_state(brw, multiplier * vs_size, + gfx7_emit_push_constant_state(brw, multiplier * vs_size, multiplier * hs_size, multiplier * ds_size, multiplier * gs_size, multiplier * fs_size); @@ -111,7 +111,7 @@ gen7_allocate_push_constants(struct brw_context *brw) } void -gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, +gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, unsigned hs_size, unsigned ds_size, unsigned gs_size, unsigned fs_size) { @@ -174,10 +174,10 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, * No such restriction exists for Haswell or Baytrail. */ if (devinfo->ver < 8 && !devinfo->is_haswell && !devinfo->is_baytrail) - gen7_emit_cs_stall_flush(brw); + gfx7_emit_cs_stall_flush(brw); } -const struct brw_tracked_state gen7_push_constant_space = { +const struct brw_tracked_state gfx7_push_constant_space = { .dirty = { .mesa = 0, .brw = BRW_NEW_CONTEXT | @@ -185,7 +185,7 @@ const struct brw_tracked_state gen7_push_constant_space = { BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TESS_PROGRAMS, }, - .emit = gen7_allocate_push_constants, + .emit = gfx7_allocate_push_constants, }; static void @@ -200,11 +200,11 @@ upload_urb(struct brw_context *brw) /* BRW_NEW_TES_PROG_DATA */ const bool tess_present = brw->tes.base.prog_data; - gen7_upload_urb(brw, vs_size, gs_present, tess_present); + gfx7_upload_urb(brw, vs_size, gs_present, tess_present); } void -gen7_upload_urb(struct brw_context *brw, unsigned vs_size, +gfx7_upload_urb(struct brw_context *brw, unsigned vs_size, bool gs_present, bool tess_present) { const struct gen_device_info *devinfo = &brw->screen->devinfo; @@ -253,7 +253,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, entries, start, NULL, &constrained); if (devinfo->ver == 7 && !devinfo->is_haswell && !devinfo->is_baytrail) - gen7_emit_vs_workaround_flush(brw); + gfx7_emit_vs_workaround_flush(brw); BEGIN_BATCH(8); for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { @@ -266,7 +266,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, ADVANCE_BATCH(); } -const struct brw_tracked_state gen7_urb = { +const struct brw_tracked_state gfx7_urb = { .dirty = { .mesa = 0, .brw = BRW_NEW_BLORP | diff --git a/src/mesa/drivers/dri/i965/gfx8_depth_state.c b/src/mesa/drivers/dri/i965/gfx8_depth_state.c index 1c2dcd488c0..be54a858561 100644 --- a/src/mesa/drivers/dri/i965/gfx8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gfx8_depth_state.c @@ -130,7 +130,7 @@ pma_fix_enable(const struct brw_context *brw) } void -gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits) +gfx8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits) { /* If we haven't actually changed the value, bail now to avoid unnecessary * pipeline stalls and register writes. @@ -169,7 +169,7 @@ gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits) } static void -gen8_emit_pma_stall_workaround(struct brw_context *brw) +gfx8_emit_pma_stall_workaround(struct brw_context *brw) { const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t bits = 0; @@ -180,10 +180,10 @@ gen8_emit_pma_stall_workaround(struct brw_context *brw) if (pma_fix_enable(brw)) bits |= GFX8_HIZ_NP_PMA_FIX_ENABLE | GFX8_HIZ_NP_EARLY_Z_FAILS_DISABLE; - gen8_write_pma_stall_bits(brw, bits); + gfx8_write_pma_stall_bits(brw, bits); } -const struct brw_tracked_state gen8_pma_fix = { +const struct brw_tracked_state gfx8_pma_fix = { .dirty = { .mesa = _NEW_BUFFERS | _NEW_COLOR | @@ -193,5 +193,5 @@ const struct brw_tracked_state gen8_pma_fix = { .brw = BRW_NEW_BLORP | BRW_NEW_FS_PROG_DATA, }, - .emit = gen8_emit_pma_stall_workaround + .emit = gfx8_emit_pma_stall_workaround }; diff --git a/src/mesa/drivers/dri/i965/gfx8_multisample_state.c b/src/mesa/drivers/dri/i965/gfx8_multisample_state.c index 04a68758837..572446370e0 100644 --- a/src/mesa/drivers/dri/i965/gfx8_multisample_state.c +++ b/src/mesa/drivers/dri/i965/gfx8_multisample_state.c @@ -31,7 +31,7 @@ * 3DSTATE_SAMPLE_PATTERN */ void -gen8_emit_3dstate_sample_pattern(struct brw_context *brw) +gfx8_emit_3dstate_sample_pattern(struct brw_context *brw) { BEGIN_BATCH(9); OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2)); diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c index 7159ded1acf..f53f93c06bf 100644 --- a/src/mesa/drivers/dri/i965/hsw_queryobj.c +++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c @@ -481,6 +481,6 @@ hsw_store_query_result(struct gl_context *ctx, struct gl_query_object *q, /* Initialize hsw+-specific query object functions. */ void hsw_init_queryobj_functions(struct dd_function_table *functions) { - gen6_init_queryobj_functions(functions); + gfx6_init_queryobj_functions(functions); functions->StoreQueryResult = hsw_store_query_result; }