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brw: get rid of GET_BUFFER_SIZE opcode

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Rely on RESINFO which is what was used already.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37171>
This commit is contained in:
Lionel Landwerlin 2025-10-10 15:17:24 +03:00 • committed by Marge Bot
parent b101d100fb
commit b722e17203
9 changed files with 19 additions and 86 deletions
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5
src/intel/compiler/brw/brw_analysis_performance.cpp
View file

@ -585,11 +585,6 @@ namespace {
0, 2 /* XXX */,
0, 0, 0, 8 /* XXX */, 0, 0);
case SHADER_OPCODE_GET_BUFFER_SIZE:
return calculate_desc(info, EU_UNIT_SAMPLER, 2, 0, 0, 0, 16 /* XXX */,
8 /* XXX */, 750 /* XXX */, 0, 0,
2 /* XXX */, 0);
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return calculate_desc(info, EU_UNIT_DP_CC, 2, 0, 0, 0, 16 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);

13
src/intel/compiler/brw/brw_eu_defines.h
View file

@ -471,8 +471,6 @@ enum ENUM_PACKED opcode {
*/
SHADER_OPCODE_CLUSTER_BROADCAST,
SHADER_OPCODE_GET_BUFFER_SIZE,
SHADER_OPCODE_INTERLOCK,
/** Target for a HALT
@ -631,17 +629,6 @@ enum pull_varying_constant_srcs {
PULL_VARYING_CONSTANT_SRCS,
};
enum get_buffer_size_srcs {
/** Surface binding table index */
GET_BUFFER_SIZE_SRC_SURFACE,
/** Surface bindless handle */
GET_BUFFER_SIZE_SRC_SURFACE_HANDLE,
/** LOD */
GET_BUFFER_SIZE_SRC_LOD,
GET_BUFFER_SIZE_SRCS
};
enum ENUM_PACKED memory_logical_mode {
MEMORY_MODE_TYPED,
MEMORY_MODE_UNTYPED,

32
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -6439,23 +6439,27 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
* the dispatch width.
*/
const brw_builder ubld = bld.scalar_group();
brw_reg ret_payload = ubld.vgrf(BRW_TYPE_UD, 4);
/* Set LOD = 0 */
brw_reg src_payload = ubld.MOV(brw_imm_ud(0));
brw_reg srcs[TEX_LOGICAL_NUM_SRCS];
srcs[TEX_LOGICAL_SRC_SURFACE] = get_nir_buffer_intrinsic_index(ntb, bld, instr);
srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_d(0);
srcs[TEX_LOGICAL_SRC_PAYLOAD0] = brw_imm_d(0); /* LOD (required) */
brw_reg srcs[GET_BUFFER_SIZE_SRCS];
srcs[get_nir_src_bindless(ntb, instr->src[0]) ?
GET_BUFFER_SIZE_SRC_SURFACE_HANDLE :
GET_BUFFER_SIZE_SRC_SURFACE] =
get_nir_buffer_intrinsic_index(ntb, bld, instr);
srcs[GET_BUFFER_SIZE_SRC_LOD] = src_payload;
brw_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload,
srcs, GET_BUFFER_SIZE_SRCS);
brw_reg tmp = ubld.vgrf(BRW_TYPE_UD, 4);
brw_tex_inst *inst = ubld.emit(SHADER_OPCODE_SAMPLER,
tmp, srcs, 3)->as_tex();
inst->required_params = 0x1 /* LOD */;
inst->sampler_opcode = BRW_SAMPLER_OPCODE_RESINFO;
inst->surface_bindless = get_nir_src_bindless(ntb, instr->src[0]);
inst->size_written = 4 * REG_SIZE * reg_unit(devinfo);
inst->fused_eu_disable =
(nir_intrinsic_access(instr) & ACCESS_FUSED_EU_DISABLE_INTEL) != 0;
for (unsigned c = 0; c < instr->def.num_components; ++c) {
bld.MOV(offset(retype(dest, tmp.type), bld, c),
component(offset(tmp, ubld, c), 0));
}
/* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
*
* "Out-of-bounds checking is always performed at a DWord granularity. If
@ -6475,11 +6479,11 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
*
* buffer_size = surface_size & ~3 - surface_size & 3
*/
brw_reg size_padding = ubld.AND(ret_payload, brw_imm_ud(3));
brw_reg size_aligned4 = ubld.AND(ret_payload, brw_imm_ud(~3));
brw_reg size_padding = ubld.AND(tmp, brw_imm_ud(3));
brw_reg size_aligned4 = ubld.AND(tmp, brw_imm_ud(~3));
brw_reg buffer_size = ubld.ADD(size_aligned4, negate(size_padding));
bld.MOV(retype(dest, ret_payload.type), component(buffer_size, 0));
bld.MOV(retype(dest, tmp.type), component(buffer_size, 0));
break;
}

1
src/intel/compiler/brw/brw_inst.cpp
View file

@ -221,7 +221,6 @@ brw_inst_kind_for_opcode(enum opcode opcode)
case FS_OPCODE_FB_WRITE_LOGICAL:
return BRW_KIND_FB_WRITE;
case SHADER_OPCODE_GET_BUFFER_SIZE:
case FS_OPCODE_FB_READ_LOGICAL:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:

7
src/intel/compiler/brw/brw_inst.h
View file

@ -213,12 +213,7 @@ struct brw_inst : brw_exec_node {
*/
bool has_no_mask_send_params:1;
/**
* Serialize the message (Gfx12.x only)
*/
bool fused_eu_disable:1;
uint8_t pad:5;
uint8_t pad:6;
};
uint16_t bits;
};

42
src/intel/compiler/brw/brw_lower_logical_sends.cpp
View file

@ -2146,44 +2146,6 @@ lower_trace_ray_logical_send(const brw_builder &bld, brw_inst *inst)
send->src[SEND_SRC_PAYLOAD2] = payload;
}
static void
lower_get_buffer_size(const brw_builder &bld, brw_inst *inst)
{
const intel_device_info *devinfo = bld.shader->devinfo;
/* Since we can only execute this instruction on uniform bti/surface
* handles, brw_from_nir.cpp should already have limited this to SIMD8.
*/
assert(inst->exec_size == (devinfo->ver < 20 ? 8 : 16));
brw_reg surface = inst->src[GET_BUFFER_SIZE_SRC_SURFACE];
brw_reg surface_handle = inst->src[GET_BUFFER_SIZE_SRC_SURFACE_HANDLE];
brw_reg lod = bld.move_to_vgrf(inst->src[GET_BUFFER_SIZE_SRC_LOD], 1);
const bool fused_eu_disable = inst->fused_eu_disable;
brw_send_inst *send = brw_transform_inst_to_send(bld, inst);
inst = NULL;
send->mlen = send->exec_size / 8;
send->ex_mlen = 0;
send->ex_desc = 0;
/* src[SEND_SRC_DESC/EX_DESC] are filled by setup_surface_descriptors() */
send->src[SEND_SRC_PAYLOAD1] = lod;
send->src[SEND_SRC_PAYLOAD2] = brw_reg();
const uint32_t return_format = GFX8_SAMPLER_RETURN_FORMAT_32BITS;
const uint32_t desc = brw_sampler_desc(devinfo, 0, 0,
GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
BRW_SAMPLER_SIMD_MODE_SIMD8,
return_format);
send->dst = retype(send->dst, BRW_TYPE_UW);
send->sfid = BRW_SFID_SAMPLER;
send->fused_eu_disable = fused_eu_disable;
setup_surface_descriptors(bld, send, desc, surface, surface_handle);
}
static void
lower_lsc_memory_fence_and_interlock(const brw_builder &bld, struct brw_send_inst *inst)
{
@ -2329,10 +2291,6 @@ brw_lower_logical_sends(brw_shader &s)
lower_sampler_logical_send(ibld, inst->as_tex());
break;
case SHADER_OPCODE_GET_BUFFER_SIZE:
lower_get_buffer_size(ibld, inst);
break;
case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL: {

1
src/intel/compiler/brw/brw_opt_cse.cpp
View file

@ -94,7 +94,6 @@ is_expression(const brw_shader *v, const brw_inst *const inst)
case SHADER_OPCODE_CLUSTER_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
case SHADER_OPCODE_SAMPLER:
case SHADER_OPCODE_GET_BUFFER_SIZE:
case FS_OPCODE_PACK:
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
case SHADER_OPCODE_RCP:

3
src/intel/compiler/brw/brw_print.cpp
View file

@ -175,9 +175,6 @@ brw_instruction_name(const struct brw_isa_info *isa, const brw_inst *inst)
case SHADER_OPCODE_CLUSTER_BROADCAST:
return "cluster_broadcast";
case SHADER_OPCODE_GET_BUFFER_SIZE:
return "get_buffer_size";
case FS_OPCODE_DDX_COARSE:
return "ddx_coarse";
case FS_OPCODE_DDX_FINE:

1
src/intel/compiler/brw/brw_validate.cpp
View file

@ -201,7 +201,6 @@ brw_validate_instruction_phase(const brw_shader &s, brw_inst *inst)
case FS_OPCODE_FB_WRITE_LOGICAL:
case FS_OPCODE_FB_READ_LOGICAL:
case SHADER_OPCODE_SAMPLER:
case SHADER_OPCODE_GET_BUFFER_SIZE:
case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL: