From b717872e0852fc922da70fa12ce1a462792dbe19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= Date: Mon, 12 Jul 2021 13:43:03 +0200 Subject: [PATCH] intel/compiler: Get mesh_global_addr from the Inline Parameter for Task/Mesh MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marcin Ślusarz Reviewed-by: Lionel Landwerlin Part-of: --- src/compiler/nir/nir_intrinsics.py | 3 ++ src/compiler/nir/nir_lower_shader_calls.c | 1 + src/intel/compiler/brw_mesh.cpp | 43 +++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 457ccbd3f57..bf82670259e 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1320,6 +1320,9 @@ store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET] # src[] = { value, offset }. store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) +# Intrinsics for Intel mesh shading +system_value("mesh_global_arg_addr_intel", 1, bit_sizes=[64]) + # Intrinsics for Intel bindless thread dispatch system_value("btd_dss_id_intel", 1) system_value("btd_stack_id_intel", 1) diff --git a/src/compiler/nir/nir_lower_shader_calls.c b/src/compiler/nir/nir_lower_shader_calls.c index 40e8d621b97..0a37ccc94fd 100644 --- a/src/compiler/nir/nir_lower_shader_calls.c +++ b/src/compiler/nir/nir_lower_shader_calls.c @@ -176,6 +176,7 @@ can_remat_instr(nir_instr *instr, struct brw_bitset *remat) case nir_intrinsic_load_ray_miss_sbt_stride_intel: case nir_intrinsic_load_callable_sbt_addr_intel: case nir_intrinsic_load_callable_sbt_stride_intel: + case nir_intrinsic_load_mesh_global_arg_addr_intel: /* Notably missing from the above list is btd_local_arg_addr_intel. * This is because the resume shader will have a different local * argument pointer because it has a different BSR. Any access of diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index f06e5dde884..b1b79dcc040 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -30,6 +30,37 @@ using namespace brw; +static bool +brw_nir_lower_load_uniforms_filter(const nir_instr *instr, + UNUSED const void *data) +{ + if (instr->type != nir_instr_type_intrinsic) + return false; + nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + return intrin->intrinsic == nir_intrinsic_load_uniform; +} + +static nir_ssa_def * +brw_nir_lower_load_uniforms_impl(nir_builder *b, nir_instr *instr, + UNUSED void *data) +{ + assert(instr->type == nir_instr_type_intrinsic); + nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + assert(intrin->intrinsic == nir_intrinsic_load_uniform); + + return brw_nir_load_global_const(b, + intrin, + nir_load_mesh_global_arg_addr_intel(b), + 0); +} + +static void +brw_nir_lower_load_uniforms(nir_shader *nir) +{ + nir_shader_lower_instructions(nir, brw_nir_lower_load_uniforms_filter, + brw_nir_lower_load_uniforms_impl, NULL); +} + static inline int type_size_scalar_dwords(const struct glsl_type *type, bool bindless) { @@ -150,6 +181,7 @@ brw_compile_task(const struct brw_compiler *compiler, brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */); NIR_PASS_V(shader, brw_nir_lower_tue_outputs, &prog_data->map); + NIR_PASS_V(shader, brw_nir_lower_load_uniforms); NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width); brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled, @@ -522,6 +554,11 @@ brw_compile_mesh(const struct brw_compiler *compiler, NIR_PASS_V(shader, brw_nir_lower_tue_inputs, params->tue_map); NIR_PASS_V(shader, brw_nir_lower_mue_outputs, &prog_data->map); NIR_PASS_V(shader, brw_nir_adjust_offset_for_arrayed_indices, &prog_data->map); + + /* Load uniforms can do a better job for constants, so fold before it. */ + NIR_PASS_V(shader, nir_opt_constant_folding); + NIR_PASS_V(shader, brw_nir_lower_load_uniforms); + NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width); brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled, @@ -937,6 +974,12 @@ fs_visitor::nir_emit_task_mesh_intrinsic(const fs_builder &bld, dest = get_nir_dest(instr->dest); switch (instr->intrinsic) { + case nir_intrinsic_load_mesh_global_arg_addr_intel: + assert(payload.num_regs == 3 || payload.num_regs == 4); + /* Passed in the Inline Parameter, the last element of the payload. */ + bld.MOV(dest, retype(brw_vec1_grf(payload.num_regs - 1, 0), dest.type)); + break; + case nir_intrinsic_load_local_invocation_index: case nir_intrinsic_load_local_invocation_id: /* Local_ID.X is given by the HW in the shader payload. */