diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index 0eb4348286d..614163debec 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -880,11 +880,11 @@ build_addr_for_var(nir_builder *b, nir_variable *var,
       nir_ssa_def *base_addr;
       switch (var->data.mode) {
       case nir_var_shader_temp:
-         base_addr = nir_load_scratch_base_ptr(b, 0, num_comps, bit_size);
+         base_addr = nir_load_scratch_base_ptr(b, num_comps, bit_size, 0);
          break;
 
       case nir_var_function_temp:
-         base_addr = nir_load_scratch_base_ptr(b, 1, num_comps, bit_size);
+         base_addr = nir_load_scratch_base_ptr(b, num_comps, bit_size, 1);
          break;
 
       case nir_var_mem_constant:
diff --git a/src/intel/compiler/brw_nir_rt_builder.h b/src/intel/compiler/brw_nir_rt_builder.h
index dd53027fe03..2b4c545c819 100644
--- a/src/intel/compiler/brw_nir_rt_builder.h
+++ b/src/intel/compiler/brw_nir_rt_builder.h
@@ -36,7 +36,7 @@ brw_nir_rt_load_scratch(nir_builder *b, uint32_t offset, unsigned align,
                         unsigned num_components, unsigned bit_size)
 {
    nir_ssa_def *addr =
-      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 1, 64), offset);
+      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 64, 1), offset);
    return nir_load_global(b, addr, MIN2(align, BRW_BTD_STACK_ALIGN),
                           num_components, bit_size);
 }
@@ -46,7 +46,7 @@ brw_nir_rt_store_scratch(nir_builder *b, uint32_t offset, unsigned align,
                          nir_ssa_def *value, nir_component_mask_t write_mask)
 {
    nir_ssa_def *addr =
-      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 1, 64), offset);
+      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 64, 1), offset);
    nir_store_global(b, addr, MIN2(align, BRW_BTD_STACK_ALIGN),
                     value, write_mask);
 }