fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-21 12:00:41 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

tu: Rename RB_MSAA_CNTL to RB_BLIT_GMEM_MSAA_CNTL

Browse source 
Based on experiments and what the blob does, this actually controls the
number of samples in GMEM for CP_EVENT_WRITE::BLIT. Rename it
accordingly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
This commit is contained in:
Connor Abbott 2022-09-07 17:31:21 +02:00 • committed by Marge Bot
parent 8c07e34f7b
commit b6ef9e1f99
8 changed files with 22 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -5861,7 +5861,7 @@ clusters:
00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_BLIT_BASE_GMEM: 0
00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT }
00000000 RB_BLIT_DST: 0
@ -6059,7 +6059,7 @@ clusters:
00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 RB_BLIT_BASE_GMEM: 0
00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT }
00000000 RB_BLIT_DST: 0

18
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -456,8 +456,8 @@ t4 write RB_BLIT_SCISSOR_TL (88d1)
RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
000000000115e00c: 0000: 4888d102 00000000 00ff00ff
t4 write RB_MSAA_CNTL (88d5)
RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
t4 write RB_BLIT_GMEM_MSAA_CNTL (88d5)
RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
000000000115e018: 0000: 4088d501 00000000
t4 write RB_BLIT_INFO (88e3)
RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
@ -493,7 +493,7 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
!+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
!+ 00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
+ 00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 01013000 RB_BLIT_DST: 0x1013000
@ -574,8 +574,8 @@ t4 write RB_RAS_MSAA_CNTL (8802)
RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
000000000115e11c: 0000: 40880202 00000000 00000004
t4 write RB_MSAA_CNTL (88d5)
RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
t4 write RB_BLIT_GMEM_MSAA_CNTL (88d5)
RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
000000000115e128: 0000: 4088d501 00000000
t7 opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
@ -1390,7 +1390,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ 3f800000 RB_Z_CLAMP_MAX: 1.000000
+ 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
!+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
@ -1555,8 +1555,8 @@ t4 write RB_BLIT_SCISSOR_TL (88d1)
RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
000000000115c020: 0000: 4888d102 00000000 00ff00ff
t4 write RB_MSAA_CNTL (88d5)
RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
t4 write RB_BLIT_GMEM_MSAA_CNTL (88d5)
RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
000000000115c02c: 0000: 4088d501 00000000
t4 write RB_BLIT_INFO (88e3)
RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
@ -1583,7 +1583,7 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
draw[3] register values
+ 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_BLIT_BASE_GMEM: 0
+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
+ 01013000 RB_BLIT_DST: 0x1013000

6
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -311,8 +311,8 @@ t4 write RB_RAS_MSAA_CNTL (8802)
RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
0000000001d9133c: 0000: 40880202 00000000 00000004
t4 write RB_MSAA_CNTL (88d5)
RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
t4 write RB_BLIT_GMEM_MSAA_CNTL (88d5)
RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
0000000001d91348: 0000: 4088d501 00000000
t4 write VPC_SO_DISABLE (9306)
VPC_SO_DISABLE: { 0 }
@ -1016,7 +1016,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
+ 00000000 RB_LRZ_CNTL: { 0 }
!+ 00001e11 RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_UNKNOWN_88F0: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0

4
src/freedreno/decode/scripts/parse-submits.lua
View file

@ -359,7 +359,7 @@ function draw(primtype, nindx)
push_mrt(r.RB_MRT[n].BUF_INFO.COLOR_FORMAT,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.X + 1,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_MSAA_CNTL.SAMPLES,
r.RB_BLIT_GMEM_MSAA_CNTL.SAMPLES,
r.RB_MRT[n].BASE,
r.RB_MRT_FLAG_BUFFER[n].ADDR,
r.RB_MRT[n].BASE_GMEM)
@ -372,7 +372,7 @@ function draw(primtype, nindx)
push_mrt(r.RB_DEPTH_BUFFER_INFO.DEPTH_FORMAT,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.X + 1,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_MSAA_CNTL.SAMPLES,
r.RB_BLIT_GMEM_MSAA_CNTL.SAMPLES,
depthbase,
r.RB_DEPTH_FLAG_BUFFER_BASE,
r.RB_DEPTH_BUFFER_BASE_GMEM)

2
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2196,7 +2196,7 @@ to upconvert to 32b float internally?
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
</reg32>
<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
<reg32 offset="0x88d5" name="RB_MSAA_CNTL">
<reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL">
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
</reg32>
<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>

4
src/freedreno/vulkan/tu_clear_blit.c
View file

@ -2944,7 +2944,7 @@ tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
if (!attachment->clear_mask)
return;
tu_cs_emit_regs(cs, A6XX_RB_MSAA_CNTL(tu_msaa_samples(attachment->samples)));
tu_cs_emit_regs(cs, A6XX_RB_BLIT_GMEM_MSAA_CNTL(tu_msaa_samples(attachment->samples)));
tu_emit_clear_gmem_attachment(cmd, cs, a, attachment->clear_mask, value);
}
@ -2958,7 +2958,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
bool separate_stencil)
{
tu_cs_emit_regs(cs,
A6XX_RB_MSAA_CNTL(tu_msaa_samples(attachment->samples)));
A6XX_RB_BLIT_GMEM_MSAA_CNTL(tu_msaa_samples(attachment->samples)));
tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(
.unk0 = !resolve,

2
src/freedreno/vulkan/tu_cmd_buffer.c
View file

@ -346,7 +346,7 @@ tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples,
.msaa_disable = msaa_disable));
tu_cs_emit_regs(cs,
A6XX_RB_MSAA_CNTL(samples));
A6XX_RB_BLIT_GMEM_MSAA_CNTL(samples));
}
static void

4
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -789,8 +789,8 @@ emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL, 1);
OUT_RING(ring, A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(samples));
}
static void prepare_tile_setup_ib(struct fd_batch *batch);