From b6c7da98bec9eadbabc35e44ce0fb8085d429fcf Mon Sep 17 00:00:00 2001 From: Italo Nicola Date: Fri, 19 Mar 2021 11:31:45 +0000 Subject: [PATCH] pan/mdg: encode/decode expand_mode properly Signed-off-by: Italo Nicola Reviewed-by: Alyssa Rosenzweig Part-of: --- src/panfrost/midgard/disassemble.c | 76 +++++++++++++++++++++-------- src/panfrost/midgard/midgard.h | 8 +-- src/panfrost/midgard/midgard_emit.c | 41 ++++++++-------- 3 files changed, 75 insertions(+), 50 deletions(-) diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c index e33b2d4373f..e6996eaa0e7 100644 --- a/src/panfrost/midgard/disassemble.c +++ b/src/panfrost/midgard/disassemble.c @@ -366,7 +366,8 @@ print_vector_constants(FILE *fp, unsigned src_binary, midgard_vector_alu *alu) { midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary; - unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half); + bool expands = INPUT_EXPANDS(src->expand_mode); + unsigned bits = bits_for_mode_halved(alu->reg_mode, expands); unsigned max_comp = (sizeof(*consts) * 8) / bits; unsigned comp_mask, num_comp = 0; @@ -384,29 +385,58 @@ print_vector_constants(FILE *fp, unsigned src_binary, unsigned c = (src->swizzle >> (i * 2)) & 3; - if (bits == 16 && !src->half) { - if (i < 4) - c += (src->rep_high * 4); - else - c += (!src->rep_low * 4); - } else if (bits == 32 && !src->half) { + if (bits == 16 && !expands) { + bool upper = i >= 4; + + switch (src->expand_mode) { + case midgard_src_passthrough: + c += upper * 4; + break; + case midgard_src_rep_low: + break; + case midgard_src_rep_high: + c += 4; + break; + case midgard_src_swap: + c += !upper * 4; + break; + default: + unreachable("invalid expand mode"); + break; + } + } else if (bits == 32 && !expands) { /* Implicitly ok */ - } else if (bits == 8) { - assert (!src->half); + } else if (bits == 64 && !expands) { + /* Implicitly ok */ + } else if (bits == 8 && !expands) { + bool upper = i >= 8; + unsigned index = (i >> 1) & 3; unsigned base = (src->swizzle >> (index * 2)) & 3; c = base * 2; - if (i < 8) - c += (src->rep_high) * 8; - else - c += (!src->rep_low) * 8; + switch (src->expand_mode) { + case midgard_src_passthrough: + c += upper * 8; + break; + case midgard_src_rep_low: + break; + case midgard_src_rep_high: + c += 8; + break; + case midgard_src_swap: + c += !upper * 8; + break; + default: + unreachable("invalid expand mode"); + break; + } /* We work on twos, actually */ if (i & 1) c++; } else { - printf(" (%d%d%d)", src->rep_low, src->rep_high, src->half); + printf(" (%u)", src->expand_mode); } if (first) @@ -415,7 +445,7 @@ print_vector_constants(FILE *fp, unsigned src_binary, fprintf(fp, ", "); mir_print_constant_component(fp, consts, c, alu->reg_mode, - src->half, src->mod, alu->op); + expands, src->mod, alu->op); } if (num_comp > 1) @@ -464,23 +494,27 @@ print_vector_src(FILE *fp, unsigned src_binary, midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary; print_srcmod(fp, is_int, src->mod, false); + bool half = INPUT_EXPANDS(src->expand_mode); + //register - unsigned bits = bits_for_mode_halved(mode, src->half); + unsigned bits = bits_for_mode_halved(mode, half); print_reg(fp, reg, bits); /* When the source was stepped down via `half`, rep_low means "higher * half" and rep_high is never seen. When it's not native, * rep_low/rep_high are for, well, replication */ + bool rep_lo = src->expand_mode & 1; + bool rep_hi = src->expand_mode & (1 << 1); if (mode == midgard_reg_mode_8) { - assert(!src->half); - print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, shrink_mode); + assert(!half); + print_swizzle_vec16(fp, src->swizzle, rep_hi, rep_lo, shrink_mode); } else if (mode == midgard_reg_mode_16) { - print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low, src->half); + print_swizzle_vec8(fp, src->swizzle, rep_hi, rep_lo, half); } else if (mode == midgard_reg_mode_32) { - print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low, src->half); + print_swizzle_vec4(fp, src->swizzle, rep_hi, rep_lo, half); } else if (mode == midgard_reg_mode_64) { - print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low, src->half); + print_swizzle_vec2(fp, src->swizzle, rep_hi, rep_lo, half); } print_srcmod_end(fp, is_int, src->mod, bits); diff --git a/src/panfrost/midgard/midgard.h b/src/panfrost/midgard/midgard.h index 85450c0530c..1773e20a8e3 100644 --- a/src/panfrost/midgard/midgard.h +++ b/src/panfrost/midgard/midgard.h @@ -273,13 +273,7 @@ __attribute__((__packed__)) /* Either midgard_int_mod or from midgard_float_mod_*, depending on the * type of op */ unsigned mod : 2; - - /* replicate lower half if dest = half, or low/high half selection if - * dest = full - */ - bool rep_low : 1; - bool rep_high : 1; /* unused if dest = full */ - bool half : 1; /* only matters if dest = full */ + midgard_src_expand_mode expand_mode : 3; unsigned swizzle : 8; } midgard_vector_alu_src; diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c index 4bb24b1979c..e4cb994b7cb 100644 --- a/src/panfrost/midgard/midgard_emit.c +++ b/src/panfrost/midgard/midgard_emit.c @@ -196,13 +196,11 @@ mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu) static unsigned mir_pack_swizzle(unsigned mask, unsigned *swizzle, unsigned sz, unsigned base_size, - bool op_channeled, bool *rep_low, bool *rep_high, bool *half) + bool op_channeled, midgard_src_expand_mode *expand_mode) { unsigned packed = 0; - *rep_low = false; - *rep_high = false; - *half = false; + *expand_mode = midgard_src_passthrough; midgard_reg_mode reg_mode = reg_mode_for_bitsize(base_size); @@ -213,8 +211,6 @@ mir_pack_swizzle(unsigned mask, unsigned *swizzle, packed = mir_pack_swizzle_64(swizzle, components); if (sz == 32) { - *half = true; - bool lo = swizzle[0] >= COMPONENT_Z; bool hi = swizzle[1] >= COMPONENT_Z; @@ -223,9 +219,11 @@ mir_pack_swizzle(unsigned mask, unsigned *swizzle, if (mask & 2) assert(lo == hi); - *rep_low = lo; + *expand_mode = lo ? midgard_src_expand_high : + midgard_src_expand_low; } else { - *rep_low = hi; + *expand_mode = hi ? midgard_src_expand_high : + midgard_src_expand_low; } } else if (sz < 32) { unreachable("Cannot encode 8/16 swizzle in 64-bit"); @@ -268,17 +266,18 @@ mir_pack_swizzle(unsigned mask, unsigned *swizzle, * dot products */ if (reg_mode == midgard_reg_mode_16 && sz == 16) { - *rep_low = !upper; - *rep_high = upper; + *expand_mode = upper ? midgard_src_rep_high : + midgard_src_rep_low; } else if (reg_mode == midgard_reg_mode_16 && sz == 8) { - if (base_size == 16) - *half = true; - - *rep_low = upper; - *rep_high = upper; + if (base_size == 16) { + *expand_mode = upper ? midgard_src_expand_high : + midgard_src_expand_low; + } else if (upper) { + *expand_mode = midgard_src_swap; + } } else if (reg_mode == midgard_reg_mode_32 && sz == 16) { - *half = true; - *rep_low = upper; + *expand_mode = upper ? midgard_src_expand_high : + midgard_src_expand_low; } else if (reg_mode == midgard_reg_mode_8) { unreachable("Unhandled reg mode"); } @@ -304,16 +303,14 @@ mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu) unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]); assert((sz == base_size) || (sz == base_size / 2)); - bool rep_lo = false, rep_hi = false, half = false; + midgard_src_expand_mode expand_mode = midgard_src_passthrough; unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i], sz, base_size, channeled, - &rep_lo, &rep_hi, &half); + &expand_mode); midgard_vector_alu_src pack = { .mod = mir_pack_mod(ins, i, false), - .rep_low = rep_lo, - .rep_high = rep_hi, - .half = half, + .expand_mode = expand_mode, .swizzle = swizzle };