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i965: Add gen8 fast clear perf debug

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In an ideal world I would just implement this instead of adding the perf debug.
There are some errata involved which lead me to believe it won't be so simple as
flipping a few bits.

There is room to add a thing for Gen9s flexibility, but since I am actively
working on that I have opted to ignore it.

Example:
Multi-LOD fast clear - giving up (256x128x8).

v2: Use braces for if statements because they are multiple lines (Ken)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Ben Widawsky 2015-06-04 23:59:23 -07:00
parent 77a44512d9
commit b639ed2f1b
2 changed files with 19 additions and 2 deletions
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4
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
View file

@ -340,6 +340,10 @@ is_color_fast_clear_compatible(struct brw_context *brw,
const union gl_color_union *color)
{
if (_mesa_is_format_integer_color(format))
if (brw->gen >= 8) {
perf_debug("Integer fast clear not enabled for (%s)",
_mesa_get_format_name(format));
}
return false;
for (int i = 0; i < 4; i++) {

17
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -198,10 +198,23 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
return false;
if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
return false;
if (mt->first_level != 0 || mt->last_level != 0)
if (mt->first_level != 0 || mt->last_level != 0) {
if (brw->gen >= 8) {
perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
mt->logical_width0, mt->logical_height0, mt->last_level);
}
return false;
if (mt->physical_depth0 != 1)
}
if (mt->physical_depth0 != 1) {
if (brw->gen >= 8) {
perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
mt->logical_width0, mt->logical_height0,
mt->physical_depth0);
}
return false;
}
/* There's no point in using an MCS buffer if the surface isn't in a
* renderable format.