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i965: Delete some dead code from brw_eu_emit.c.

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Presumably some of this was used by the old fragment shader backend.
This commit is contained in:
Kenneth Graunke 2012-10-08 09:51:08 -07:00
parent 840d8484c0
commit b6346749a8
2 changed files with 0 additions and 120 deletions
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12
src/mesa/drivers/dri/i965/brw_eu.h
View file

@ -974,13 +974,6 @@ void brw_SAMPLE(struct brw_compile *p,
GLuint simd_mode,
GLuint return_format);
void brw_math_16( struct brw_compile *p,
struct brw_reg dest,
GLuint function,
GLuint msg_reg_nr,
struct brw_reg src,
GLuint precision );
void brw_math( struct brw_compile *p,
struct brw_reg dest,
GLuint function,
@ -1012,11 +1005,6 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
int num_regs,
GLuint offset);
void brw_dword_scattered_read(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
uint32_t bind_table_index);
void brw_dp_READ_4_vs( struct brw_compile *p,
struct brw_reg dest,
GLuint location,

108
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

@ -1771,74 +1771,6 @@ void brw_math2(struct brw_compile *p,
brw_set_src1(p, insn, src1);
}
/**
* Extended math function, float[16].
* Use 2 send instructions.
*/
void brw_math_16( struct brw_compile *p,
struct brw_reg dest,
GLuint function,
GLuint msg_reg_nr,
struct brw_reg src,
GLuint precision )
{
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
if (intel->gen >= 6) {
insn = next_insn(p, BRW_OPCODE_MATH);
/* Math is the same ISA format as other opcodes, except that CondModifier
* becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
*/
insn->header.destreg__conditionalmod = function;
/* Source modifiers are ignored for extended math instructions. */
assert(!src.negate);
assert(!src.abs);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src);
brw_set_src1(p, insn, brw_null_reg());
return;
}
/* First instruction:
*/
brw_push_insn_state(p);
brw_set_predicate_control_flag_value(p, 0xff);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src);
brw_set_math_message(p,
insn,
function,
BRW_MATH_INTEGER_UNSIGNED,
precision,
BRW_MATH_DATA_VECTOR);
/* Second instruction:
*/
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
insn->header.destreg__conditionalmod = msg_reg_nr+1;
brw_set_dest(p, insn, offset(dest,1));
brw_set_src0(p, insn, src);
brw_set_math_message(p,
insn,
function,
BRW_MATH_INTEGER_UNSIGNED,
precision,
BRW_MATH_DATA_VECTOR);
brw_pop_insn_state(p);
}
/**
* Write a block of OWORDs (half a GRF each) from the scratch buffer,
@ -2082,46 +2014,6 @@ void brw_oword_block_read(struct brw_compile *p,
brw_pop_insn_state(p);
}
/**
* Read a set of dwords from the data port Data Cache (const buffer).
*
* Location (in buffer) appears as UD offsets in the register after
* the provided mrf header reg.
*/
void brw_dword_scattered_read(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
uint32_t bind_table_index)
{
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
brw_push_insn_state(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_pop_insn_state(p);
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.destreg__conditionalmod = mrf.nr;
/* cast dest to a uword[8] vector */
dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, brw_null_reg());
brw_set_dp_read_message(p,
insn,
bind_table_index,
BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS,
BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ,
BRW_DATAPORT_READ_TARGET_DATA_CACHE,
2, /* msg_length */
1); /* response_length */
}
/**
* Read float[4] constant(s) from VS constant buffer.