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fix

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32329>
This commit is contained in:
Lionel Landwerlin 2024-11-26 12:54:26 +02:00 • committed by Marge Bot
parent 6eb48a3e47
commit b625a573da
4 changed files with 12 additions and 4 deletions
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1
src/intel/compiler/intel_nir_blockify_uniform_loads.c
View file

@ -91,6 +91,7 @@ intel_nir_blockify_uniform_loads_instr(nir_builder *b,
return true; return true;
case nir_intrinsic_load_global_constant: case nir_intrinsic_load_global_constant:
return false;
if (nir_src_is_divergent(&intrin->src[0])) if (nir_src_is_divergent(&intrin->src[0]))
return false; return false;

6
src/intel/vulkan/anv_descriptor_set.c
View file

@ -2473,9 +2473,9 @@ anv_descriptor_set_write_buffer(struct anv_device *device,
/* We report a bounds checking alignment of 32B for the sake of block /* We report a bounds checking alignment of 32B for the sake of block
* messages which read an entire register worth at a time. * messages which read an entire register worth at a time.
*/ */
if (type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER || /* if (type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER || */
type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC) /* type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC) */
desc->bind_range = align64(desc->bind_range, ANV_UBO_ALIGNMENT); /* desc->bind_range = align64(desc->bind_range, ANV_UBO_ALIGNMENT); */
if (data & ANV_DESCRIPTOR_INDIRECT_ADDRESS_RANGE) { if (data & ANV_DESCRIPTOR_INDIRECT_ADDRESS_RANGE) {
struct anv_address_range_descriptor desc_data = { struct anv_address_range_descriptor desc_data = {

7
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
View file

@ -424,6 +424,10 @@ build_optimized_load_render_surface_state_address(nir_builder *b,
nir_def *addr_udw = nir_channel(b, surface_addr, 1); nir_def *addr_udw = nir_channel(b, surface_addr, 1);
nir_def *length = nir_channel(b, surface_addr, 3); nir_def *length = nir_channel(b, surface_addr, 3);
nir_printf_fmt(b, true, 64, "ubo_len=%u\n",
length);
return nir_vec4(b, addr_ldw, addr_udw, length, nir_imm_int(b, 0)); return nir_vec4(b, addr_ldw, addr_udw, length, nir_imm_int(b, 0));
} }
@ -500,6 +504,9 @@ build_non_optimized_load_render_surface_state_address(nir_builder *b,
length = nir_ior(b, length, nir_ishl_imm(b, depth, width_bits + height_bits)); length = nir_ior(b, length, nir_ishl_imm(b, depth, width_bits + height_bits));
length = nir_iadd_imm(b, length, 1); length = nir_iadd_imm(b, length, 1);
nir_printf_fmt(b, true, 64, "ubo_len=%u\n",
length);
/* Check the surface type, if it's SURFTYPE_NULL, set the length of the /* Check the surface type, if it's SURFTYPE_NULL, set the length of the
* buffer to 0. * buffer to 0.
*/ */

2
src/intel/vulkan/anv_nir_lower_ubo_loads.c
View file

@ -44,7 +44,7 @@ lower_ubo_load_instr(nir_builder *b, nir_intrinsic_instr *load,
unsigned byte_size = bit_size / 8; unsigned byte_size = bit_size / 8;
nir_def *val; nir_def *val;
if (!nir_src_is_divergent(&load->src[0]) && nir_src_is_const(load->src[1])) { if (!nir_src_is_divergent(&load->src[0]) && nir_src_is_const(load->src[1]) && false) {
uint32_t offset = nir_src_as_uint(load->src[1]); uint32_t offset = nir_src_as_uint(load->src[1]);
/* Things should be component-aligned. */ /* Things should be component-aligned. */