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nir/from_ssa: Drop legacy reg support
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
bbb9838b78
commit
b606a0b91e
1 changed files with 5 additions and 316 deletions
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@ -37,7 +37,6 @@ struct from_ssa_state {
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void *dead_ctx;
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void *dead_ctx;
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struct exec_list dead_instrs;
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struct exec_list dead_instrs;
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bool phi_webs_only;
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bool phi_webs_only;
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bool reg_intrinsics;
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struct hash_table *merge_node_table;
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struct hash_table *merge_node_table;
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nir_instr *instr;
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nir_instr *instr;
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bool progress;
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bool progress;
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@ -521,18 +520,6 @@ aggressive_coalesce_block(nir_block *block, struct from_ssa_state *state)
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return true;
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return true;
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}
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}
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static nir_register *
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create_reg_for_ssa_def(nir_ssa_def *def, nir_function_impl *impl)
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{
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nir_register *reg = nir_local_reg_create(impl);
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reg->num_components = def->num_components;
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reg->bit_size = def->bit_size;
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reg->num_array_elems = 0;
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return reg;
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}
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static nir_ssa_def *
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static nir_ssa_def *
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decl_reg_for_ssa_def(nir_builder *b, nir_ssa_def *def)
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decl_reg_for_ssa_def(nir_builder *b, nir_ssa_def *def)
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{
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{
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@ -591,87 +578,6 @@ nir_rewrite_uses_to_load_reg(nir_builder *b, nir_ssa_def *old,
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}
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}
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}
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}
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static bool
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rewrite_ssa_def_legacy_reg(nir_ssa_def *def, void *void_state)
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{
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struct from_ssa_state *state = void_state;
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nir_register *reg;
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struct hash_entry *entry =
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_mesa_hash_table_search(state->merge_node_table, def);
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if (entry) {
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/* In this case, we're part of a phi web. Use the web's register. */
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merge_node *node = (merge_node *)entry->data;
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/* If it doesn't have a register yet, create one. Note that all of
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* the things in the merge set should be the same so it doesn't
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* matter which node's definition we use.
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*/
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if (node->set->reg.reg == NULL) {
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node->set->reg.reg = create_reg_for_ssa_def(def, state->builder.impl);
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node->set->reg.reg->divergent = node->set->divergent;
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}
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reg = node->set->reg.reg;
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} else {
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if (state->phi_webs_only)
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return true;
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/* We leave load_const SSA values alone. They act as immediates to
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* the backend. If it got coalesced into a phi, that's ok.
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*/
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if (def->parent_instr->type == nir_instr_type_load_const)
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return true;
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reg = create_reg_for_ssa_def(def, state->builder.impl);
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}
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nir_ssa_def_rewrite_uses_src(def, nir_src_for_reg(reg));
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assert(nir_ssa_def_is_unused(def));
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if (def->parent_instr->type == nir_instr_type_ssa_undef) {
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/* If it's an ssa_undef instruction, remove it since we know we just got
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* rid of all its uses.
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*/
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nir_instr *parent_instr = def->parent_instr;
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nir_instr_remove(parent_instr);
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exec_list_push_tail(&state->dead_instrs, &parent_instr->node);
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state->progress = true;
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return true;
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}
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assert(def->parent_instr->type != nir_instr_type_load_const);
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/* At this point we know a priori that this SSA def is part of a
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* nir_dest. We can use exec_node_data to get the dest pointer.
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*/
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nir_dest *dest = exec_node_data(nir_dest, def, ssa);
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nir_instr_rewrite_dest(state->instr, dest, nir_dest_for_reg(reg));
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state->progress = true;
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return true;
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}
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/* Resolves ssa definitions to registers. While we're at it, we also
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* remove phi nodes.
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*/
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static void
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resolve_registers_block_legacy_reg(nir_block *block,
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struct from_ssa_state *state)
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{
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nir_foreach_instr_safe(instr, block) {
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state->instr = instr;
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nir_foreach_ssa_def(instr, rewrite_ssa_def_legacy_reg, state);
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if (instr->type == nir_instr_type_phi) {
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nir_instr_remove(instr);
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exec_list_push_tail(&state->dead_instrs, &instr->node);
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state->progress = true;
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}
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}
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state->instr = NULL;
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}
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static bool
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static bool
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dest_replace_ssa_with_reg(nir_dest *dest, nir_function_impl *impl)
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dest_replace_ssa_with_reg(nir_dest *dest, nir_function_impl *impl)
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{
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{
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@ -855,25 +761,6 @@ resolve_registers_impl(nir_function_impl *impl, struct from_ssa_state *state)
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}
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}
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}
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}
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static void
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emit_copy(nir_builder *b, nir_src src, nir_src dest_src)
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{
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assert(!dest_src.is_ssa);
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assert(!nir_src_is_divergent(src) || nir_src_is_divergent(dest_src));
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if (src.is_ssa)
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assert(src.ssa->num_components >= dest_src.reg.reg->num_components);
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else
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assert(src.reg.reg->num_components >= dest_src.reg.reg->num_components);
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nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
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nir_src_copy(&mov->src[0].src, &src, &mov->instr);
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mov->dest.dest = nir_dest_for_reg(dest_src.reg.reg);
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mov->dest.write_mask = (1 << dest_src.reg.reg->num_components) - 1;
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nir_builder_instr_insert(b, &mov->instr);
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}
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/* Resolves a single parallel copy operation into a sequence of movs
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/* Resolves a single parallel copy operation into a sequence of movs
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*
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*
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* This is based on Algorithm 1 from "Revisiting Out-of-SSA Translation for
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* This is based on Algorithm 1 from "Revisiting Out-of-SSA Translation for
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@ -896,174 +783,6 @@ emit_copy(nir_builder *b, nir_src src, nir_src dest_src)
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* we copied as living in that temporary. Now, the cycle is broken, so we
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* we copied as living in that temporary. Now, the cycle is broken, so we
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* can continue with the above steps.
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* can continue with the above steps.
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*/
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*/
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static void
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resolve_parallel_copy_legacy_reg(nir_parallel_copy_instr *pcopy,
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struct from_ssa_state *state)
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{
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unsigned num_copies = 0;
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nir_foreach_parallel_copy_entry(entry, pcopy) {
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/* Sources may be SSA but destinations are always registers */
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assert(!entry->src_is_reg);
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assert(!entry->dest_is_reg && !entry->dest.dest.is_ssa);
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if (!entry->src.is_ssa && entry->src.reg.reg == entry->dest.dest.reg.reg)
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continue;
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num_copies++;
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}
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if (num_copies == 0) {
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/* Hooray, we don't need any copies! */
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nir_instr_remove(&pcopy->instr);
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exec_list_push_tail(&state->dead_instrs, &pcopy->instr.node);
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return;
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}
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/* The register/source corresponding to the given index */
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NIR_VLA_ZERO(nir_src, values, num_copies * 2);
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/* The current location of a given piece of data. We will use -1 for "null" */
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NIR_VLA_FILL(int, loc, num_copies * 2, -1);
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/* The piece of data that the given piece of data is to be copied from. We will use -1 for "null" */
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NIR_VLA_FILL(int, pred, num_copies * 2, -1);
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/* The destinations we have yet to properly fill */
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NIR_VLA(int, to_do, num_copies * 2);
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int to_do_idx = -1;
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state->builder.cursor = nir_before_instr(&pcopy->instr);
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/* Now we set everything up:
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* - All values get assigned a temporary index
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* - Current locations are set from sources
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* - Predecessors are recorded from sources and destinations
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*/
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int num_vals = 0;
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nir_foreach_parallel_copy_entry(entry, pcopy) {
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/* Sources may be SSA but destinations are always registers */
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if (!entry->src.is_ssa && entry->src.reg.reg == entry->dest.dest.reg.reg)
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continue;
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int src_idx = -1;
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for (int i = 0; i < num_vals; ++i) {
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if (nir_srcs_equal(values[i], entry->src))
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src_idx = i;
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}
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if (src_idx < 0) {
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src_idx = num_vals++;
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values[src_idx] = entry->src;
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}
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nir_src dest_src = nir_src_for_reg(entry->dest.dest.reg.reg);
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int dest_idx = -1;
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for (int i = 0; i < num_vals; ++i) {
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if (nir_srcs_equal(values[i], dest_src)) {
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/* Each destination of a parallel copy instruction should be
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* unique. A destination may get used as a source, so we still
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* have to walk the list. However, the predecessor should not,
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* at this point, be set yet, so we should have -1 here.
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*/
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assert(pred[i] == -1);
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dest_idx = i;
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}
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}
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if (dest_idx < 0) {
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dest_idx = num_vals++;
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values[dest_idx] = dest_src;
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}
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loc[src_idx] = src_idx;
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pred[dest_idx] = src_idx;
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to_do[++to_do_idx] = dest_idx;
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}
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/* Currently empty destinations we can go ahead and fill */
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NIR_VLA(int, ready, num_copies * 2);
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int ready_idx = -1;
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/* Mark the ones that are ready for copying. We know an index is a
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* destination if it has a predecessor and it's ready for copying if
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* it's not marked as containing data.
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*/
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for (int i = 0; i < num_vals; i++) {
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if (pred[i] != -1 && loc[i] == -1)
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ready[++ready_idx] = i;
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}
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while (1) {
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while (ready_idx >= 0) {
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int b = ready[ready_idx--];
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int a = pred[b];
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emit_copy(&state->builder, values[loc[a]], values[b]);
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/* b has been filled, mark it as not needing to be copied */
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pred[b] = -1;
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/* The next bit only applies if the source and destination have the
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* same divergence. If they differ (it must be convergent ->
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* divergent), then we can't guarantee we won't need the convergent
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* version of it again.
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*/
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if (nir_src_is_divergent(values[a]) ==
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nir_src_is_divergent(values[b])) {
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/* If a needs to be filled... */
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if (pred[a] != -1) {
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/* If any other copies want a they can find it at b */
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loc[a] = b;
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/* It's ready for copying now */
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ready[++ready_idx] = a;
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}
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}
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}
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assert(ready_idx < 0);
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if (to_do_idx < 0)
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break;
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int b = to_do[to_do_idx--];
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if (pred[b] == -1)
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continue;
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/* If we got here, then we don't have any more trivial copies that we
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* can do. We have to break a cycle, so we create a new temporary
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* register for that purpose. Normally, if going out of SSA after
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* register allocation, you would want to avoid creating temporary
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* registers. However, we are going out of SSA before register
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* allocation, so we would rather not create extra register
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* dependencies for the backend to deal with. If it wants, the
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* backend can coalesce the (possibly multiple) temporaries.
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*
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* We can also get here in the case where there is no cycle but our
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* source value is convergent, is also used as a destination by another
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* element of the parallel copy, and all the destinations of the
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* parallel copy which copy from it are divergent. In this case, the
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* above loop cannot detect that the value has moved due to all the
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* divergent destinations and we'll end up emitting a copy to a
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* temporary which never gets used. We can avoid this with additional
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* tracking or we can just trust the back-end to dead-code the unused
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* temporary (which is trivial).
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*/
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assert(num_vals < num_copies * 2);
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nir_register *reg = nir_local_reg_create(state->builder.impl);
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reg->num_array_elems = 0;
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reg->num_components = nir_src_num_components(values[b]);
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reg->bit_size = nir_src_bit_size(values[b]);
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reg->divergent = nir_src_is_divergent(values[b]);
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values[num_vals] = nir_src_for_reg(reg);
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emit_copy(&state->builder, values[b], values[num_vals]);
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loc[b] = num_vals;
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ready[++ready_idx] = b;
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num_vals++;
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}
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nir_instr_remove(&pcopy->instr);
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exec_list_push_tail(&state->dead_instrs, &pcopy->instr.node);
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}
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struct copy_value {
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struct copy_value {
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bool is_reg;
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bool is_reg;
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nir_ssa_def *ssa;
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nir_ssa_def *ssa;
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@ -1100,11 +819,6 @@ static void
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resolve_parallel_copy(nir_parallel_copy_instr *pcopy,
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resolve_parallel_copy(nir_parallel_copy_instr *pcopy,
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struct from_ssa_state *state)
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struct from_ssa_state *state)
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{
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{
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if (!state->reg_intrinsics) {
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resolve_parallel_copy_legacy_reg(pcopy, state);
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return;
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}
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unsigned num_copies = 0;
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unsigned num_copies = 0;
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nir_foreach_parallel_copy_entry(entry, pcopy) {
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nir_foreach_parallel_copy_entry(entry, pcopy) {
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/* Sources may be SSA but destinations are always registers */
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/* Sources may be SSA but destinations are always registers */
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@ -1302,7 +1016,6 @@ resolve_parallel_copies_block(nir_block *block, struct from_ssa_state *state)
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if (first_instr == NULL)
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if (first_instr == NULL)
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return true; /* Empty, nothing to do. */
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return true; /* Empty, nothing to do. */
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if (state->reg_intrinsics) {
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/* There can be load_reg in the way of the copies... don't be clever. */
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/* There can be load_reg in the way of the copies... don't be clever. */
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nir_foreach_instr_safe(instr, block) {
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nir_foreach_instr_safe(instr, block) {
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||||||
if (instr->type == nir_instr_type_parallel_copy) {
|
if (instr->type == nir_instr_type_parallel_copy) {
|
||||||
|
|
@ -1311,23 +1024,6 @@ resolve_parallel_copies_block(nir_block *block, struct from_ssa_state *state)
|
||||||
resolve_parallel_copy(pcopy, state);
|
resolve_parallel_copy(pcopy, state);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else {
|
|
||||||
if (first_instr->type == nir_instr_type_parallel_copy) {
|
|
||||||
nir_parallel_copy_instr *pcopy = nir_instr_as_parallel_copy(first_instr);
|
|
||||||
|
|
||||||
resolve_parallel_copy(pcopy, state);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* It's possible that the above code already cleaned up the end parallel
|
|
||||||
* copy. However, doing so removed it form the instructions list so we
|
|
||||||
* won't find it here. Therefore, it's safe to go ahead and just look
|
|
||||||
* for one and clean it up if it exists.
|
|
||||||
*/
|
|
||||||
nir_parallel_copy_instr *end_pcopy =
|
|
||||||
get_parallel_copy_at_end_of_block(block);
|
|
||||||
if (end_pcopy)
|
|
||||||
resolve_parallel_copy(end_pcopy, state);
|
|
||||||
}
|
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
@ -1343,7 +1039,6 @@ nir_convert_from_ssa_impl(nir_function_impl *impl,
|
||||||
state.builder = nir_builder_create(impl);
|
state.builder = nir_builder_create(impl);
|
||||||
state.dead_ctx = ralloc_context(NULL);
|
state.dead_ctx = ralloc_context(NULL);
|
||||||
state.phi_webs_only = phi_webs_only;
|
state.phi_webs_only = phi_webs_only;
|
||||||
state.reg_intrinsics = true;
|
|
||||||
state.merge_node_table = _mesa_pointer_hash_table_create(NULL);
|
state.merge_node_table = _mesa_pointer_hash_table_create(NULL);
|
||||||
state.progress = false;
|
state.progress = false;
|
||||||
exec_list_make_empty(&state.dead_instrs);
|
exec_list_make_empty(&state.dead_instrs);
|
||||||
|
|
@ -1373,13 +1068,7 @@ nir_convert_from_ssa_impl(nir_function_impl *impl,
|
||||||
aggressive_coalesce_block(block, &state);
|
aggressive_coalesce_block(block, &state);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (state.reg_intrinsics) {
|
|
||||||
resolve_registers_impl(impl, &state);
|
resolve_registers_impl(impl, &state);
|
||||||
} else {
|
|
||||||
nir_foreach_block(block, impl) {
|
|
||||||
resolve_registers_block_legacy_reg(block, &state);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
nir_foreach_block(block, impl) {
|
nir_foreach_block(block, impl) {
|
||||||
resolve_parallel_copies_block(block, &state);
|
resolve_parallel_copies_block(block, &state);
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue