From b5f11080452fc97fcd0abe2db26c76e581994cbd Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Thu, 29 May 2025 16:35:22 -0400 Subject: [PATCH] freedreno/crashdec: Add support for CP_BV_MEMPOOL The BV mempool is even further cut down compared to the "small mem pool" layout which seems to be used by a610. It also shrinks the block size to 4 chunks instead of 8. This layout happens to be shared by a702, so abstract out the layout into a "mempool size" enum. While we're here, fix a bug with how the mempool offset for chunks is printed. This accounts for the test diff. Part-of: --- src/freedreno/decode/crashdec-mempool.c | 124 ++++++++---- src/freedreno/decode/crashdec.c | 4 +- src/freedreno/decode/crashdec.h | 2 +- .../tests/reference/crash_prefetch.log | 180 +++++++++--------- 4 files changed, 177 insertions(+), 133 deletions(-) diff --git a/src/freedreno/decode/crashdec-mempool.c b/src/freedreno/decode/crashdec-mempool.c index 2abeed09405..e1c97a6a643 100644 --- a/src/freedreno/decode/crashdec-mempool.c +++ b/src/freedreno/decode/crashdec-mempool.c @@ -71,7 +71,7 @@ dump_mem_pool_chunk(const uint32_t *chunk) } void -dump_cp_mem_pool(uint32_t *mempool) +dump_cp_mem_pool(uint32_t *mempool, bool is_bv) { /* The mem pool is a shared pool of memory used for storing in-flight * register writes. There are 6 different queues, one for each @@ -82,11 +82,12 @@ dump_cp_mem_pool(uint32_t *mempool) * * The queues are conceptually divided into 128-bit "chunks", and the * read and write pointers are in units of chunks. These chunks are - * organized internally into 8-chunk "blocks", and memory is allocated - * dynamically in terms of blocks. Each queue is represented as a - * singly-linked list of blocks, as well as 3-bit start/end chunk - * pointers that point within the first/last block. The next pointers - * are located in a separate array, rather than inline. + * organized internally into 8-chunk (or on certain cut-down parts, + * 4-chunk) "blocks", and memory is allocated dynamically in terms of + * blocks. Each queue is represented as a singly-linked list of blocks, as + * well as 3-bit start/end chunk pointers that point within the first/last + * block. The next pointers are located in a separate array, rather than + * inline. */ /* TODO: The firmware CP_MEM_POOL save/restore routines do something @@ -111,17 +112,60 @@ dump_cp_mem_pool(uint32_t *mempool) */ bool small_mem_pool = false; - /* The array of next pointers for each block. */ - const uint32_t *next_pointers = - small_mem_pool ? &mempool[0x800] : &mempool[0x1000]; + enum { + MEMPOOL_FULL, + MEMPOOL_HALF, + MEMPOOL_QUARTER, + } mempool_size = MEMPOOL_FULL; + if (small_mem_pool) + mempool_size = MEMPOOL_HALF; + else if (is_bv) + mempool_size = MEMPOOL_QUARTER; + + uint32_t next_pointers_offset; + uint32_t data1_offset; + uint32_t data2_offset; /* Maximum number of blocks in the pool, also the size of the pointers * array. */ - const int num_blocks = small_mem_pool ? 0x30 : 0x80; + int num_blocks; + /* log2 of number of chunks per block. */ + int block_size_log2; - /* Number of queues */ - const unsigned num_queues = is_a6xx() ? 6 : 7; + switch (mempool_size) { + case MEMPOOL_FULL: + next_pointers_offset = 0x1000; + data1_offset = 0x1800; + data2_offset = 0x2000; + num_blocks = 0x80; + block_size_log2 = 3; + break; + case MEMPOOL_HALF: + next_pointers_offset = 0x800; + data1_offset = 0xc00; + data2_offset = 0x1000; + num_blocks = 0x30; + block_size_log2 = 3; + break; + case MEMPOOL_QUARTER: + next_pointers_offset = 0x400; + data1_offset = 0x600; + data2_offset = 0x800; + num_blocks = 0x40; + block_size_log2 = 2; + break; + default: + UNREACHABLE("unknown mempool size"); + } + const uint32_t *next_pointers = &mempool[next_pointers_offset]; + + const int block_size = 1 << block_size_log2; + + /* Number of queues or clusters. On a7xx the clusters are shuffled a bit to + * increase the count by one, but BV seems to not use the last cluster. + */ + const unsigned num_queues = (is_a6xx() || is_bv) ? 6 : 7; /* Unfortunately the per-queue state is a little more complicated than * a simple pair of begin/end pointers. Instead of a single beginning @@ -182,11 +226,8 @@ dump_cp_mem_pool(uint32_t *mempool) uint32_t unk0; uint32_t padding0[7]; /* Mirrors of unk0 */ - struct { - uint32_t chunk : 3; - uint32_t first_block : 32 - 3; - } writer[6]; - uint32_t padding1[2]; /* Mirror of writer[5] */ + uint32_t writer_first_block_chunk[7]; + uint32_t padding1[1]; /* Mirror of writer_first_block_chunk[6] */ uint32_t unk1; uint32_t padding2[7]; /* Mirrors of unk1 */ @@ -197,11 +238,8 @@ dump_cp_mem_pool(uint32_t *mempool) uint32_t unk2[7]; uint32_t padding4[1]; - struct { - uint32_t chunk : 3; - uint32_t first_block : 32 - 3; - } reader[7]; - uint32_t padding5[1]; /* Mirror of reader[5] */ + uint32_t reader_first_block_chunk[7]; + uint32_t padding5[1]; /* Mirror of reader_first_block_chunk[6] */ uint32_t unk3; uint32_t padding6[7]; /* Mirrors of unk3 */ @@ -216,15 +254,13 @@ dump_cp_mem_pool(uint32_t *mempool) uint32_t padding9[7]; /* Mirrors of unk4 */ } data1; - const uint32_t *data1_ptr = - small_mem_pool ? &mempool[0xc00] : &mempool[0x1800]; + const uint32_t *data1_ptr = &mempool[data1_offset]; memcpy(&data1, data1_ptr, sizeof(data1)); /* Based on the kernel, the first dword is the mem pool size (in * blocks?) and mirrors CP_MEM_POOL_DBG_SIZE. */ - const uint32_t *data2_ptr = - small_mem_pool ? &mempool[0x1000] : &mempool[0x2000]; + const uint32_t *data2_ptr = &mempool[data2_offset]; const int data2_size = 0x60; /* This seems to be the size of each queue in chunks. */ @@ -249,28 +285,34 @@ dump_cp_mem_pool(uint32_t *mempool) printf("\tCLUSTER_%s:\n\n", is_a6xx() ? cluster_names_a6xx[queue] : cluster_names_a7xx[queue]); + uint32_t writer_first_block = + data1.writer_first_block_chunk[queue] >> block_size_log2; + uint32_t writer_chunk = + data1.writer_first_block_chunk[queue] & (block_size - 1); + uint32_t reader_first_block = + data1.reader_first_block_chunk[queue] >> block_size_log2; + uint32_t reader_chunk = + data1.reader_first_block_chunk[queue] & (block_size - 1); if (verbose) { - printf("\t\twriter_first_block: 0x%x\n", - data1.writer[queue].first_block); + printf("\t\twriter_first_block: 0x%x\n", writer_first_block); printf("\t\twriter_second_block: 0x%x\n", data1.writer_second_block[queue]); - printf("\t\twriter_chunk: %d\n", data1.writer[queue].chunk); - printf("\t\treader_first_block: 0x%x\n", - data1.reader[queue].first_block); + printf("\t\twriter_chunk: %d\n", writer_chunk); + printf("\t\treader_first_block: 0x%x\n", reader_first_block); printf("\t\treader_second_block: 0x%x\n", data1.reader_second_block[queue]); - printf("\t\treader_chunk: %d\n", data1.reader[queue].chunk); + printf("\t\treader_chunk: %d\n", reader_chunk); printf("\t\tblock_count: %d\n", data1.block_count[queue]); printf("\t\tunk2: 0x%x\n", data1.unk2[queue]); printf("\t\tqueue_size: %d\n\n", queue_sizes[queue]); } - uint32_t cur_chunk = data1.reader[queue].chunk; - uint32_t cur_block = cur_chunk > 3 ? data1.reader[queue].first_block - : data1.reader_second_block[queue]; - uint32_t last_chunk = data1.writer[queue].chunk; - uint32_t last_block = last_chunk > 3 ? data1.writer[queue].first_block - : data1.writer_second_block[queue]; + uint32_t cur_chunk = reader_chunk; + uint32_t cur_block = cur_chunk >= block_size / 2 ? + reader_first_block : data1.reader_second_block[queue]; + uint32_t last_chunk = writer_chunk; + uint32_t last_block = last_chunk >= block_size / 2 ? + writer_first_block : data1.writer_second_block[queue]; if (verbose) printf("\tblock %x\n", cur_block); @@ -281,16 +323,16 @@ dump_cp_mem_pool(uint32_t *mempool) unsigned calculated_queue_size = 0; while (cur_block != last_block || cur_chunk != last_chunk) { calculated_queue_size++; - uint32_t *chunk_ptr = &mempool[cur_block * 0x20 + cur_chunk * 4]; + uint32_t *chunk_ptr = &mempool[(cur_block * block_size + cur_chunk) * 4]; dump_mem_pool_chunk(chunk_ptr); printf("\t%05x: %08x %08x %08x %08x\n", - 4 * (cur_block * 0x20 + cur_chunk + 4), chunk_ptr[0], + 16 * (cur_block * block_size + cur_chunk), chunk_ptr[0], chunk_ptr[1], chunk_ptr[2], chunk_ptr[3]); cur_chunk++; - if (cur_chunk == 8) { + if (cur_chunk == block_size) { cur_block = next_pointers[cur_block]; if (verbose) printf("\tblock %x\n", cur_block); diff --git a/src/freedreno/decode/crashdec.c b/src/freedreno/decode/crashdec.c index 36ec71ceefc..0ee93046fe2 100644 --- a/src/freedreno/decode/crashdec.c +++ b/src/freedreno/decode/crashdec.c @@ -900,7 +900,9 @@ decode_indexed_registers(void) dump_cp_ucode_dbg(buf); if (!strcmp(name, "CP_MEM_POOL_DBG")) - dump_cp_mem_pool(buf); + dump_cp_mem_pool(buf, false); + if (!strcmp(name, "CP_BV_MEM_POOL_DBG")) + dump_cp_mem_pool(buf, true); if (dump) dump_hex_ascii(buf, 4 * sizedwords, 1); diff --git a/src/freedreno/decode/crashdec.h b/src/freedreno/decode/crashdec.h index c7987c53e06..aa6aff91a65 100644 --- a/src/freedreno/decode/crashdec.h +++ b/src/freedreno/decode/crashdec.h @@ -85,7 +85,7 @@ is_gmu_legacy(void) } void dump_register(struct regacc *r); -void dump_cp_mem_pool(uint32_t *mempool); +void dump_cp_mem_pool(uint32_t *mempool, bool is_bv); void handle_prefetch(uint32_t *dwords, uint32_t sizedwords); struct a6xx_hfi_state { diff --git a/src/freedreno/tests/reference/crash_prefetch.log b/src/freedreno/tests/reference/crash_prefetch.log index 0ab947ac51b..28fbb50f74f 100644 --- a/src/freedreno/tests/reference/crash_prefetch.log +++ b/src/freedreno/tests/reference/crash_prefetch.log @@ -14655,346 +14655,346 @@ indexed-registers: 000170: 00000026 00000026 00000026 00000026 |&...&...&...&...| CLUSTER_FE: - 01fa0: 00000000 00000000 00000000 00000000 + 01fc0: 00000000 00000000 00000000 00000000 write PC_CNTL (09b00) context 1 PC_CNTL: { 0 } - 01fa4: 00000002 00000000 b0000000 00000209 + 01fd0: 00000002 00000000 b0000000 00000209 CLUSTER_SP_VS: - 02310: 00000000 00000000 00000000 00000000 + 02300: 00000000 00000000 00000000 00000000 CLUSTER_PC_VS: - 01f18: 00000000 00000000 00000000 00000000 + 01f20: 00000000 00000000 00000000 00000000 write PC_CNTL (09b00) context 1 PC_CNTL: { 0 } - 01f1c: 00000002 00000000 b0000000 00000209 + 01f30: 00000002 00000000 b0000000 00000209 CLUSTER_GRAS: write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x22 } - 01c1c: 00000002 00000088 60100000 0000000d + 01c30: 00000002 00000088 60100000 0000000d write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x23 } - 01c20: 00000002 0000008c 60000000 0000020d + 01c40: 00000002 0000008c 60000000 0000020d write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x23 } - 01c24: 00000002 0000008c 60100000 0000020d + 01c50: 00000002 0000008c 60100000 0000020d write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x24 } - 01c28: 00000002 00000090 60000000 0000000d + 01c60: 00000002 00000090 60000000 0000000d write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x24 } - 01c2c: 00000002 00000090 60100000 0000000d + 01c70: 00000002 00000090 60100000 0000000d write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x25 } - 02b90: 00000002 00000094 60000000 0000020d + 02b80: 00000002 00000094 60000000 0000020d write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x25 } - 02b94: 00000002 00000094 60100000 0000020d + 02b90: 00000002 00000094 60100000 0000020d write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x26 } - 02b98: 00000002 00000098 60000000 0000000d + 02ba0: 00000002 00000098 60000000 0000000d write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x26 } - 02b9c: 00000002 00000098 60100000 0000000d - 02ba0: 00000000 00000000 00000000 00000000 - 02ba4: 00000000 00000000 00000000 00000000 + 02bb0: 00000002 00000098 60100000 0000000d + 02bc0: 00000000 00000000 00000000 00000000 + 02bd0: 00000000 00000000 00000000 00000000 CLUSTER_SP_PS: write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x21 } - 01a9c: 00000002 00000084 60100000 0000020d + 01ab0: 00000002 00000084 60100000 0000020d write SP_PS_MRT[0].REG (0a996) context 0 SP_PS_MRT[0].REG: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM } write SP_PS_MRT[0x1].REG (0a997) context 0 SP_PS_MRT[0x1].REG: { COLOR_FORMAT = FMT6_5_6_5_UNORM } - 01aa0: 00000183 00000038 9972a658 0000000a + 01ac0: 00000183 00000038 9972a658 0000000a write SP_PS_MRT[0x2].REG (0a998) context 0 SP_PS_MRT[0x2].REG: { COLOR_FORMAT = FMT6_16_16_UNORM } write SP_PS_MRT[0x3].REG (0a999) context 0 SP_PS_MRT[0x3].REG: { COLOR_FORMAT = FMT6_16_16_16_16_SNORM } - 01aa4: 0000010f 00000184 9992a660 0000000a + 01ad0: 0000010f 00000184 9992a660 0000000a write SP_SRGB_CNTL (0a98a) context 0 SP_SRGB_CNTL: { 0 } - 01aa8: 00000002 00000000 98a00000 0000000a + 01ae0: 00000002 00000000 98a00000 0000000a write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x22 } - 01aac: 00000002 00000088 60000000 0000000d + 01af0: 00000002 00000088 60000000 0000000d write SP_EVENT_INITIATOR (0bb02) context 0 SP_EVENT_INITIATOR: { STATE_ID = 0x22 | EVENT = PC_CCU_FLUSH_COLOR_TS } write SP_EVENT_INITIATOR (0bb02) context 0 SP_EVENT_INITIATOR: { STATE_ID = 0x22 | EVENT = CONTEXT_DONE } - 02790: 00880077 00880014 b022ec08 0000000b + 02780: 00880077 00880014 b022ec08 0000000b write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x22 } - 02794: 00000002 00000088 60100000 0000000d + 02790: 00000002 00000088 60100000 0000000d write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x23 } - 02798: 00000002 0000008c 60000000 0000020d + 027a0: 00000002 0000008c 60000000 0000020d write SP_EVENT_INITIATOR (0bb02) context 1 SP_EVENT_INITIATOR: { STATE_ID = 0x23 | EVENT = PC_CCU_FLUSH_DEPTH_TS } write SP_EVENT_INITIATOR (0bb02) context 1 SP_EVENT_INITIATOR: { STATE_ID = 0x23 | EVENT = CONTEXT_DONE } - 0279c: 008c0073 008c0014 b022ec08 0000030b + 027b0: 008c0073 008c0014 b022ec08 0000030b write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x23 } - 027a0: 00000002 0000008c 60100000 0000020d + 027c0: 00000002 0000008c 60100000 0000020d write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x24 } - 027a4: 00000002 00000090 60000000 0000000d + 027d0: 00000002 00000090 60000000 0000000d write SP_EVENT_INITIATOR (0bb02) context 0 SP_EVENT_INITIATOR: { STATE_ID = 0x24 | EVENT = PC_CCU_INVALIDATE_COLOR } write SP_EVENT_INITIATOR (0bb02) context 0 SP_EVENT_INITIATOR: { STATE_ID = 0x24 | EVENT = CONTEXT_DONE } - 027a8: 00900067 00900014 b022ec08 0000000b + 027e0: 00900067 00900014 b022ec08 0000000b write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x24 } - 027ac: 00000002 00000090 60100000 0000000d + 027f0: 00000002 00000090 60100000 0000000d write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x25 } - 02d10: 00000002 00000094 60000000 0000020d + 02d00: 00000002 00000094 60000000 0000020d write SP_EVENT_INITIATOR (0bb02) context 1 SP_EVENT_INITIATOR: { STATE_ID = 0x25 | EVENT = PC_CCU_INVALIDATE_DEPTH } write SP_EVENT_INITIATOR (0bb02) context 1 SP_EVENT_INITIATOR: { STATE_ID = 0x25 | EVENT = CONTEXT_DONE } - 02d14: 00940063 00940014 b022ec08 0000030b + 02d10: 00940063 00940014 b022ec08 0000030b write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x25 } - 02d18: 00000002 00000094 60100000 0000020d + 02d20: 00000002 00000094 60100000 0000020d write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x26 } - 02d1c: 00000002 00000098 60000000 0000000d + 02d30: 00000002 00000098 60000000 0000000d write SP_EVENT_INITIATOR (0bb02) context 0 SP_EVENT_INITIATOR: { STATE_ID = 0x26 | EVENT = CACHE_INVALIDATE } write SP_EVENT_INITIATOR (0bb02) context 0 SP_EVENT_INITIATOR: { STATE_ID = 0x26 | EVENT = CONTEXT_DONE } - 02d20: 009800c7 00980014 b022ec08 0000000b + 02d40: 009800c7 00980014 b022ec08 0000000b write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x26 } - 02d24: 00000002 00000098 60100000 0000000d - 02d28: 00000000 00000000 00000000 00000000 - 02d2c: 00000000 00000000 00000000 00000000 + 02d50: 00000002 00000098 60100000 0000000d + 02d60: 00000000 00000000 00000000 00000000 + 02d70: 00000000 00000000 00000000 00000000 CLUSTER_PS: write CP_2D_EVENT_END (0d701) context 1 CP_2D_EVENT_END: { STATE_ID = 0x9 } - 01a24: 00000002 00000024 70100000 0000020d + 01a50: 00000002 00000024 70100000 0000020d write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT | TS_WRITE } write EVENT_TS_ADDR (e8) pipe EVENT_TS_ADDR: 0x1000 - 01a28: 00000017 00004000 0e80039c 000000c0 + 01a60: 00000017 00004000 0e80039c 000000c0 write EVENT_TS_ADDR+0x1 (e9) pipe EVENT_TS_ADDR+0x1: 0x1 write EVENT_TS_CTRL (ea) pipe EVENT_TS_CTRL: { EVENT = CCU_FLUSH_COLOR } - 01a2c: 00000007 00001400 0ea003a4 000000c0 + 01a70: 00000007 00001400 0ea003a4 000000c0 write EVENT_TS_DATA (eb) pipe EVENT_TS_DATA: 0 - 01990: 00000002 00000000 0eb00000 00000080 + 01980: 00000002 00000000 0eb00000 00000080 write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x20 } - 01994: 00000002 00000080 60000000 0000000d + 01990: 00000002 00000080 60000000 0000000d write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x20 } - 01998: 00000002 00000080 60100000 0000000d + 019a0: 00000002 00000080 60100000 0000000d write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT } - 0199c: 00000002 00000004 0e700000 00000080 + 019b0: 00000002 00000004 0e700000 00000080 write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x21 } - 019a0: 00000002 00000084 60000000 0000020d + 019c0: 00000002 00000084 60000000 0000020d write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x21 } - 019a4: 00000002 00000084 60100000 0000020d + 019d0: 00000002 00000084 60100000 0000020d write RB_DEPTH_BUFFER_INFO (08872) context 0 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } write RB_DEPTH_BUFFER_PITCH (08873) context 0 RB_DEPTH_BUFFER_PITCH: 0 - 019a8: 00000003 00000000 873221c8 00000008 + 019e0: 00000003 00000000 873221c8 00000008 write RB_DEPTH_BUFFER_ARRAY_PITCH (08874) context 0 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 write RB_DEPTH_BUFFER_BASE (08875) context 0 RB_DEPTH_BUFFER_BASE: 0 - 019ac: 00000003 00000000 875221d0 00000008 + 019f0: 00000003 00000000 875221d0 00000008 write RB_DEPTH_BUFFER_BASE_HI (08876) context 0 RB_DEPTH_BUFFER_BASE_HI: 0 write RB_DEPTH_GMEM_BASE (08877) context 0 RB_DEPTH_GMEM_BASE: 0 - 02110: 00000003 00000000 877221d8 00000008 + 02100: 00000003 00000000 877221d8 00000008 write RB_STENCIL_BUFFER_INFO (08881) context 0 RB_STENCIL_BUFFER_INFO: { 0 } write RB_MRT[0].BUF_INFO (08822) context 0 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX } - 02114: 00000003 00000d80 82222204 00000008 + 02110: 00000003 00000d80 82222204 00000008 write RB_MRT[0].PITCH (08823) context 0 RB_MRT[0].PITCH: 512 write RB_MRT[0].ARRAY_PITCH (08824) context 0 RB_MRT[0].ARRAY_PITCH: 40960 - 02118: 00000023 00000a00 8242208c 00000008 + 02120: 00000023 00000a00 8242208c 00000008 write RB_MRT[0].BASE (08825) context 0 RB_MRT[0].BASE: 0x9c000 write RB_MRT[0].BASE_HI (08826) context 0 RB_MRT[0].BASE_HI: 0x1 - 0211c: 00270003 00000004 82622094 00000008 + 02130: 00270003 00000004 82622094 00000008 write RB_MRT[0].BASE_GMEM (08827) context 0 RB_MRT[0].BASE_GMEM: 0x2e000 write RB_COLOR_FLAG_BUFFER[0].ADDR (08903) context 0 RB_COLOR_FLAG_BUFFER[0].ADDR: 0x9c000 - 02120: 000b8003 00270000 9032209c 00000008 + 02140: 000b8003 00270000 9032209c 00000008 write RB_COLOR_FLAG_BUFFER[0].ADDR_HI (08904) context 0 RB_COLOR_FLAG_BUFFER[0].ADDR_HI: 0x1 write RB_COLOR_FLAG_BUFFER[0].PITCH (08905) context 0 RB_COLOR_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } - 02124: 00000007 00000000 90522410 00000008 + 02150: 00000007 00000000 90522410 00000008 write RB_MRT[0x1].BUF_INFO (0882a) context 0 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = FMT6_5_6_5_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX } write RB_MRT[0x1].PITCH (0882b) context 0 RB_MRT[0x1].PITCH: 256 - 02128: 00000c3b 00000010 82b220a8 00000008 + 02160: 00000c3b 00000010 82b220a8 00000008 write RB_MRT[0x1].ARRAY_PITCH (0882c) context 0 RB_MRT[0x1].ARRAY_PITCH: 20480 write RB_MRT[0x1].BASE (0882d) context 0 RB_MRT[0x1].BASE: 0xaf000 - 0212c: 00000503 002bc000 82d220b0 00000008 + 02170: 00000503 002bc000 82d220b0 00000008 write RB_MRT[0x1].BASE_HI (0882e) context 0 RB_MRT[0x1].BASE_HI: 0x1 write RB_MRT[0x1].BASE_GMEM (0882f) context 0 RB_MRT[0x1].BASE_GMEM: 0x52000 - 01e10: 00000007 00148000 82f220b8 00000008 + 01e00: 00000007 00148000 82f220b8 00000008 write RB_COLOR_FLAG_BUFFER[0x1].ADDR (08906) context 0 RB_COLOR_FLAG_BUFFER[0x1].ADDR: 0xae000 write RB_COLOR_FLAG_BUFFER[0x1].ADDR_HI (08907) context 0 RB_COLOR_FLAG_BUFFER[0x1].ADDR_HI: 0x1 - 01e14: 002b8003 00000004 90722418 00000008 + 01e10: 002b8003 00000004 90722418 00000008 write RB_COLOR_FLAG_BUFFER[0x1].PITCH (08908) context 0 RB_COLOR_FLAG_BUFFER[0x1].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } write RB_MRT[0x2].BUF_INFO (08832) context 0 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = FMT6_16_16_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX } - 01e18: 00010007 00000d0c 83222420 00000008 + 01e20: 00010007 00000d0c 83222420 00000008 write RB_MRT[0x2].PITCH (08833) context 0 RB_MRT[0x2].PITCH: 256 write RB_MRT[0x2].ARRAY_PITCH (08834) context 0 RB_MRT[0x2].ARRAY_PITCH: 20480 - 01e1c: 00000013 00000500 834220cc 00000008 + 01e30: 00000013 00000500 834220cc 00000008 write RB_MRT[0x2].BASE (08835) context 0 RB_MRT[0x2].BASE: 0xb6000 write RB_MRT[0x2].BASE_HI (08836) context 0 RB_MRT[0x2].BASE_HI: 0x1 - 01e20: 002d8003 00000004 836220d4 00000008 + 01e40: 002d8003 00000004 836220d4 00000008 write RB_MRT[0x2].BASE_GMEM (08837) context 0 RB_MRT[0x2].BASE_GMEM: 0 write RB_COLOR_FLAG_BUFFER[0x2].ADDR (08909) context 0 RB_COLOR_FLAG_BUFFER[0x2].ADDR: 0xb6000 - 01e24: 00000003 002d8000 909220dc 00000008 + 01e50: 00000003 002d8000 909220dc 00000008 write RB_COLOR_FLAG_BUFFER[0x2].ADDR_HI (0890a) context 0 RB_COLOR_FLAG_BUFFER[0x2].ADDR_HI: 0x1 write RB_COLOR_FLAG_BUFFER[0x2].PITCH (0890b) context 0 RB_COLOR_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } - 01e28: 00000007 00000000 90b22428 00000008 + 01e60: 00000007 00000000 90b22428 00000008 write RB_MRT[0x3].BUF_INFO (0883a) context 0 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = FMT6_16_16_16_16_SNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX } write RB_MRT[0x3].PITCH (0883b) context 0 RB_MRT[0x3].PITCH: 512 - 01e2c: 00000d87 00000020 83b220e8 00000008 + 01e70: 00000d87 00000020 83b220e8 00000008 write RB_MRT[0x3].ARRAY_PITCH (0883c) context 0 RB_MRT[0x3].ARRAY_PITCH: 40960 write RB_MRT[0x3].BASE (0883d) context 0 RB_MRT[0x3].BASE: 0xbf000 - 02410: 00000a03 002fc000 83d220f0 00000008 + 02400: 00000a03 002fc000 83d220f0 00000008 write RB_MRT[0x3].BASE_HI (0883e) context 0 RB_MRT[0x3].BASE_HI: 0x1 write RB_MRT[0x3].BASE_GMEM (0883f) context 0 RB_MRT[0x3].BASE_GMEM: 0x5c000 - 02414: 00000007 00170000 83f220f8 00000008 + 02410: 00000007 00170000 83f220f8 00000008 write RB_COLOR_FLAG_BUFFER[0x3].ADDR (0890c) context 0 RB_COLOR_FLAG_BUFFER[0x3].ADDR: 0xbf000 write RB_COLOR_FLAG_BUFFER[0x3].ADDR_HI (0890d) context 0 RB_COLOR_FLAG_BUFFER[0x3].ADDR_HI: 0x1 - 02418: 002fc003 00000004 90d22430 00000008 + 02420: 002fc003 00000004 90d22430 00000008 write RB_COLOR_FLAG_BUFFER[0x3].PITCH (0890e) context 0 RB_COLOR_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } write RB_SRGB_CNTL (0880f) context 0 RB_SRGB_CNTL: { 0 } - 0241c: 00000003 00000000 80f22438 00000008 + 02430: 00000003 00000000 80f22438 00000008 write RB_RENDER_CNTL (08801) context 0 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x2 } write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT | TS_WRITE } - 02420: 00080043 00000014 0e722004 00000080 + 02440: 00080043 00000014 0e722004 00000080 write EVENT_TS_ADDR (e8) pipe EVENT_TS_ADDR: 0x1000 write EVENT_TS_ADDR+0x1 (e9) pipe EVENT_TS_ADDR+0x1: 0x1 - 02424: 00004003 00000004 0e9003a0 000000c0 + 02450: 00004003 00000004 0e9003a0 000000c0 write EVENT_TS_CTRL (ea) pipe EVENT_TS_CTRL: { EVENT = CCU_FLUSH_COLOR } write EVENT_TS_DATA (eb) pipe EVENT_TS_DATA: 0 - 02428: 00001403 00000000 0eb003a8 000000c0 + 02460: 00001403 00000000 0eb003a8 000000c0 write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x22 } - 0242c: 00000002 00000088 60000000 0000000d + 02470: 00000002 00000088 60000000 0000000d write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x22 } - 01b90: 00000002 00000088 60100000 0000000d + 01b80: 00000002 00000088 60100000 0000000d write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT | TS_WRITE } write EVENT_TS_ADDR (e8) pipe EVENT_TS_ADDR: 0x1000 - 01b94: 00000017 00004000 0e80039c 000000c0 + 01b90: 00000017 00004000 0e80039c 000000c0 write EVENT_TS_ADDR+0x1 (e9) pipe EVENT_TS_ADDR+0x1: 0x1 write EVENT_TS_CTRL (ea) pipe EVENT_TS_CTRL: { EVENT = CCU_FLUSH_DEPTH } - 01b98: 00000007 00001000 0ea003a4 000000c0 + 01ba0: 00000007 00001000 0ea003a4 000000c0 write EVENT_TS_DATA (eb) pipe EVENT_TS_DATA: 0 - 01b9c: 00000002 00000000 0eb00000 00000080 + 01bb0: 00000002 00000000 0eb00000 00000080 write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x23 } - 01ba0: 00000002 0000008c 60000000 0000020d + 01bc0: 00000002 0000008c 60000000 0000020d write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x23 } - 01ba4: 00000002 0000008c 60100000 0000020d + 01bd0: 00000002 0000008c 60100000 0000020d write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT } - 01ba8: 00000002 00000004 0e700000 00000080 + 01be0: 00000002 00000004 0e700000 00000080 write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x24 } - 01bac: 00000002 00000090 60000000 0000000d + 01bf0: 00000002 00000090 60000000 0000000d write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x24 } - 02190: 00000002 00000090 60100000 0000000d + 02180: 00000002 00000090 60100000 0000000d write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT } - 02194: 00000002 00000004 0e700000 00000080 + 02190: 00000002 00000004 0e700000 00000080 write CP_EVENT_START (0d600) context 1 CP_EVENT_START: { STATE_ID = 0x25 } - 02198: 00000002 00000094 60000000 0000020d + 021a0: 00000002 00000094 60000000 0000020d write CP_EVENT_END (0d601) context 1 CP_EVENT_END: { STATE_ID = 0x25 } - 0219c: 00000002 00000094 60100000 0000020d + 021b0: 00000002 00000094 60100000 0000020d write EVENT_CMD (e7) pipe EVENT_CMD: { EVENT_TYPE = EVENT } - 021a0: 00000002 00000004 0e700000 00000080 + 021c0: 00000002 00000004 0e700000 00000080 write CP_EVENT_START (0d600) context 0 CP_EVENT_START: { STATE_ID = 0x26 } - 021a4: 00000002 00000098 60000000 0000000d + 021d0: 00000002 00000098 60000000 0000000d write CP_EVENT_END (0d601) context 0 CP_EVENT_END: { STATE_ID = 0x26 } - 021a8: 00000002 00000098 60100000 0000000d - 021ac: 00000000 00000000 00000000 00000000 + 021e0: 00000002 00000098 60100000 0000000d + 021f0: 00000000 00000000 00000000 00000000 write RBBM_WAIT_FOR_GPU_IDLE_CMD (0001c) context 0 RBBM_WAIT_FOR_GPU_IDLE_CMD: { WAIT_GPU_IDLE } write WFI_PEND_DECR (81) pipe - 02710: 00000007 00000004 08100070 00000080 - 02714: 00000000 00000000 00000000 00000000 + 02700: 00000007 00000004 08100070 00000080 + 02710: 00000000 00000000 00000000 00000000 shader-blocks: - type: A6XX_TP0_TMO_DATA