fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-30 20:50:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/miptree: Add and use a memset option in alloc_aux_buffer

Browse source 
Add infrastructure for initializing the clear color BO.
intel_miptree_init_mcs is no longer needed with change.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Nanley Chery 2018-04-30 10:44:01 -07:00
parent 8a9491058d
commit b58675e93f
1 changed files with 31 additions and 37 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

68
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -1655,41 +1655,13 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
}
static bool
intel_miptree_init_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int init_value)
{
assert(mt->aux_buf != NULL);
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
* When MCS buffer is enabled and bound to MSRT, it is required that it
* is cleared prior to any rendering.
*
* Since we don't use the MCS buffer for any purpose other than rendering,
* it makes sense to just clear it immediately upon allocation.
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
if (unlikely(map == NULL)) {
fprintf(stderr, "Failed to map mcs buffer into GTT\n");
intel_miptree_aux_buffer_free(mt->aux_buf);
mt->aux_buf = NULL;
return false;
}
void *data = map;
memset(data, init_value, mt->aux_buf->surf.size);
brw_bo_unmap(mt->aux_buf->bo);
return true;
}
static struct intel_miptree_aux_buffer *
intel_alloc_aux_buffer(struct brw_context *brw,
const char *name,
const struct isl_surf *aux_surf,
uint32_t alloc_flags,
bool wants_memset,
uint8_t memset_value,
struct intel_mipmap_tree *mt)
{
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
@ -1720,6 +1692,19 @@ intel_alloc_aux_buffer(struct brw_context *brw,
return NULL;
}
/* Initialize the bo to the desired value */
if (wants_memset) {
assert(!(alloc_flags & BO_ALLOC_BUSY));
void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
if (map == NULL) {
intel_miptree_aux_buffer_free(buf);
return NULL;
}
memset(map, memset_value, aux_surf->size);
brw_bo_unmap(buf->bo);
}
if (devinfo->gen >= 10) {
buf->clear_color_bo = buf->bo;
brw_bo_reference(buf->clear_color_bo);
@ -1758,10 +1743,19 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
* to be just used by the GPU.
*/
const uint32_t alloc_flags = 0;
mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
&temp_mcs_surf, alloc_flags, mt);
if (!mt->aux_buf ||
!intel_miptree_init_mcs(brw, mt, 0xFF)) {
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
* When MCS buffer is enabled and bound to MSRT, it is required that it
* is cleared prior to any rendering.
*
* Since we don't use the MCS buffer for any purpose other than rendering,
* it makes sense to just clear it immediately upon allocation.
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree", &temp_mcs_surf,
alloc_flags, true, 0xFF, mt);
if (!mt->aux_buf) {
free(aux_state);
return false;
}
@ -1805,7 +1799,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* bits in the aux buffer.
*/
mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf,
BO_ALLOC_ZEROED, mt);
BO_ALLOC_ZEROED, false, 0, mt);
if (!mt->aux_buf) {
free(aux_state);
return false;
@ -1871,8 +1865,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
assert(ok);
const uint32_t alloc_flags = BO_ALLOC_BUSY;
mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
&temp_hiz_surf, alloc_flags, mt);
mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree", &temp_hiz_surf,
alloc_flags, false, 0, mt);
if (!mt->aux_buf) {
free(aux_state);