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ir3: Bump type mismatch penalty to 3

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After some experimentation with computerator, it seems on a618 that
writing a full register and then reading half of it as a half register
requires a delay of 6, the same as the delay for cat5/cat6 sources. The
other direction only has a delay of 5, but just bump it unconditionally
out of an abundance of caution.

Fixes: 890de1a436 ("ir3/delay: Fix full->half and half->full delay")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14246>
(cherry picked from commit 603791bdeb)
This commit is contained in:
Connor Abbott 2022-01-06 20:16:44 +01:00 • committed by Eric Engestrom
parent d761347e05
commit b57693c541
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -1255,7 +1255,7 @@
"description": "ir3: Bump type mismatch penalty to 3",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "890de1a43603c98b5788f9867ff0793f117b5f4b"
},

2
src/freedreno/ir3/ir3_delay.c
View file

@ -98,7 +98,7 @@ ir3_delayslots(struct ir3_instruction *assigner,
*/
bool mismatched_half = (assigner->dsts[0]->flags & IR3_REG_HALF) !=
(consumer->srcs[n]->flags & IR3_REG_HALF);
unsigned penalty = mismatched_half ? 2 : 0;
unsigned penalty = mismatched_half ? 3 : 0;
if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) && (n == 2)) {
/* special case, 3rd src to cat3 not required on first cycle */
return 1 + penalty;