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radeonsi/sqtt: rework pm4.reg_va_low_idx

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The initial logic was to remember the place were SPI_SHADER_PGM_LO_*
are written, then assume that we can get the register offset because
the sequence would always be:

   PKT3_SET_SH_REG
   SPI_SHADER_PGM_LO_* register offset
   VA low 32 bits value <- reg_va_low_idx

The problem is that this sequence isn't guaranteed, for instance we
can get this instead:

   0   c0067600 |
   1   00000046 |
   2   003ffffd | SPI_SHADER_PGM_RSRC3_VS
   3   00000020 | SPI_SHADER_LATE_ALLOC_VS
   4 * 00002080 | SPI_SHADER_PGM_LO_VS
   5   00000080 | SPI_SHADER_PGM_HI_VS

So the assert in si_state_draw.cpp would fail as well as the VA
update logic.

So instead remember which the SPI_SHADER_PGM_LO_* offset, and the low
32 bits of the VA in si_update_shaders.

Fixes: 8034a71430 ("radeonsi/sqtt: re-export shaders in a single bo")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26774>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2023-11-07 16:05:52 +01:00 • committed by Marge Bot
parent e4d537fb84
commit b55a2065e0
4 changed files with 7 additions and 7 deletions
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5
src/gallium/drivers/radeonsi/si_pm4.c
View file

@ -135,7 +135,7 @@ void si_pm4_finalize(struct si_pm4_state *state)
if (strstr(ac_get_register_name(state->screen->info.gfx_level,
state->screen->info.family, reg_offset),
"SPI_SHADER_PGM_LO_")) {
state->reg_va_low_idx = get_packed_reg_valueN_idx(state, i);
state->spi_shader_pgm_lo_reg = reg_offset;
break;
}
}
@ -158,7 +158,8 @@ void si_pm4_finalize(struct si_pm4_state *state)
if (strstr(ac_get_register_name(state->screen->info.gfx_level,
state->screen->info.family, reg_base_offset + i * 4),
"SPI_SHADER_PGM_LO_")) {
state->reg_va_low_idx = state->last_pm4 + 2 + i;
state->spi_shader_pgm_lo_reg = reg_base_offset + i * 4;
break;
}
}

2
src/gallium/drivers/radeonsi/si_pm4.h
View file

@ -45,7 +45,7 @@ struct si_pm4_state {
uint16_t max_dw;
/* Used by SQTT to override the shader address */
uint16_t reg_va_low_idx;
uint32_t spi_shader_pgm_lo_reg;
/* This must be the last field because the array can continue after the structure. */
uint32_t pm4[64];

5
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -370,9 +370,8 @@ static bool si_update_shaders(struct si_context *sctx)
struct si_pm4_state *pm4 = &shader->pm4;
uint32_t va_low = (pipeline->bo->gpu_address + pipeline->offset[i]) >> 8;
assert(PKT3_IT_OPCODE_G(pm4->pm4[pm4->reg_va_low_idx - 2]) == PKT3_SET_SH_REG);
uint32_t reg = (pm4->pm4[pm4->reg_va_low_idx - 1] << 2) + SI_SH_REG_OFFSET;
uint64_t va_low = (pipeline->bo->gpu_address + pipeline->offset[i]) >> 8;
uint32_t reg = pm4->spi_shader_pgm_lo_reg;
si_pm4_set_reg(&pipeline->pm4, reg, va_low);
}
}

2
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -2096,7 +2096,7 @@ static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader
assert(0);
}
assert(!(sscreen->debug_flags & DBG(SQTT)) || shader->pm4.reg_va_low_idx != 0);
assert(!(sscreen->debug_flags & DBG(SQTT)) || shader->pm4.spi_shader_pgm_lo_reg != 0);
}
static void si_clear_vs_key_inputs(struct si_context *sctx, union si_shader_key *key,