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r600g: fix z/stencil texture creation v2
z or stencil texture should not be created with the z/stencil flags for surface creation as they are intended to be bound as texture. v2: remove broken code Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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988ad7831c
commit
b4f0ab0b22
1 changed files with 17 additions and 15 deletions
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@ -237,7 +237,7 @@ static void r600_texture_set_array_mode(struct pipe_screen *screen,
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static int r600_init_surface(struct radeon_surface *surface,
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const struct pipe_resource *ptex,
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unsigned array_mode)
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unsigned array_mode, bool is_transfer)
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{
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surface->npix_x = ptex->width0;
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surface->npix_y = ptex->height0;
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@ -298,7 +298,7 @@ static int r600_init_surface(struct radeon_surface *surface,
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if (ptex->bind & PIPE_BIND_SCANOUT) {
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surface->flags |= RADEON_SURF_SCANOUT;
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}
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if (util_format_is_depth_and_stencil(ptex->format)) {
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if (util_format_is_depth_and_stencil(ptex->format) && !is_transfer) {
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surface->flags |= RADEON_SURF_ZBUFFER;
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surface->flags |= RADEON_SURF_SBUFFER;
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}
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@ -316,11 +316,6 @@ static int r600_setup_surface(struct pipe_screen *screen,
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unsigned i;
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int r;
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if (util_format_is_depth_or_stencil(rtex->real_format)) {
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rtex->surface.flags |= RADEON_SURF_ZBUFFER;
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rtex->surface.flags |= RADEON_SURF_SBUFFER;
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}
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r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
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if (r) {
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return r;
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@ -572,7 +567,8 @@ r600_texture_create_object(struct pipe_screen *screen,
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r600_setup_miptree(screen, rtex, array_mode);
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if (rscreen->use_surface_alloc) {
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rtex->surface = *surface;
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r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
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r = r600_setup_surface(screen, rtex, array_mode,
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pitch_in_bytes_override);
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if (r) {
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FREE(rtex);
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return NULL;
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@ -642,7 +638,8 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
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}
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}
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r = r600_init_surface(&surface, templ, array_mode);
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r = r600_init_surface(&surface, templ, array_mode,
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templ->flags & R600_RESOURCE_FLAG_TRANSFER);
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if (r) {
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return NULL;
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}
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@ -723,7 +720,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
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else
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array_mode = 0;
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r = r600_init_surface(&surface, templ, array_mode);
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r = r600_init_surface(&surface, templ, array_mode, 0);
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if (r) {
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return NULL;
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}
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@ -796,8 +793,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
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* the CPU is much happier reading out of cached system memory
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* than uncached VRAM.
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*/
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if (R600_TEX_IS_TILED(rtex, level))
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if (R600_TEX_IS_TILED(rtex, level)) {
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use_staging_texture = TRUE;
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}
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if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
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use_staging_texture = TRUE;
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@ -805,15 +803,18 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
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/* Use a staging texture for uploads if the underlying BO is busy. */
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if (!(usage & PIPE_TRANSFER_READ) &&
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(rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
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rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE)))
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rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
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use_staging_texture = TRUE;
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}
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if (!permit_hardware_blit(ctx->screen, texture) ||
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(texture->flags & R600_RESOURCE_FLAG_TRANSFER))
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(texture->flags & R600_RESOURCE_FLAG_TRANSFER)) {
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use_staging_texture = FALSE;
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}
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if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
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if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
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return NULL;
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}
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trans = CALLOC_STRUCT(r600_transfer);
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if (trans == NULL)
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@ -898,8 +899,9 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
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}
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if (rtex->is_depth && !rtex->is_flushing_texture) {
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if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
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if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) {
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r600_blit_push_depth(ctx, rtex);
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}
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}
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pipe_resource_reference(&transfer->resource, NULL);
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