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radv: add MSAA support to CopyImage() on compute queue
CopyImage supports copying MSAA images if the number of samples match. Found by inspection because this is untested by CTS for some reasons. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10055>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
4caf19eb7d
commit
b4a66b29cd
2 changed files with 84 additions and 55 deletions
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@ -617,9 +617,10 @@ radv_device_finish_meta_btoi_r32g32b32_state(struct radv_device *device)
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}
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static nir_shader *
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build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
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build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples)
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{
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enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
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bool is_multisampled = samples > 1;
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enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : is_multisampled ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
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const struct glsl_type *buf_type = glsl_sampler_type(dim,
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false,
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false,
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@ -627,7 +628,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
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const struct glsl_type *img_type = glsl_image_type(dim,
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false,
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GLSL_TYPE_FLOAT);
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nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, is_3d ? "meta_itoi_cs_3d" : "meta_itoi_cs");
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nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, is_3d ? "meta_itoi_cs_3d-%d" : "meta_itoi_cs-%d", samples);
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b.shader->info.cs.local_size[0] = 8;
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b.shader->info.cs.local_size[1] = 8;
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b.shader->info.cs.local_size[2] = 1;
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@ -658,38 +659,78 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
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nir_ssa_def *dst_coord = nir_iadd(&b, global_id, dst_offset);
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
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tex->sampler_dim = dim;
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tex->op = nir_texop_txf;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, is_3d ? 0x7 : 0x3));
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tex->src[1].src_type = nir_tex_src_lod;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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tex->dest_type = nir_type_float32;
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tex->is_array = false;
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tex->coord_components = is_3d ? 3 : 2;
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nir_tex_instr *tex_instr[8];
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for (uint32_t i = 0; i < samples; i++) {
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tex_instr[i] = nir_tex_instr_create(b.shader, is_multisampled ? 4 : 3);
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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nir_tex_instr *tex = tex_instr[i];
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tex->sampler_dim = dim;
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tex->op = is_multisampled ? nir_texop_txf_ms : nir_texop_txf;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, is_3d ? 0x7 : 0x3));
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tex->src[1].src_type = nir_tex_src_lod;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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if (is_multisampled) {
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tex->src[3].src_type = nir_tex_src_ms_index;
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tex->src[3].src = nir_src_for_ssa(nir_imm_int(&b, i));
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}
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tex->dest_type = nir_type_float32;
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tex->is_array = false;
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tex->coord_components = is_3d ? 3 : 2;
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nir_ssa_def *outval = &tex->dest.ssa;
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
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dst_coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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}
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for (uint32_t i = 0; i < samples; i++) {
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nir_ssa_def *outval = &tex_instr[i]->dest.ssa;
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
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dst_coord, nir_imm_int(&b, i), outval, nir_imm_int(&b, 0));
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}
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return b.shader;
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}
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static VkResult
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create_itoi_pipeline(struct radv_device *device,
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int samples,
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VkPipeline *pipeline)
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{
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struct radv_meta_state *state = &device->meta_state;
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nir_shader *cs = build_nir_itoi_compute_shader(device, false, samples);
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VkResult result;
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = state->itoi.img_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&state->cache),
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1, &vk_pipeline_info, NULL,
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pipeline);
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ralloc_free(cs);
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return result;
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}
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/* image to image - don't write use image accessors */
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static VkResult
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radv_device_init_meta_itoi_state(struct radv_device *device)
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{
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VkResult result;
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nir_shader *cs = build_nir_itoi_compute_shader(device, false);
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nir_shader *cs_3d = NULL;
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if (device->physical_device->rad_info.chip_class >= GFX9)
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cs_3d = build_nir_itoi_compute_shader(device, true);
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/*
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* two descriptors one for the image being sampled
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* one for the buffer being written.
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@ -739,31 +780,17 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
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if (result != VK_SUCCESS)
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goto fail;
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.itoi.img_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &vk_pipeline_info, NULL,
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&device->meta_state.itoi.pipeline);
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if (result != VK_SUCCESS)
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goto fail;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) {
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uint32_t samples = 1 << i;
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result = create_itoi_pipeline(device, samples,
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&device->meta_state.itoi.pipeline[i]);
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if (result != VK_SUCCESS)
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goto fail;
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}
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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nir_shader *cs_3d = build_nir_itoi_compute_shader(device, true, 1);
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VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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@ -783,15 +810,11 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &vk_pipeline_info_3d, NULL,
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&device->meta_state.itoi.pipeline_3d);
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ralloc_free(cs_3d);
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}
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ralloc_free(cs);
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return VK_SUCCESS;
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fail:
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ralloc_free(cs);
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ralloc_free(cs_3d);
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return result;
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}
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@ -805,8 +828,12 @@ radv_device_finish_meta_itoi_state(struct radv_device *device)
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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state->itoi.img_ds_layout,
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&state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->itoi.pipeline, &state->alloc);
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->itoi.pipeline[i], &state->alloc);
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}
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if (device->physical_device->rad_info.chip_class >= GFX9)
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->itoi.pipeline_3d, &state->alloc);
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@ -1899,9 +1926,10 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
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unsigned num_rects,
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struct radv_meta_blit2d_rect *rects)
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{
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VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline;
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struct radv_device *device = cmd_buffer->device;
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struct radv_image_view src_view, dst_view;
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uint32_t samples = src->image->info.samples;
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uint32_t samples_log2 = ffs(samples) - 1;
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if (src->format == VK_FORMAT_R32G32B32_UINT ||
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src->format == VK_FORMAT_R32G32B32_SINT ||
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@ -1916,6 +1944,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
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itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
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VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline[samples_log2];
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if (device->physical_device->rad_info.chip_class >= GFX9 &&
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(src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D))
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pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
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@ -533,7 +533,7 @@ struct radv_meta_state {
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struct {
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VkPipelineLayout img_p_layout;
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VkDescriptorSetLayout img_ds_layout;
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VkPipeline pipeline;
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VkPipeline pipeline[MAX_SAMPLES_LOG2];
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VkPipeline pipeline_3d;
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} itoi;
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struct {
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