diff --git a/src/freedreno/common/fd6_pack.h b/src/freedreno/common/fd6_pack.h
index b4805809d10..630cc145204 100644
--- a/src/freedreno/common/fd6_pack.h
+++ b/src/freedreno/common/fd6_pack.h
@@ -74,7 +74,6 @@ __reg_iova(const struct fd_reg_pair *reg)
             uint64_t *__p64 = (uint64_t *)__p;                                 \
             *__p64 = __reg_iova(&__regs[i]) | __regs[i].value;                 \
             __p += 2;                                                          \
-            fd_ringbuffer_attach_bo(ring, __regs[i].bo);                       \
          } else {                                                              \
             *__p++ = __regs[i].value;                                          \
             if (__regs[i].is_address)                                          \
diff --git a/src/freedreno/drm/freedreno_ringbuffer.h b/src/freedreno/drm/freedreno_ringbuffer.h
index 49652d72a23..8c131750d78 100644
--- a/src/freedreno/drm/freedreno_ringbuffer.h
+++ b/src/freedreno/drm/freedreno_ringbuffer.h
@@ -319,7 +319,6 @@ OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo, uint32_t offset,
    uint64_t *cur = (uint64_t *)ring->cur;
    *cur = iova;
    ring->cur += 2;
-   fd_ringbuffer_attach_bo(ring, bo);
 #else
    struct fd_reloc reloc = {
          .bo = bo,
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
index 4d356f9147d..7147b7efb37 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
@@ -904,17 +904,24 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
     */
    if (batch->tessellation) {
       assert(screen->tess_bo);
+      fd_ringbuffer_attach_bo(ring, screen->tess_bo);
       OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR, 2);
       OUT_RELOC(ring, screen->tess_bo, 0, 0, 0);
       /* Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it. */
       OUT_WFI5(ring);
    }
 
+   struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
+   struct fd_bo *bcolor_mem = fd6_ctx->bcolor_mem;
    OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, 2);
-   OUT_RELOC(ring, fd6_context(batch->ctx)->bcolor_mem, 0, 0, 0);
+   OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
 
    OUT_PKT4(ring, REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, 2);
-   OUT_RELOC(ring, fd6_context(batch->ctx)->bcolor_mem, 0, 0, 0);
+   OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
+
+   fd_ringbuffer_attach_bo(ring, bcolor_mem);
+
+   fd_ringbuffer_attach_bo(ring, fd6_ctx->control_mem);
 
    if (!batch->nondraw) {
       trace_end_state_restore(&batch->trace, ring);
@@ -942,6 +949,8 @@ fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
       dst_off += 4;
       src_off += 4;
    }
+   fd_ringbuffer_attach_bo(ring, dst_bo);
+   fd_ringbuffer_attach_bo(ring, src_bo);
 }
 
 void
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
index 780552d0ae1..70f5d2f9c1d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
@@ -255,6 +255,7 @@ emit_lrz(struct fd_batch *batch, struct fd_batch_subpass *subpass)
    OUT_REG(ring, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = subpass->lrz),
            A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = zsbuf->lrz_pitch),
            A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
+   fd_ringbuffer_attach_bo(ring, subpass->lrz);
 }
 
 /* Emit any needed lrz clears to the prologue cmds
@@ -568,6 +569,9 @@ update_vsc_pipe(struct fd_batch *batch)
       ring, A6XX_VSC_DRAW_STRM_ADDRESS(.bo = fd6_ctx->vsc_draw_strm),
       A6XX_VSC_DRAW_STRM_PITCH(.dword = fd6_ctx->vsc_draw_strm_pitch),
       A6XX_VSC_DRAW_STRM_LIMIT(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
+
+   fd_ringbuffer_attach_bo(ring, fd6_ctx->vsc_draw_strm);
+   fd_ringbuffer_attach_bo(ring, fd6_ctx->vsc_prim_strm);
 }
 
 /*
@@ -713,6 +717,9 @@ emit_common_fini(struct fd_batch *batch)
    if (!result)
       return;
 
+   // TODO attach directly to submit:
+   fd_ringbuffer_attach_bo(ring, at->results_mem);
+
    OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
    OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
 
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.cc b/src/gallium/drivers/freedreno/a6xx/fd6_image.cc
index 7e1a371f10c..2c3b189cb74 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_image.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.cc
@@ -202,16 +202,12 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
       struct pipe_shader_buffer *buf = &bufso->sb[b];
       unsigned idx = b + IR3_BINDLESS_SSBO_OFFSET;
       validate_buffer_descriptor(ctx, set, idx, buf);
-      if (buf->buffer)
-         fd_ringbuffer_attach_bo(ring, fd_resource(buf->buffer)->bo);
    }
 
    u_foreach_bit (b, imgso->enabled_mask) {
       struct pipe_image_view *img = &imgso->si[b];
       unsigned idx = b + IR3_BINDLESS_IMAGE_OFFSET;
       validate_image_descriptor(ctx, set, idx, img);
-      if (img->resource)
-         fd_ringbuffer_attach_bo(ring, fd_resource(img->resource)->bo);
    }
 
    if (!set->bo) {
@@ -258,6 +254,8 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
 
    unsigned idx = ir3_shader_descriptor_set(shader);
 
+   fd_ringbuffer_attach_bo(ring, set->bo);
+
    if (shader == PIPE_SHADER_COMPUTE) {
       OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .cs_bindless = 0x1f));
       OUT_REG(ring, SP_CS_BINDLESS_BASE_DESCRIPTOR(CHIP,
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc
index a85c9531f18..8cdafd99303 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc
@@ -133,6 +133,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
    OUT_RING(ring, A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(per_fiber_size));
    if (so->pvtmem_size > 0) { /* SP_xS_PVT_MEM_ADDR */
       OUT_RELOC(ring, ctx->pvtmem[so->pvtmem_per_wave].bo, 0, 0, 0);
+      fd_ringbuffer_attach_bo(ring, ctx->pvtmem[so->pvtmem_per_wave].bo);
    } else {
       OUT_RING(ring, 0);
       OUT_RING(ring, 0);
@@ -154,6 +155,8 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
                      CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
                      CP_LOAD_STATE6_0_NUM_UNIT(shader_preload_size));
    OUT_RELOC(ring, so->bo, 0, 0, 0);
+
+   fd_ringbuffer_attach_bo(ring, so->bo);
 }
 
 /**
diff --git a/src/gallium/drivers/freedreno/freedreno_batch.c b/src/gallium/drivers/freedreno/freedreno_batch.c
index 48db74fa2e9..d2023caeb8e 100644
--- a/src/gallium/drivers/freedreno/freedreno_batch.c
+++ b/src/gallium/drivers/freedreno/freedreno_batch.c
@@ -498,6 +498,12 @@ fd_batch_add_resource(struct fd_batch *batch, struct fd_resource *rsc)
 
    _mesa_set_add_pre_hashed(batch->resources, rsc->hash, rsc);
    rsc->track->batch_mask |= (1 << batch->idx);
+
+   fd_ringbuffer_attach_bo(batch->draw, rsc->bo);
+   if (unlikely(rsc->b.b.next)) {
+      struct fd_resource *n = fd_resource(rsc->b.b.next);
+      fd_ringbuffer_attach_bo(batch->draw, n->bo);
+   }
 }
 
 void