From b4055a020fff2f3e5feb267c4be8e701a995d166 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 2 Sep 2020 14:59:29 -0700 Subject: [PATCH] intel/compiler: Regroup TCS barrier code paths Rearrange if/else fragments to unify case for Gen11 or later platforms. This will help the code look cleaner for adding unified barrier support to TCS. Signed-off-by: Jordan Justen Reviewed-by: Sagar Ghuge Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 10d3f0eece2..58fb065a1dd 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -2824,25 +2824,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld, /* Zero the message header */ bld.exec_all().MOV(m0, brw_imm_ud(0u)); - if (devinfo->ver < 11) { + if (devinfo->ver >= 11) { + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), + brw_imm_ud(INTEL_MASK(30, 24))); + + /* Set the Barrier Count and the enable bit */ + chanbld.OR(m0_2, m0_2, + brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15))); + } else { /* Copy "Barrier ID" from r0.2, bits 16:13 */ chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), brw_imm_ud(INTEL_MASK(16, 13))); /* Shift it up to bits 27:24. */ chanbld.SHL(m0_2, m0_2, brw_imm_ud(11)); - } else { - chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(30, 24))); - } - /* Set the Barrier Count and the enable bit */ - if (devinfo->ver < 11) { + /* Set the Barrier Count and the enable bit */ chanbld.OR(m0_2, m0_2, brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15))); - } else { - chanbld.OR(m0_2, m0_2, - brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15))); } bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);