From b404ca0eb0f2c661cfd2985852ca4e7df8cdf847 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Mon, 24 Jun 2024 16:09:57 -0400 Subject: [PATCH] intel: Don't use HW clear color conversion on gfx11 The hardware's clear color conversion feature unfortunately requires invalidating the texture cache for every fast clear. To avoid the performance penalty that comes with the invalidation, avoid using the hardware feature and write out the converted clear color pixel ourselves. When testing a patch which moves a state cache invalidate to occur after fast clears instead of before, this prevents the following failures on icl/zink: * piglit.fast_color_clear.fcc-read-after-clear sample tex * piglit.spec.arb_clear_texture.arb_clear_texture-cube Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/blorp/blorp_genX_exec_brw.h | 41 +++++++++------------------ src/intel/isl/isl_surface_state.c | 20 ------------- 2 files changed, 13 insertions(+), 48 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec_brw.h b/src/intel/blorp/blorp_genX_exec_brw.h index d961ecd1bfe..d335724f841 100644 --- a/src/intel/blorp/blorp_genX_exec_brw.h +++ b/src/intel/blorp/blorp_genX_exec_brw.h @@ -1513,36 +1513,21 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, const struct blorp_surface_info *info) { assert(info->clear_color_addr.buffer != NULL); + + uint32_t pixel[4]; + isl_color_value_pack(&info->clear_color, info->surf.format, pixel); + #if GFX_VER == 11 - /* 2 QWORDS */ - const unsigned inlinedata_dw = 2 * 2; - const unsigned num_dwords = GENX(MI_ATOMIC_length) + inlinedata_dw; - - struct blorp_address clear_addr = info->clear_color_addr; - uint32_t *dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, - .DataSize = MI_ATOMIC_QWORD, - .ATOMICOPCODE = MI_ATOMIC_OP_MOVE8B, - .InlineData = true, - .MemoryAddress = clear_addr); - /* dw starts at dword 1, but we need to fill dwords 3 and 5 */ + uint32_t *dw = blorp_emitn(batch, GENX(MI_STORE_DATA_IMM), 3 + 6, + .StoreQword = true, + .Address = info->clear_color_addr); + /* dw starts at dword 1 */ dw[2] = info->clear_color.u32[0]; - dw[3] = 0; - dw[4] = info->clear_color.u32[1]; - dw[5] = 0; - - clear_addr.offset += 8; - dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, - .DataSize = MI_ATOMIC_QWORD, - .ATOMICOPCODE = MI_ATOMIC_OP_MOVE8B, - .CSSTALL = true, - .ReturnDataControl = true, - .InlineData = true, - .MemoryAddress = clear_addr); - /* dw starts at dword 1, but we need to fill dwords 3 and 5 */ - dw[2] = info->clear_color.u32[2]; - dw[3] = 0; - dw[4] = info->clear_color.u32[3]; - dw[5] = 0; + dw[3] = info->clear_color.u32[1]; + dw[4] = info->clear_color.u32[2]; + dw[5] = info->clear_color.u32[3]; + dw[6] = pixel[0]; + dw[7] = pixel[1]; #else diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 9857976debe..5e5688b4de1 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -895,26 +895,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif } -#if GFX_VER == 11 - /* - * From BXML > GT > Shared Functions > vol5c Shared Functions > - * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable: - * - * Project: Gfx11 - * - * "Enables Pixel backend hw to convert clear values into native format - * and write back to clear address, so that display and sampler can use - * the converted value for resolving fast cleared RTs." - * - * Summary: - * Clear color conversion must be enabled if the clear color is stored - * indirectly and fast color clears are enabled. - */ - if (info->use_clear_address) { - s.ClearColorConversionEnable = true; - } -#endif - #if GFX_VER >= 20 /* According to Bspec 57023 >> RENDER_SURFACE_STATE, the clear value * address and explicit clear value are removed since Xe2.