diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 7df2aea5c5b..3e994b997e9 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -579,6 +579,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_ubo_vec4: case nir_intrinsic_ldc_nv: case nir_intrinsic_ldcx_nv: + case nir_intrinsic_load_texel_buf_index_address_pan: is_divergent = (src_divergent(instr->src[0], state) && (nir_intrinsic_access(instr) & ACCESS_NON_UNIFORM)) || src_divergent(instr->src[1], state); @@ -622,6 +623,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_get_ssbo_size: case nir_intrinsic_ssbo_descriptor_amd: case nir_intrinsic_deref_buffer_array_length: + case nir_intrinsic_load_texel_buf_conv_pan: is_divergent = src_divergent(instr->src[0], state) && (nir_intrinsic_access(instr) & ACCESS_NON_UNIFORM); break; @@ -727,6 +729,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_vulkan_descriptor: case nir_intrinsic_load_input_attachment_target_pan: case nir_intrinsic_load_input_attachment_conv_pan: + case nir_intrinsic_load_converted_mem_pan: case nir_intrinsic_atomic_counter_read: case nir_intrinsic_atomic_counter_read_deref: case nir_intrinsic_quad_swizzle_amd: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 5e7284d6c1c..8f3c471a4d1 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1665,6 +1665,22 @@ load("converted_output_pan", [1, 1, 1], indices=[ACCESS, DEST_TYPE, IO_SEMANTICS # and is ignored otherwise load("readonly_output_pan", [1, 1, 1], indices=[ACCESS, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) +# Load converted memory given an address and a conversion descriptor +# src[] = { address, conversion } +load("converted_mem_pan", [1, 1], indices=[DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) + +# Store a value to memory with conversion given an address and a conversion descriptor +# src[] = { value, address, conversion } +store("converted_mem_pan", [1, 1], indices=[IO_SEMANTICS]) + +# Load the address of a texel buffer index +# src[] = { resource_handle, index } +intrinsic("load_texel_buf_index_address_pan", [1, 1], dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[64]) + +# Load conversion descriptor for a texel buffer +# src[] = { resource_handle } +intrinsic("load_texel_buf_conv_pan", [1], dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) + # Load input attachment target # src[] = { input_attachment_index } # valid targets are: