mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-04 01:08:03 +02:00
broadcom/compiler: use imm-helpers
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
This commit is contained in:
parent
c69dc01796
commit
b3b3be55c4
3 changed files with 19 additions and 19 deletions
|
|
@ -109,8 +109,8 @@ v3d_nir_lower_uniform(struct v3d_compile *c, nir_builder *b,
|
|||
|
||||
nir_instr_rewrite_src(&intr->instr,
|
||||
&intr->src[0],
|
||||
nir_src_for_ssa(nir_ishl(b, intr->src[0].ssa,
|
||||
nir_imm_int(b, 4))));
|
||||
nir_src_for_ssa(nir_ishl_imm(b, intr->src[0].ssa,
|
||||
4)));
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -185,7 +185,7 @@ v3d_nir_lower_vpm_output(struct v3d_compile *c, nir_builder *b,
|
|||
if (location == VARYING_SLOT_LAYER) {
|
||||
assert(c->s->info.stage == MESA_SHADER_GEOMETRY);
|
||||
nir_ssa_def *header = nir_load_var(b, state->gs.header_var);
|
||||
header = nir_iand(b, header, nir_imm_int(b, 0xff00ffff));
|
||||
header = nir_iand_imm(b, header, 0xff00ffff);
|
||||
|
||||
/* From the GLES 3.2 spec:
|
||||
*
|
||||
|
|
@ -210,7 +210,7 @@ v3d_nir_lower_vpm_output(struct v3d_compile *c, nir_builder *b,
|
|||
nir_ssa_def *layer_id =
|
||||
nir_bcsel(b, cond,
|
||||
nir_imm_int(b, 0),
|
||||
nir_ishl(b, src, nir_imm_int(b, 16)));
|
||||
nir_ishl_imm(b, src, 16));
|
||||
header = nir_ior(b, header, layer_id);
|
||||
nir_store_var(b, state->gs.header_var, header, 0x1);
|
||||
}
|
||||
|
|
@ -275,13 +275,13 @@ v3d_nir_lower_emit_vertex(struct v3d_compile *c, nir_builder *b,
|
|||
|
||||
/* Update VPM offset for next vertex output data and header */
|
||||
output_offset =
|
||||
nir_iadd(b, output_offset,
|
||||
nir_imm_int(b, state->gs.output_vertex_data_size));
|
||||
nir_iadd_imm(b, output_offset,
|
||||
state->gs.output_vertex_data_size);
|
||||
|
||||
header_offset = nir_iadd(b, header_offset, nir_imm_int(b, 1));
|
||||
header_offset = nir_iadd_imm(b, header_offset, 1);
|
||||
|
||||
/* Reset the New Primitive bit */
|
||||
header = nir_iand(b, header, nir_imm_int(b, 0xfffffffe));
|
||||
header = nir_iand_imm(b, header, 0xfffffffe);
|
||||
|
||||
nir_store_var(b, state->gs.output_offset_var, output_offset, 0x1);
|
||||
nir_store_var(b, state->gs.header_offset_var, header_offset, 0x1);
|
||||
|
|
@ -686,11 +686,12 @@ emit_gs_vpm_output_header_prolog(struct v3d_compile *c, nir_builder *b,
|
|||
nir_ssa_def *header_offset =
|
||||
nir_load_var(b, state->gs.header_offset_var);
|
||||
nir_ssa_def *vertex_count =
|
||||
nir_isub(b, header_offset, nir_imm_int(b, 1));
|
||||
nir_iadd_imm(b, header_offset, -1);
|
||||
nir_ssa_def *header =
|
||||
nir_ior(b, nir_imm_int(b, state->gs.output_header_size),
|
||||
nir_ishl(b, vertex_count,
|
||||
nir_imm_int(b, VERTEX_COUNT_OFFSET)));
|
||||
nir_ior_imm(b,
|
||||
nir_ishl_imm(b, vertex_count,
|
||||
VERTEX_COUNT_OFFSET),
|
||||
state->gs.output_header_size);
|
||||
|
||||
v3d_nir_store_output(b, 0, NULL, header);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@ pack_unorm_rgb10a2(nir_builder *b, nir_ssa_def *c)
|
|||
int offset = bits[0];
|
||||
for (int i = 1; i < 4; i++) {
|
||||
nir_ssa_def *shifted_chan =
|
||||
nir_ishl(b, chans[i], nir_imm_int(b, offset));
|
||||
nir_ishl_imm(b, chans[i], offset);
|
||||
result = nir_ior(b, result, shifted_chan);
|
||||
offset += bits[i];
|
||||
}
|
||||
|
|
@ -176,9 +176,9 @@ unpack_unorm_rgb10a2(nir_builder *b, nir_ssa_def *c)
|
|||
|
||||
nir_ssa_def *chans[4];
|
||||
for (int i = 0; i < 4; i++) {
|
||||
nir_ssa_def *unorm = nir_iand(b, c, nir_imm_int(b, masks[i]));
|
||||
nir_ssa_def *unorm = nir_iand_imm(b, c, masks[i]);
|
||||
chans[i] = nir_format_unorm_to_float(b, unorm, &bits[i]);
|
||||
c = nir_ushr(b, c, nir_imm_int(b, bits[i]));
|
||||
c = nir_ushr_imm(b, c, bits[i]);
|
||||
}
|
||||
|
||||
return nir_vec4(b, chans[0], chans[1], chans[2], chans[3]);
|
||||
|
|
@ -246,9 +246,8 @@ v3d_emit_logic_op_raw(struct v3d_compile *c, nir_builder *b,
|
|||
c->fs_key->color_fmt[rt].format,
|
||||
UTIL_FORMAT_COLORSPACE_RGB, i);
|
||||
if (bits > 0 && bits < 32) {
|
||||
nir_ssa_def *mask =
|
||||
nir_imm_int(b, (1u << bits) - 1);
|
||||
op_res[i] = nir_iand(b, op_res[i], mask);
|
||||
op_res[i] = nir_iand_imm(b, op_res[i],
|
||||
(1u << bits) - 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ lower_image(struct v3d_compile *c,
|
|||
nir_ssa_def *z = nir_channel(b, coord, 2);
|
||||
nir_ssa_def *d = nir_channel(b, size, 2);
|
||||
if (nir_intrinsic_image_dim(instr) == GLSL_SAMPLER_DIM_CUBE)
|
||||
d = nir_imul(b, nir_imm_int(b, 6), d);
|
||||
d = nir_imul_imm(b, d, 6);
|
||||
oob_cond = nir_ior(b, oob_cond, nir_uge(b, z, d));
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue