fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 22:18:13 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

intel/gen9: Enable MSC RAW Hazard Avoidance

Browse source 
Workaround # 22011374674
Applied to i965, iris and anv drivers
No performance impact is observed with WA.

Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 545d852a7a)
This commit is contained in:
Anuj Phogat 2020-09-09 11:05:18 -07:00 • committed by Dylan Baker
parent 556d6b099e
commit b38d1d1b25
5 changed files with 8 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -1039,7 +1039,7 @@
"description": "intel/gen9: Enable MSC RAW Hazard Avoidance",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

2
src/gallium/drivers/iris/iris_state.c
View file

@ -944,6 +944,8 @@ iris_init_render_context(struct iris_batch *batch)
iris_pack_state(GENX(CACHE_MODE_1), &reg_val, reg) {
reg.FloatBlendOptimizationEnable = true;
reg.FloatBlendOptimizationEnableMask = true;
reg.MSCRAWHazardAvoidanceBit = true;
reg.MSCRAWHazardAvoidanceBitMask = true;
reg.PartialResolveDisableInVC = true;
reg.PartialResolveDisableInVCMask = true;
}

2
src/intel/vulkan/genX_state.c
View file

@ -131,6 +131,8 @@ genX(init_device_state)(struct anv_device *device)
anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
.FloatBlendOptimizationEnable = true,
.FloatBlendOptimizationEnableMask = true,
.MSCRAWHazardAvoidanceBit = true,
.MSCRAWHazardAvoidanceBitMask = true,
.PartialResolveDisableInVC = true,
.PartialResolveDisableInVCMask = true);

1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1561,6 +1561,7 @@ enum brw_pixel_shader_coverage_mask_mode {
#define GEN7_CACHE_MODE_0 0x7000
#define GEN7_CACHE_MODE_1 0x7004
# define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
# define GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT (1 << 9)
# define GEN8_HIZ_NP_PMA_FIX_ENABLE (1 << 11)
# define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
# define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -206,8 +206,10 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
*/
brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
REG_MASK(GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT) |
REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT |
GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
}