diff --git a/src/amd/registers/parse_kernel_headers.py b/src/amd/registers/parse_kernel_headers.py
index 580df37d9bf..f19af8a1417 100644
--- a/src/amd/registers/parse_kernel_headers.py
+++ b/src/amd/registers/parse_kernel_headers.py
@@ -69,8 +69,18 @@ re_shift = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)__SHIFT\s+(?P<valu
 re_mask = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)_MASK\s+(?P<value>[0-9a-fA-Fx]+)L?\n')
 
 def register_filter(gfx_level, name, offset, already_added):
+    # Compute shader registers
+    umd_ranges = [0xB]
+
+    # Gfx context, uconfig, and perf counter registers
+    umd_ranges += [0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37]
+
+    # Add all registers in the 0x8000 range for gfx6
+    if gfx_level == 'gfx6':
+        umd_ranges += [0x8]
+
     # Only accept writeable registers and debug registers
-    return ((offset // 0x1000 in [0xB, 0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37] or
+    return ((offset // 0x1000 in umd_ranges or
              # Add SQ_WAVE registers for trap handlers
              name.startswith('SQ_WAVE_') or
              # Add registers in the 0x8000 range used by all generations
@@ -80,8 +90,6 @@ def register_filter(gfx_level, name, offset, already_added):
                name.startswith('SQ_THREAD') or
                name.startswith('GRBM_STATUS') or
                name.startswith('CP_CP'))) or
-             # Add all registers in the 0x8000 range for gfx6
-             (gfx_level == 'gfx6' and offset // 0x1000 == 0x8) or
              # Add registers in the 0x9000 range
              (offset // 0x1000 == 0x9 and
               (name in ['TA_CS_BC_BASE_ADDR', 'GB_ADDR_CONFIG', 'SPI_CONFIG_CNTL'] or