mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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r600g: initial evergreen support in new path
This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Jerome Glisse
parent
ce8c71817b
commit
b360c050b6
9 changed files with 2806 additions and 126 deletions
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@ -9,6 +9,7 @@ LIBRARY_INCLUDES = \
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C_SOURCES = \
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r600_buffer.c \
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r600_state2.c \
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evergreen_state.c \
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r600_context.c \
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r600_shader.c \
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r600_draw.c \
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1477
src/gallium/drivers/r600/evergreen_state.c
Normal file
1477
src/gallium/drivers/r600/evergreen_state.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -26,6 +26,23 @@
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#ifndef EVERGREEND_H
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#define EVERGREEND_H
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/* evergreen values */
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#define EVERGREEN_CONFIG_REG_OFFSET 0X00008000
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#define EVERGREEN_CONFIG_REG_END 0X0000AC00
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#define EVERGREEN_CONTEXT_REG_OFFSET 0X00028000
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#define EVERGREEN_CONTEXT_REG_END 0X00029000
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#define EVERGREEN_RESOURCE_OFFSET 0x00030000
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#define EVERGREEN_RESOURCE_END 0x00030400
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#define EVERGREEN_LOOP_CONST_OFFSET 0x0003A200
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#define EVERGREEN_LOOP_CONST_END 0x0003A26C
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#define EVERGREEN_BOOL_CONST_OFFSET 0x0003A500
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#define EVERGREEN_BOOL_CONST_END 0x0003A506
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#define EVERGREEN_SAMPLER_OFFSET 0X0003C000
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#define EVERGREEN_SAMPLER_END 0X0003CFF0
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#define EVENT_TYPE_ZPASS_DONE 0x15
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#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
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#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
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#define PKT3_NOP 0x10
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@ -1456,4 +1473,397 @@
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#define SQ_TEX_INST_SAMPLE 0x10
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#define SQ_TEX_INST_SAMPLE_L 0x11
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#define SQ_TEX_INST_SAMPLE_C 0x18
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#define R_008A14_PA_CL_ENHANCE 0x00008A14
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#define R_008C0C_SQ_THREAD_RESOURCE_MGMT 0x00008C0C
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#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x00008D8C
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#define R_028000_DB_RENDER_CONTROL 0x00028000
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#define R_028008_DB_DEPTH_VIEW 0x00028008
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#define R_02800C_DB_RENDER_OVERRIDE 0x0002800C
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#define R_028010_DB_RENDER_OVERRIDE2 0x00028010
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#define R_028014_DB_HTILE_DATA_BASE 0x00028014
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#define R_028028_DB_STENCIL_CLEAR 0x00028028
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#define R_02802C_DB_DEPTH_CLEAR 0x0002802C
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#define R_028048_DB_Z_READ_BASE 0x00028048
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#define R_02804C_DB_STENCIL_READ_BASE 0x0002804C
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#define R_028050_DB_Z_WRITE_BASE 0x00028050
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#define R_028054_DB_STENCIL_WRITE_BASE 0x00028054
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#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140
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#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180
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#define R_028200_PA_SC_WINDOW_OFFSET 0x00028200
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#define R_02820C_PA_SC_CLIPRECT_RULE 0x0002820C
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#define R_028210_PA_SC_CLIPRECT_0_TL 0x00028210
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#define R_028214_PA_SC_CLIPRECT_0_BR 0x00028214
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#define R_028218_PA_SC_CLIPRECT_1_TL 0x00028218
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#define R_02821C_PA_SC_CLIPRECT_1_BR 0x0002821C
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#define R_028220_PA_SC_CLIPRECT_2_TL 0x00028220
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#define R_028224_PA_SC_CLIPRECT_2_BR 0x00028224
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#define R_028228_PA_SC_CLIPRECT_3_TL 0x00028228
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#define R_02822C_PA_SC_CLIPRECT_3_BR 0x0002822C
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#define R_028230_PA_SC_EDGERULE 0x00028230
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#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x00028234
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#define R_028238_CB_TARGET_MASK 0x00028238
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#define R_02823C_CB_SHADER_MASK 0x0002823C
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#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x00028250
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#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x00028254
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#define R_028350_SX_MISC 0x00028350
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#define R_028380_SQ_VTX_SEMANTIC_0 0x00028380
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#define R_028384_SQ_VTX_SEMANTIC_1 0x00028384
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#define R_028388_SQ_VTX_SEMANTIC_2 0x00028388
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#define R_02838C_SQ_VTX_SEMANTIC_3 0x0002838C
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#define R_028390_SQ_VTX_SEMANTIC_4 0x00028390
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#define R_028394_SQ_VTX_SEMANTIC_5 0x00028394
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#define R_028398_SQ_VTX_SEMANTIC_6 0x00028398
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#define R_02839C_SQ_VTX_SEMANTIC_7 0x0002839C
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#define R_0283A0_SQ_VTX_SEMANTIC_8 0x000283A0
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#define R_0283A4_SQ_VTX_SEMANTIC_9 0x000283A4
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#define R_0283A8_SQ_VTX_SEMANTIC_10 0x000283A8
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#define R_0283AC_SQ_VTX_SEMANTIC_11 0x000283AC
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#define R_0283B0_SQ_VTX_SEMANTIC_12 0x000283B0
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#define R_0283B4_SQ_VTX_SEMANTIC_13 0x000283B4
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#define R_0283B8_SQ_VTX_SEMANTIC_14 0x000283B8
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#define R_0283BC_SQ_VTX_SEMANTIC_15 0x000283BC
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#define R_0283C0_SQ_VTX_SEMANTIC_16 0x000283C0
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#define R_0283C4_SQ_VTX_SEMANTIC_17 0x000283C4
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#define R_0283C8_SQ_VTX_SEMANTIC_18 0x000283C8
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#define R_0283CC_SQ_VTX_SEMANTIC_19 0x000283CC
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#define R_0283D0_SQ_VTX_SEMANTIC_20 0x000283D0
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#define R_0283D4_SQ_VTX_SEMANTIC_21 0x000283D4
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#define R_0283D8_SQ_VTX_SEMANTIC_22 0x000283D8
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#define R_0283DC_SQ_VTX_SEMANTIC_23 0x000283DC
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#define R_0283E0_SQ_VTX_SEMANTIC_24 0x000283E0
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#define R_0283E4_SQ_VTX_SEMANTIC_25 0x000283E4
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#define R_0283E8_SQ_VTX_SEMANTIC_26 0x000283E8
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#define R_0283EC_SQ_VTX_SEMANTIC_27 0x000283EC
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#define R_0283F0_SQ_VTX_SEMANTIC_28 0x000283F0
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#define R_0283F4_SQ_VTX_SEMANTIC_29 0x000283F4
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#define R_0283F8_SQ_VTX_SEMANTIC_30 0x000283F8
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#define R_0283FC_SQ_VTX_SEMANTIC_31 0x000283FC
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#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x000282D0
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#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x000282D4
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#define R_028400_VGT_MAX_VTX_INDX 0x00028400
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#define R_028404_VGT_MIN_VTX_INDX 0x00028404
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#define R_028408_VGT_INDX_OFFSET 0x00028408
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#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x0002840C
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#define R_028414_CB_BLEND_RED 0x00028414
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#define R_028418_CB_BLEND_GREEN 0x00028418
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#define R_02841C_CB_BLEND_BLUE 0x0002841C
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#define R_028420_CB_BLEND_ALPHA 0x00028420
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#define R_028438_SX_ALPHA_REF 0x00028438
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#define R_02843C_PA_CL_VPORT_XSCALE_0 0x0002843C
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#define R_028440_PA_CL_VPORT_XOFFSET_0 0x00028440
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#define R_028444_PA_CL_VPORT_YSCALE_0 0x00028444
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#define R_028448_PA_CL_VPORT_YOFFSET_0 0x00028448
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#define R_02844C_PA_CL_VPORT_ZSCALE_0 0x0002844C
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#define R_028450_PA_CL_VPORT_ZOFFSET_0 0x00028450
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#define R_0285BC_PA_CL_UCP0_X 0x000285BC
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#define R_0285C0_PA_CL_UCP0_Y 0x000285C0
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#define R_0285C4_PA_CL_UCP0_Z 0x000285C4
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#define R_0285C8_PA_CL_UCP0_W 0x000285C8
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#define R_0285CC_PA_CL_UCP1_X 0x000285CC
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#define R_0285D0_PA_CL_UCP1_Y 0x000285D0
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#define R_0285D4_PA_CL_UCP1_Z 0x000285D4
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#define R_0285D8_PA_CL_UCP1_W 0x000285D8
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#define R_0285DC_PA_CL_UCP2_X 0x000285DC
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#define R_0285E0_PA_CL_UCP2_Y 0x000285E0
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#define R_0285E4_PA_CL_UCP2_Z 0x000285E4
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#define R_0285E8_PA_CL_UCP2_W 0x000285E8
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#define R_0285EC_PA_CL_UCP3_X 0x000285EC
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#define R_0285F0_PA_CL_UCP3_Y 0x000285F0
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#define R_0285F4_PA_CL_UCP3_Z 0x000285F4
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#define R_0285F8_PA_CL_UCP3_W 0x000285F8
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#define R_0285FC_PA_CL_UCP4_X 0x000285FC
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#define R_028600_PA_CL_UCP4_Y 0x00028600
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#define R_028604_PA_CL_UCP4_Z 0x00028604
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#define R_028608_PA_CL_UCP4_W 0x00028608
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#define R_02860C_PA_CL_UCP5_X 0x0002860C
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#define R_028610_PA_CL_UCP5_Y 0x00028610
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#define R_028614_PA_CL_UCP5_Z 0x00028614
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#define R_028618_PA_CL_UCP5_W 0x00028618
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#define R_02861C_SPI_VS_OUT_ID_0 0x0002861C
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#define R_028620_SPI_VS_OUT_ID_1 0x00028620
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#define R_028624_SPI_VS_OUT_ID_2 0x00028624
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#define R_028628_SPI_VS_OUT_ID_3 0x00028628
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#define R_02862C_SPI_VS_OUT_ID_4 0x0002862C
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#define R_028630_SPI_VS_OUT_ID_5 0x00028630
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#define R_028634_SPI_VS_OUT_ID_6 0x00028634
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#define R_028638_SPI_VS_OUT_ID_7 0x00028638
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#define R_02863C_SPI_VS_OUT_ID_8 0x0002863C
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#define R_028640_SPI_VS_OUT_ID_9 0x00028640
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#define R_028648_SPI_PS_INPUT_CNTL_1 0x00028648
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#define R_02864C_SPI_PS_INPUT_CNTL_2 0x0002864C
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#define R_028650_SPI_PS_INPUT_CNTL_3 0x00028650
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#define R_028654_SPI_PS_INPUT_CNTL_4 0x00028654
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#define R_028658_SPI_PS_INPUT_CNTL_5 0x00028658
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#define R_02865C_SPI_PS_INPUT_CNTL_6 0x0002865C
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#define R_028660_SPI_PS_INPUT_CNTL_7 0x00028660
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#define R_028664_SPI_PS_INPUT_CNTL_8 0x00028664
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#define R_028668_SPI_PS_INPUT_CNTL_9 0x00028668
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#define R_02866C_SPI_PS_INPUT_CNTL_10 0x0002866C
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#define R_028670_SPI_PS_INPUT_CNTL_11 0x00028670
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#define R_028674_SPI_PS_INPUT_CNTL_12 0x00028674
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#define R_028678_SPI_PS_INPUT_CNTL_13 0x00028678
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#define R_02867C_SPI_PS_INPUT_CNTL_14 0x0002867C
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#define R_028680_SPI_PS_INPUT_CNTL_15 0x00028680
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#define R_028684_SPI_PS_INPUT_CNTL_16 0x00028684
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#define R_028688_SPI_PS_INPUT_CNTL_17 0x00028688
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#define R_02868C_SPI_PS_INPUT_CNTL_18 0x0002868C
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#define R_028690_SPI_PS_INPUT_CNTL_19 0x00028690
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#define R_028694_SPI_PS_INPUT_CNTL_20 0x00028694
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#define R_028698_SPI_PS_INPUT_CNTL_21 0x00028698
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#define R_02869C_SPI_PS_INPUT_CNTL_22 0x0002869C
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#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x000286A0
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#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x000286A4
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#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x000286A8
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#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x000286AC
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#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x000286B0
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#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x000286B4
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#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x000286B8
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#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x000286BC
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#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x000286C0
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#define R_0286C8_SPI_THREAD_GROUPING 0x000286C8
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#define R_0286D8_SPI_INPUT_Z 0x000286D8
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#define R_0286DC_SPI_FOG_CNTL 0x000286DC
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#define R_0286E4_SPI_PS_IN_CONTROL_2 0x000286E4
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#define R_0286E8_SPI_COMPUTE_INPUT_CNTL 0x000286E8
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#define R_028780_CB_BLEND0_CONTROL 0x00028780
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#define R_028784_CB_BLEND1_CONTROL 0x00028784
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#define R_028788_CB_BLEND2_CONTROL 0x00028788
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#define R_02878C_CB_BLEND3_CONTROL 0x0002878C
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#define R_028790_CB_BLEND4_CONTROL 0x00028790
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#define R_028794_CB_BLEND5_CONTROL 0x00028794
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#define R_028798_CB_BLEND6_CONTROL 0x00028798
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#define R_02879C_CB_BLEND7_CONTROL 0x0002879C
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#define R_028818_PA_CL_VTE_CNTL 0x00028818
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#define R_028820_PA_CL_NANINF_CNTL 0x00028820
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#define R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1 0x00028838
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#define R_028840_SQ_PGM_START_PS 0x00028840
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#define R_02884C_SQ_PGM_EXPORTS_PS 0x0002884C
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#define S_02884C_EXPORT_COLORS(x) (((x) & 0xF) << 1)
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#define G_02884C_EXPORT_COLORS(x) (((x) >> 1) & 0xF)
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#define C_02884C_EXPORT_COLORS 0xFFFFFFE1
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#define S_02884C_EXPORT_Z(x) (((x) & 0x1) << 0)
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#define G_02884C_EXPORT_Z(x) (((x) >> 0) & 0x1)
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#define C_02884C_EXPORT_Z 0xFFFFFFFE
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#define R_02885C_SQ_PGM_START_VS 0x0002885C
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#define R_0288A4_SQ_PGM_START_FS 0x000288A4
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#define R_0288A8_SQ_PGM_RESOURCES_FS 0x000288A8
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#define R_0288EC_SQ_LDS_ALLOC_PS 0x000288EC
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#define R_028900_SQ_ESGS_RING_ITEMSIZE 0x00028900
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#define R_028904_SQ_GSVS_RING_ITEMSIZE 0x00028904
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#define R_028908_SQ_ESTMP_RING_ITEMSIZE 0x00028908
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#define R_02890C_SQ_GSTMP_RING_ITEMSIZE 0x0002890C
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#define R_028910_SQ_VSTMP_RING_ITEMSIZE 0x00028910
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#define R_028914_SQ_PSTMP_RING_ITEMSIZE 0x00028914
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#define R_02891C_SQ_GS_VERT_ITEMSIZE 0x0002891C
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#define R_028920_SQ_GS_VERT_ITEMSIZE_1 0x00028920
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#define R_028924_SQ_GS_VERT_ITEMSIZE_2 0x00028924
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#define R_028928_SQ_GS_VERT_ITEMSIZE_3 0x00028928
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#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940
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#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980
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#define R_028A04_PA_SU_POINT_MINMAX 0x00028A04
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#define R_028A08_PA_SU_LINE_CNTL 0x00028A08
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#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x00028A10
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#define R_028A14_VGT_HOS_CNTL 0x00028A14
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#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x00028A18
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#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x00028A1C
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#define R_028A20_VGT_HOS_REUSE_DEPTH 0x00028A20
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#define R_028A24_VGT_GROUP_PRIM_TYPE 0x00028A24
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#define R_028A28_VGT_GROUP_FIRST_DECR 0x00028A28
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#define R_028A2C_VGT_GROUP_DECR 0x00028A2C
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#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x00028A30
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#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x00028A34
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#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x00028A38
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#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x00028A3C
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#define R_028A48_PA_SC_MODE_CNTL_0 0x00028A48
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#define R_028A4C_PA_SC_MODE_CNTL_1 0x00028A4C
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#define R_028AB4_VGT_REUSE_OFF 0x00028AB4
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#define R_028AB8_VGT_VTX_CNT_EN 0x00028AB8
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#define R_028ABC_DB_HTILE_SURFACE 0x00028ABC
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#define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x00028AC0
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#define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x00028AC4
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#define R_028AC8_DB_PRELOAD_CONTROL 0x00028AC8
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#define R_028B54_VGT_SHADER_STAGES_EN 0x00028B54
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#define R_028B70_DB_ALPHA_TO_MASK 0x00028B70
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#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x00028B78
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#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x00028B7C
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#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00028B80
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#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00028B84
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#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x00028B88
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#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00028B8C
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#define R_028B94_VGT_STRMOUT_CONFIG 0x00028B94
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#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x00028B98
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#define R_028C00_PA_SC_LINE_CNTL 0x00028C00
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#define R_028C04_PA_SC_AA_CONFIG 0x00028C04
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#define R_028C08_PA_SU_VTX_CNTL 0x00028C08
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#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x00028C0C
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#define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x00028C10
|
||||
#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x00028C14
|
||||
#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ 0x00028C18
|
||||
#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x00028C1C
|
||||
#define R_028C3C_PA_SC_AA_MASK 0x00028C3C
|
||||
#define R_028C60_CB_COLOR0_BASE 0x00028C60
|
||||
#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
|
||||
#define R_028C9C_CB_COLOR1_BASE 0x00028C9C
|
||||
#define R_028CA0_CB_COLOR1_PITCH 0x00028CA0
|
||||
#define R_028CA4_CB_COLOR1_SLICE 0x00028CA4
|
||||
#define R_028CA8_CB_COLOR1_VIEW 0x00028CA8
|
||||
#define R_028CAC_CB_COLOR1_INFO 0x00028CAC
|
||||
#define R_028CB0_CB_COLOR1_ATTRIB 0x00028CB0
|
||||
#define R_028CB8_CB_COLOR1_DIM 0x00028CB8
|
||||
#define R_028CD8_CB_COLOR2_BASE 0x00028CD8
|
||||
#define R_028CDC_CB_COLOR2_PITCH 0x00028CDC
|
||||
#define R_028CE0_CB_COLOR2_SLICE 0x00028CE0
|
||||
#define R_028CE4_CB_COLOR2_VIEW 0x00028CE4
|
||||
#define R_028CE8_CB_COLOR2_INFO 0x00028CE8
|
||||
#define R_028CEC_CB_COLOR2_ATTRIB 0x00028CEC
|
||||
#define R_028CF0_CB_COLOR2_DIM 0x00028CF0
|
||||
#define R_028D14_CB_COLOR3_BASE 0x00028D14
|
||||
#define R_028D18_CB_COLOR3_PITCH 0x00028D18
|
||||
#define R_028D1C_CB_COLOR3_SLICE 0x00028D1C
|
||||
#define R_028D20_CB_COLOR3_VIEW 0x00028D20
|
||||
#define R_028D24_CB_COLOR3_INFO 0x00028D24
|
||||
#define R_028D28_CB_COLOR3_ATTRIB 0x00028D28
|
||||
#define R_028D2C_CB_COLOR3_DIM 0x00028D2C
|
||||
#define R_028D50_CB_COLOR4_BASE 0x00028D50
|
||||
#define R_028D54_CB_COLOR4_PITCH 0x00028D54
|
||||
#define R_028D58_CB_COLOR4_SLICE 0x00028D58
|
||||
#define R_028D5C_CB_COLOR4_VIEW 0x00028D5C
|
||||
#define R_028D60_CB_COLOR4_INFO 0x00028D60
|
||||
#define R_028D64_CB_COLOR4_ATTRIB 0x00028D64
|
||||
#define R_028D68_CB_COLOR4_DIM 0x00028D68
|
||||
#define R_028D8C_CB_COLOR5_BASE 0x00028D8C
|
||||
#define R_028D90_CB_COLOR5_PITCH 0x00028D90
|
||||
#define R_028D94_CB_COLOR5_SLICE 0x00028D94
|
||||
#define R_028D98_CB_COLOR5_VIEW 0x00028D98
|
||||
#define R_028D9C_CB_COLOR5_INFO 0x00028D9C
|
||||
#define R_028DA0_CB_COLOR5_ATTRIB 0x00028DA0
|
||||
#define R_028DA4_CB_COLOR5_DIM 0x00028DA4
|
||||
#define R_028DC8_CB_COLOR6_BASE 0x00028DC8
|
||||
#define R_028DCC_CB_COLOR6_PITCH 0x00028DCC
|
||||
#define R_028DD0_CB_COLOR6_SLICE 0x00028DD0
|
||||
#define R_028DD4_CB_COLOR6_VIEW 0x00028DD4
|
||||
#define R_028DD8_CB_COLOR6_INFO 0x00028DD8
|
||||
#define R_028DDC_CB_COLOR6_ATTRIB 0x00028DDC
|
||||
#define R_028DE0_CB_COLOR6_DIM 0x00028DE0
|
||||
#define R_028E04_CB_COLOR7_BASE 0x00028E04
|
||||
#define R_028E08_CB_COLOR7_PITCH 0x00028E08
|
||||
#define R_028E0C_CB_COLOR7_SLICE 0x00028E0C
|
||||
#define R_028E10_CB_COLOR7_VIEW 0x00028E10
|
||||
#define R_028E14_CB_COLOR7_INFO 0x00028E14
|
||||
#define R_028E18_CB_COLOR7_ATTRIB 0x00028E18
|
||||
#define R_028E1C_CB_COLOR7_DIM 0x00028E1C
|
||||
#define R_028E40_CB_COLOR8_BASE 0x00028E40
|
||||
#define R_028E44_CB_COLOR8_PITCH 0x00028E44
|
||||
#define R_028E48_CB_COLOR8_SLICE 0x00028E48
|
||||
#define R_028E4C_CB_COLOR8_VIEW 0x00028E4C
|
||||
#define R_028E50_CB_COLOR8_INFO 0x00028E50
|
||||
#define R_028E54_CB_COLOR8_ATTRIB 0x00028E54
|
||||
#define R_028E58_CB_COLOR8_DIM 0x00028E58
|
||||
#define R_028E5C_CB_COLOR9_BASE 0x00028E5C
|
||||
#define R_028E60_CB_COLOR9_PITCH 0x00028E60
|
||||
#define R_028E64_CB_COLOR9_SLICE 0x00028E64
|
||||
#define R_028E68_CB_COLOR9_VIEW 0x00028E68
|
||||
#define R_028E6C_CB_COLOR9_INFO 0x00028E6C
|
||||
#define R_028E70_CB_COLOR9_ATTRIB 0x00028E70
|
||||
#define R_028E74_CB_COLOR9_DIM 0x00028E74
|
||||
#define R_028E78_CB_COLOR10_BASE 0x00028E78
|
||||
#define R_028E7C_CB_COLOR10_PITCH 0x00028E7C
|
||||
#define R_028E80_CB_COLOR10_SLICE 0x00028E80
|
||||
#define R_028E84_CB_COLOR10_VIEW 0x00028E84
|
||||
#define R_028E88_CB_COLOR10_INFO 0x00028E88
|
||||
#define R_028E8C_CB_COLOR10_ATTRIB 0x00028E8C
|
||||
#define R_028E90_CB_COLOR10_DIM 0x00028E90
|
||||
#define R_028E94_CB_COLOR11_BASE 0x00028E94
|
||||
#define R_028E98_CB_COLOR11_PITCH 0x00028E98
|
||||
#define R_028E9C_CB_COLOR11_SLICE 0x00028E9C
|
||||
#define R_028EA0_CB_COLOR11_VIEW 0x00028EA0
|
||||
#define R_028EA4_CB_COLOR11_INFO 0x00028EA4
|
||||
#define R_028EA8_CB_COLOR11_ATTRIB 0x00028EA8
|
||||
#define R_028EAC_CB_COLOR11_DIM 0x00028EAC
|
||||
#define R_030000_RESOURCE0_WORD0 0x00030000
|
||||
#define R_030004_RESOURCE0_WORD1 0x00030004
|
||||
#define R_030008_RESOURCE0_WORD2 0x00030008
|
||||
#define R_03000C_RESOURCE0_WORD3 0x0003000C
|
||||
#define R_030010_RESOURCE0_WORD4 0x00030010
|
||||
#define R_030014_RESOURCE0_WORD5 0x00030014
|
||||
#define R_030018_RESOURCE0_WORD6 0x00030018
|
||||
#define R_03001C_RESOURCE0_WORD7 0x0003001C
|
||||
#define R_0085F0_CP_COHER_CNTL 0x0085F0
|
||||
#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
|
||||
#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
|
||||
#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
|
||||
#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
|
||||
#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
|
||||
#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
|
||||
#define S_0085F0_SO0_DEST_BASE_ENA(x) (((x) & 0x1) << 2)
|
||||
#define G_0085F0_SO0_DEST_BASE_ENA(x) (((x) >> 2) & 0x1)
|
||||
#define C_0085F0_SO0_DEST_BASE_ENA 0xFFFFFFFB
|
||||
#define S_0085F0_SO1_DEST_BASE_ENA(x) (((x) & 0x1) << 3)
|
||||
#define G_0085F0_SO1_DEST_BASE_ENA(x) (((x) >> 3) & 0x1)
|
||||
#define C_0085F0_SO1_DEST_BASE_ENA 0xFFFFFFF7
|
||||
#define S_0085F0_SO2_DEST_BASE_ENA(x) (((x) & 0x1) << 4)
|
||||
#define G_0085F0_SO2_DEST_BASE_ENA(x) (((x) >> 4) & 0x1)
|
||||
#define C_0085F0_SO2_DEST_BASE_ENA 0xFFFFFFEF
|
||||
#define S_0085F0_SO3_DEST_BASE_ENA(x) (((x) & 0x1) << 5)
|
||||
#define G_0085F0_SO3_DEST_BASE_ENA(x) (((x) >> 5) & 0x1)
|
||||
#define C_0085F0_SO3_DEST_BASE_ENA 0xFFFFFFDF
|
||||
#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
|
||||
#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
|
||||
#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
|
||||
#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
|
||||
#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
|
||||
#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
|
||||
#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
|
||||
#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
|
||||
#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
|
||||
#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
|
||||
#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
|
||||
#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
|
||||
#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
|
||||
#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
|
||||
#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
|
||||
#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
|
||||
#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
|
||||
#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
|
||||
#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
|
||||
#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
|
||||
#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
|
||||
#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
|
||||
#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
|
||||
#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
|
||||
#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
|
||||
#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
|
||||
#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
|
||||
#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
|
||||
#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
|
||||
#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF
|
||||
#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
|
||||
#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
|
||||
#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
|
||||
#define S_0085F0_VC_ACTION_ENA(x) (((x) & 0x1) << 24)
|
||||
#define G_0085F0_VC_ACTION_ENA(x) (((x) >> 24) & 0x1)
|
||||
#define C_0085F0_VC_ACTION_ENA 0xFEFFFFFF
|
||||
#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
|
||||
#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
|
||||
#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF
|
||||
#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
|
||||
#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
|
||||
#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
|
||||
#define S_0085F0_SH_ACTION_ENA(x) (((x) & 0x1) << 27)
|
||||
#define G_0085F0_SH_ACTION_ENA(x) (((x) >> 27) & 0x1)
|
||||
#define C_0085F0_SH_ACTION_ENA 0xF7FFFFFF
|
||||
#define S_0085F0_SMX_ACTION_ENA(x) (((x) & 0x1) << 28)
|
||||
#define G_0085F0_SMX_ACTION_ENA(x) (((x) >> 28) & 0x1)
|
||||
#define C_0085F0_SMX_ACTION_ENA 0xEFFFFFFF
|
||||
#define S_0085F0_CR0_ACTION_ENA(x) (((x) & 0x1) << 29)
|
||||
#define G_0085F0_CR0_ACTION_ENA(x) (((x) >> 29) & 0x1)
|
||||
#define C_0085F0_CR0_ACTION_ENA 0xDFFFFFFF
|
||||
#define S_0085F0_CR1_ACTION_ENA(x) (((x) & 0x1) << 30)
|
||||
#define G_0085F0_CR1_ACTION_ENA(x) (((x) >> 30) & 0x1)
|
||||
#define C_0085F0_CR1_ACTION_ENA 0xBFFFFFFF
|
||||
#define S_0085F0_CR2_ACTION_ENA(x) (((x) & 0x1) << 31)
|
||||
#define G_0085F0_CR2_ACTION_ENA(x) (((x) >> 31) & 0x1)
|
||||
#define C_0085F0_CR2_ACTION_ENA 0x7FFFFFFF
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -129,6 +129,17 @@ enum r600_group_id {
|
|||
R600_NGROUPS
|
||||
};
|
||||
|
||||
enum evergreen_group_id {
|
||||
EVERGREEN_GROUP_CONFIG = 0,
|
||||
EVERGREEN_GROUP_CONTEXT,
|
||||
EVERGREEN_GROUP_RESOURCE,
|
||||
EVERGREEN_GROUP_SAMPLER,
|
||||
EVERGREEN_GROUP_CTL_CONST,
|
||||
EVERGREEN_GROUP_LOOP_CONST,
|
||||
EVERGREEN_GROUP_BOOL_CONST,
|
||||
EVERGREEN_NGROUPS
|
||||
};
|
||||
|
||||
struct r600_pipe_reg {
|
||||
unsigned group_id;
|
||||
u32 offset;
|
||||
|
|
@ -265,4 +276,9 @@ boolean r600_context_query_result(struct r600_context *ctx,
|
|||
void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
|
||||
void r600_query_end(struct r600_context *ctx, struct r600_query *query);
|
||||
|
||||
int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
|
||||
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
|
||||
void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
|
||||
void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
146
src/gallium/drivers/r600/r600_pipe.h
Normal file
146
src/gallium/drivers/r600/r600_pipe.h
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
* license, and/or sell copies of the Software, and to permit persons to whom
|
||||
* the Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Jerome Glisse
|
||||
*/
|
||||
#ifndef R600_PIPE_H
|
||||
#define R600_PIPE_H
|
||||
|
||||
enum r600_pipe_state_id {
|
||||
R600_PIPE_STATE_BLEND = 0,
|
||||
R600_PIPE_STATE_BLEND_COLOR,
|
||||
R600_PIPE_STATE_CONFIG,
|
||||
R600_PIPE_STATE_CLIP,
|
||||
R600_PIPE_STATE_SCISSOR,
|
||||
R600_PIPE_STATE_VIEWPORT,
|
||||
R600_PIPE_STATE_RASTERIZER,
|
||||
R600_PIPE_STATE_VGT,
|
||||
R600_PIPE_STATE_FRAMEBUFFER,
|
||||
R600_PIPE_STATE_DSA,
|
||||
R600_PIPE_STATE_STENCIL_REF,
|
||||
R600_PIPE_STATE_PS_SHADER,
|
||||
R600_PIPE_STATE_VS_SHADER,
|
||||
R600_PIPE_STATE_CONSTANT,
|
||||
R600_PIPE_STATE_SAMPLER,
|
||||
R600_PIPE_STATE_RESOURCE,
|
||||
R600_PIPE_NSTATES
|
||||
};
|
||||
|
||||
struct r600_screen {
|
||||
struct pipe_screen screen;
|
||||
struct radeon *radeon;
|
||||
};
|
||||
|
||||
struct r600_pipe_sampler_view {
|
||||
struct pipe_sampler_view base;
|
||||
struct r600_pipe_state state;
|
||||
};
|
||||
|
||||
struct r600_pipe_rasterizer {
|
||||
struct r600_pipe_state rstate;
|
||||
bool flatshade;
|
||||
unsigned sprite_coord_enable;
|
||||
};
|
||||
|
||||
struct r600_pipe_blend {
|
||||
struct r600_pipe_state rstate;
|
||||
unsigned cb_target_mask;
|
||||
};
|
||||
|
||||
struct r600_pipe_shader {
|
||||
struct r600_shader shader;
|
||||
struct r600_pipe_state rstate;
|
||||
struct radeon_ws_bo *bo;
|
||||
};
|
||||
|
||||
struct r600_vertex_element
|
||||
{
|
||||
unsigned count;
|
||||
unsigned refcount;
|
||||
struct pipe_vertex_element elements[32];
|
||||
};
|
||||
|
||||
struct r600_pipe_context {
|
||||
struct pipe_context context;
|
||||
struct r600_screen *screen;
|
||||
struct radeon *radeon;
|
||||
struct blitter_context *blitter;
|
||||
struct r600_pipe_state *states[R600_PIPE_NSTATES];
|
||||
struct r600_context ctx;
|
||||
struct r600_vertex_element *vertex_elements;
|
||||
struct pipe_framebuffer_state framebuffer;
|
||||
struct pipe_index_buffer index_buffer;
|
||||
struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
|
||||
unsigned nvertex_buffer;
|
||||
unsigned cb_target_mask;
|
||||
/* for saving when using blitter */
|
||||
struct pipe_stencil_ref stencil_ref;
|
||||
struct pipe_viewport_state viewport;
|
||||
struct pipe_clip_state clip;
|
||||
unsigned vs_nconst;
|
||||
unsigned ps_nconst;
|
||||
struct r600_pipe_state vs_const[256];
|
||||
struct r600_pipe_state ps_const[256];
|
||||
struct r600_pipe_state vs_resource[160];
|
||||
struct r600_pipe_state ps_resource[160];
|
||||
struct r600_pipe_state config;
|
||||
struct r600_pipe_shader *ps_shader;
|
||||
struct r600_pipe_shader *vs_shader;
|
||||
struct r600_pipe_state vs_const_buffer;
|
||||
struct r600_pipe_state ps_const_buffer;
|
||||
/* shader information */
|
||||
unsigned sprite_coord_enable;
|
||||
bool flatshade;
|
||||
};
|
||||
|
||||
struct r600_drawl {
|
||||
struct pipe_context *ctx;
|
||||
unsigned mode;
|
||||
unsigned start;
|
||||
unsigned count;
|
||||
unsigned index_size;
|
||||
struct pipe_resource *index_buffer;
|
||||
};
|
||||
|
||||
uint32_t r600_translate_texformat(enum pipe_format format,
|
||||
const unsigned char *swizzle_view,
|
||||
uint32_t *word4_p, uint32_t *yuv_format_p);
|
||||
|
||||
/* r600_state2.c */
|
||||
int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader);
|
||||
int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens);
|
||||
|
||||
/* evergreen_state.c */
|
||||
void evergreen_init_state_functions2(struct r600_pipe_context *rctx);
|
||||
void evergreen_init_config2(struct r600_pipe_context *rctx);
|
||||
void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info);
|
||||
void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
|
||||
void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
|
||||
|
||||
static INLINE u32 S_FIXED(float value, u32 frac_bits)
|
||||
{
|
||||
return value * (1 << frac_bits);
|
||||
}
|
||||
#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
|
||||
|
||||
#endif
|
||||
|
|
@ -48,108 +48,12 @@ struct radeon_state {
|
|||
};
|
||||
#include "r600_resource.h"
|
||||
#include "r600_shader.h"
|
||||
|
||||
|
||||
uint32_t r600_translate_texformat(enum pipe_format format,
|
||||
const unsigned char *swizzle_view,
|
||||
uint32_t *word4_p, uint32_t *yuv_format_p);
|
||||
|
||||
#include "r600_pipe.h"
|
||||
#include "r600_state_inlines.h"
|
||||
|
||||
enum r600_pipe_state_id {
|
||||
R600_PIPE_STATE_BLEND = 0,
|
||||
R600_PIPE_STATE_BLEND_COLOR,
|
||||
R600_PIPE_STATE_CONFIG,
|
||||
R600_PIPE_STATE_CLIP,
|
||||
R600_PIPE_STATE_SCISSOR,
|
||||
R600_PIPE_STATE_VIEWPORT,
|
||||
R600_PIPE_STATE_RASTERIZER,
|
||||
R600_PIPE_STATE_VGT,
|
||||
R600_PIPE_STATE_FRAMEBUFFER,
|
||||
R600_PIPE_STATE_DSA,
|
||||
R600_PIPE_STATE_STENCIL_REF,
|
||||
R600_PIPE_STATE_PS_SHADER,
|
||||
R600_PIPE_STATE_VS_SHADER,
|
||||
R600_PIPE_STATE_CONSTANT,
|
||||
R600_PIPE_STATE_SAMPLER,
|
||||
R600_PIPE_STATE_RESOURCE,
|
||||
R600_PIPE_NSTATES
|
||||
};
|
||||
|
||||
struct r600_screen {
|
||||
struct pipe_screen screen;
|
||||
struct radeon *radeon;
|
||||
};
|
||||
|
||||
struct r600_pipe_sampler_view {
|
||||
struct pipe_sampler_view base;
|
||||
struct r600_pipe_state state;
|
||||
};
|
||||
|
||||
struct r600_pipe_rasterizer {
|
||||
struct r600_pipe_state rstate;
|
||||
bool flatshade;
|
||||
unsigned sprite_coord_enable;
|
||||
};
|
||||
|
||||
struct r600_pipe_blend {
|
||||
struct r600_pipe_state rstate;
|
||||
unsigned cb_target_mask;
|
||||
};
|
||||
|
||||
struct r600_pipe_shader {
|
||||
struct r600_shader shader;
|
||||
struct r600_pipe_state rstate;
|
||||
struct radeon_ws_bo *bo;
|
||||
};
|
||||
|
||||
struct r600_vertex_element
|
||||
{
|
||||
unsigned count;
|
||||
unsigned refcount;
|
||||
struct pipe_vertex_element elements[32];
|
||||
};
|
||||
|
||||
struct r600_pipe_context {
|
||||
struct pipe_context context;
|
||||
struct r600_screen *screen;
|
||||
struct radeon *radeon;
|
||||
struct blitter_context *blitter;
|
||||
struct r600_pipe_state *states[R600_PIPE_NSTATES];
|
||||
struct r600_context ctx;
|
||||
struct r600_vertex_element *vertex_elements;
|
||||
struct pipe_framebuffer_state framebuffer;
|
||||
struct pipe_index_buffer index_buffer;
|
||||
struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
|
||||
unsigned nvertex_buffer;
|
||||
unsigned cb_target_mask;
|
||||
/* for saving when using blitter */
|
||||
struct pipe_stencil_ref stencil_ref;
|
||||
struct pipe_viewport_state viewport;
|
||||
struct pipe_clip_state clip;
|
||||
unsigned vs_nconst;
|
||||
unsigned ps_nconst;
|
||||
struct r600_pipe_state vs_const[256];
|
||||
struct r600_pipe_state ps_const[256];
|
||||
struct r600_pipe_state vs_resource[160];
|
||||
struct r600_pipe_state ps_resource[160];
|
||||
struct r600_pipe_state config;
|
||||
struct r600_pipe_shader *ps_shader;
|
||||
struct r600_pipe_shader *vs_shader;
|
||||
/* shader information */
|
||||
unsigned sprite_coord_enable;
|
||||
bool flatshade;
|
||||
};
|
||||
|
||||
static INLINE u32 S_FIXED(float value, u32 frac_bits)
|
||||
{
|
||||
return value * (1 << frac_bits);
|
||||
}
|
||||
|
||||
/* r600_shader.c */
|
||||
static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
|
||||
{
|
||||
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
|
||||
struct r600_pipe_state *rstate = &shader->rstate;
|
||||
struct r600_shader *rshader = &shader->shader;
|
||||
unsigned spi_vs_out_id[10];
|
||||
|
|
@ -287,10 +191,18 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *s
|
|||
rshader->flat_shade = rctx->flatshade;
|
||||
switch (rshader->processor_type) {
|
||||
case TGSI_PROCESSOR_VERTEX:
|
||||
r600_pipe_shader_vs(ctx, shader);
|
||||
if (rshader->family >= CHIP_CEDAR) {
|
||||
evergreen_pipe_shader_vs(ctx, shader);
|
||||
} else {
|
||||
r600_pipe_shader_vs(ctx, shader);
|
||||
}
|
||||
break;
|
||||
case TGSI_PROCESSOR_FRAGMENT:
|
||||
r600_pipe_shader_ps(ctx, shader);
|
||||
if (rshader->family >= CHIP_CEDAR) {
|
||||
evergreen_pipe_shader_ps(ctx, shader);
|
||||
} else {
|
||||
r600_pipe_shader_ps(ctx, shader);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
|
@ -339,7 +251,7 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader
|
|||
return r600_bc_build(&shader->bc);
|
||||
}
|
||||
|
||||
static int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
|
||||
int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
|
||||
{
|
||||
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
|
||||
int r;
|
||||
|
|
@ -359,7 +271,7 @@ static int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_s
|
|||
}
|
||||
|
||||
int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
|
||||
static int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
|
||||
int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
|
||||
{
|
||||
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
|
||||
int r;
|
||||
|
|
@ -535,15 +447,6 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
|
|||
FREE(rscreen);
|
||||
}
|
||||
|
||||
struct r600_drawl {
|
||||
struct pipe_context *ctx;
|
||||
unsigned mode;
|
||||
unsigned start;
|
||||
unsigned count;
|
||||
unsigned index_size;
|
||||
struct pipe_resource *index_buffer;
|
||||
};
|
||||
|
||||
int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
|
||||
static void r600_draw_common(struct r600_drawl *draw)
|
||||
{
|
||||
|
|
@ -2137,7 +2040,6 @@ static struct pipe_context *r600_create_context2(struct pipe_screen *screen, voi
|
|||
rctx->context.screen = screen;
|
||||
rctx->context.priv = priv;
|
||||
rctx->context.destroy = r600_destroy_context;
|
||||
rctx->context.draw_vbo = r600_draw_vbo2;
|
||||
rctx->context.flush = r600_flush2;
|
||||
|
||||
/* Easy accessing of screen/winsys. */
|
||||
|
|
@ -2146,7 +2048,6 @@ static struct pipe_context *r600_create_context2(struct pipe_screen *screen, voi
|
|||
|
||||
r600_init_blit_functions2(rctx);
|
||||
r600_init_query_functions2(rctx);
|
||||
r600_init_state_functions2(rctx);
|
||||
r600_init_context_resource_functions2(rctx);
|
||||
|
||||
rctx->blitter = util_blitter_create(&rctx->context);
|
||||
|
|
@ -2155,13 +2056,46 @@ static struct pipe_context *r600_create_context2(struct pipe_screen *screen, voi
|
|||
return NULL;
|
||||
}
|
||||
|
||||
if (r600_context_init(&rctx->ctx, rctx->radeon)) {
|
||||
switch (r600_get_family(rctx->radeon)) {
|
||||
case CHIP_R600:
|
||||
case CHIP_RV610:
|
||||
case CHIP_RV630:
|
||||
case CHIP_RV670:
|
||||
case CHIP_RV620:
|
||||
case CHIP_RV635:
|
||||
case CHIP_RS780:
|
||||
case CHIP_RS880:
|
||||
case CHIP_RV770:
|
||||
case CHIP_RV730:
|
||||
case CHIP_RV710:
|
||||
case CHIP_RV740:
|
||||
rctx->context.draw_vbo = r600_draw_vbo2;
|
||||
r600_init_state_functions2(rctx);
|
||||
if (r600_context_init(&rctx->ctx, rctx->radeon)) {
|
||||
r600_destroy_context(&rctx->context);
|
||||
return NULL;
|
||||
}
|
||||
r600_init_config2(rctx);
|
||||
break;
|
||||
case CHIP_CEDAR:
|
||||
case CHIP_REDWOOD:
|
||||
case CHIP_JUNIPER:
|
||||
case CHIP_CYPRESS:
|
||||
case CHIP_HEMLOCK:
|
||||
rctx->context.draw_vbo = evergreen_draw;
|
||||
evergreen_init_state_functions2(rctx);
|
||||
if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
|
||||
r600_destroy_context(&rctx->context);
|
||||
return NULL;
|
||||
}
|
||||
evergreen_init_config2(rctx);
|
||||
break;
|
||||
default:
|
||||
R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
|
||||
r600_destroy_context(&rctx->context);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
r600_init_config2(rctx);
|
||||
|
||||
return &rctx->context;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ C_SOURCES = \
|
|||
bof.c \
|
||||
r600_state.c \
|
||||
r600_state2.c \
|
||||
evergreen_state.c \
|
||||
r600.c \
|
||||
radeon_ctx.c \
|
||||
radeon_draw.c \
|
||||
|
|
|
|||
685
src/gallium/winsys/r600/drm/evergreen_state.c
Normal file
685
src/gallium/winsys/r600/drm/evergreen_state.c
Normal file
|
|
@ -0,0 +1,685 @@
|
|||
/*
|
||||
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
* license, and/or sell copies of the Software, and to permit persons to whom
|
||||
* the Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Jerome Glisse
|
||||
*/
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <assert.h>
|
||||
#include "xf86drm.h"
|
||||
#include "r600.h"
|
||||
#include "evergreend.h"
|
||||
#include "r600_priv.h"
|
||||
#include "radeon_drm.h"
|
||||
#include "bof.h"
|
||||
#include "pipe/p_compiler.h"
|
||||
#include "util/u_inlines.h"
|
||||
#include <pipebuffer/pb_bufmgr.h>
|
||||
|
||||
struct radeon_bo {
|
||||
struct pipe_reference reference;
|
||||
unsigned handle;
|
||||
unsigned size;
|
||||
unsigned alignment;
|
||||
unsigned map_count;
|
||||
void *data;
|
||||
};
|
||||
struct radeon_ws_bo {
|
||||
struct pipe_reference reference;
|
||||
struct pb_buffer *pb;
|
||||
};
|
||||
struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
|
||||
|
||||
struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset);
|
||||
void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode);
|
||||
void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo);
|
||||
int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg);
|
||||
int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset);
|
||||
|
||||
#define GROUP_FORCE_NEW_BLOCK 0
|
||||
static const struct r600_reg evergreen_reg_list[] = {
|
||||
{0, 0, R_008958_VGT_PRIMITIVE_TYPE},
|
||||
{0, 0, R_008A14_PA_CL_ENHANCE},
|
||||
{0, 0, R_008C00_SQ_CONFIG},
|
||||
{0, 0, R_008C04_SQ_GPR_RESOURCE_MGMT_1},
|
||||
{0, 0, R_008C08_SQ_GPR_RESOURCE_MGMT_2},
|
||||
{0, 0, R_008C0C_SQ_THREAD_RESOURCE_MGMT},
|
||||
{0, 0, R_008C18_SQ_THREAD_RESOURCE_MGMT_1},
|
||||
{0, 0, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2},
|
||||
{0, 0, R_008C20_SQ_STACK_RESOURCE_MGMT_1},
|
||||
{0, 0, R_008C24_SQ_STACK_RESOURCE_MGMT_2},
|
||||
{0, 0, R_008C28_SQ_STACK_RESOURCE_MGMT_3},
|
||||
{0, 0, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ},
|
||||
{0, 0, R_009100_SPI_CONFIG_CNTL},
|
||||
{0, 0, R_00913C_SPI_CONFIG_CNTL_1},
|
||||
{0, 0, R_028000_DB_RENDER_CONTROL},
|
||||
{0, 0, R_028008_DB_DEPTH_VIEW},
|
||||
{0, 0, R_02800C_DB_RENDER_OVERRIDE},
|
||||
{0, 0, R_028010_DB_RENDER_OVERRIDE2},
|
||||
{1, 0, R_028014_DB_HTILE_DATA_BASE},
|
||||
{0, 0, R_028028_DB_STENCIL_CLEAR},
|
||||
{0, 0, R_02802C_DB_DEPTH_CLEAR},
|
||||
{0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL},
|
||||
{0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR},
|
||||
{1, 0, R_028040_DB_Z_INFO},
|
||||
{0, 0, R_028044_DB_STENCIL_INFO},
|
||||
{1, 0, R_028048_DB_Z_READ_BASE},
|
||||
{1, 0, R_02804C_DB_STENCIL_READ_BASE},
|
||||
{1, 0, R_028050_DB_Z_WRITE_BASE},
|
||||
{1, 0, R_028054_DB_STENCIL_WRITE_BASE},
|
||||
{0, 0, R_028058_DB_DEPTH_SIZE},
|
||||
{0, 0, R_02805C_DB_DEPTH_SLICE},
|
||||
{0, 0, R_028140_ALU_CONST_BUFFER_SIZE_PS_0},
|
||||
{0, 0, R_028180_ALU_CONST_BUFFER_SIZE_VS_0},
|
||||
{0, 0, R_028200_PA_SC_WINDOW_OFFSET},
|
||||
{0, 0, R_028204_PA_SC_WINDOW_SCISSOR_TL},
|
||||
{0, 0, R_028208_PA_SC_WINDOW_SCISSOR_BR},
|
||||
{0, 0, R_02820C_PA_SC_CLIPRECT_RULE},
|
||||
{0, 0, R_028210_PA_SC_CLIPRECT_0_TL},
|
||||
{0, 0, R_028214_PA_SC_CLIPRECT_0_BR},
|
||||
{0, 0, R_028218_PA_SC_CLIPRECT_1_TL},
|
||||
{0, 0, R_02821C_PA_SC_CLIPRECT_1_BR},
|
||||
{0, 0, R_028220_PA_SC_CLIPRECT_2_TL},
|
||||
{0, 0, R_028224_PA_SC_CLIPRECT_2_BR},
|
||||
{0, 0, R_028228_PA_SC_CLIPRECT_3_TL},
|
||||
{0, 0, R_02822C_PA_SC_CLIPRECT_3_BR},
|
||||
{0, 0, R_028230_PA_SC_EDGERULE},
|
||||
{0, 0, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET},
|
||||
{0, 0, R_028238_CB_TARGET_MASK},
|
||||
{0, 0, R_02823C_CB_SHADER_MASK},
|
||||
{0, 0, R_028240_PA_SC_GENERIC_SCISSOR_TL},
|
||||
{0, 0, R_028244_PA_SC_GENERIC_SCISSOR_BR},
|
||||
{0, 0, R_028250_PA_SC_VPORT_SCISSOR_0_TL},
|
||||
{0, 0, R_028254_PA_SC_VPORT_SCISSOR_0_BR},
|
||||
{0, 0, R_028350_SX_MISC},
|
||||
{0, 0, R_028380_SQ_VTX_SEMANTIC_0},
|
||||
{0, 0, R_028384_SQ_VTX_SEMANTIC_1},
|
||||
{0, 0, R_028388_SQ_VTX_SEMANTIC_2},
|
||||
{0, 0, R_02838C_SQ_VTX_SEMANTIC_3},
|
||||
{0, 0, R_028390_SQ_VTX_SEMANTIC_4},
|
||||
{0, 0, R_028394_SQ_VTX_SEMANTIC_5},
|
||||
{0, 0, R_028398_SQ_VTX_SEMANTIC_6},
|
||||
{0, 0, R_02839C_SQ_VTX_SEMANTIC_7},
|
||||
{0, 0, R_0283A0_SQ_VTX_SEMANTIC_8},
|
||||
{0, 0, R_0283A4_SQ_VTX_SEMANTIC_9},
|
||||
{0, 0, R_0283A8_SQ_VTX_SEMANTIC_10},
|
||||
{0, 0, R_0283AC_SQ_VTX_SEMANTIC_11},
|
||||
{0, 0, R_0283B0_SQ_VTX_SEMANTIC_12},
|
||||
{0, 0, R_0283B4_SQ_VTX_SEMANTIC_13},
|
||||
{0, 0, R_0283B8_SQ_VTX_SEMANTIC_14},
|
||||
{0, 0, R_0283BC_SQ_VTX_SEMANTIC_15},
|
||||
{0, 0, R_0283C0_SQ_VTX_SEMANTIC_16},
|
||||
{0, 0, R_0283C4_SQ_VTX_SEMANTIC_17},
|
||||
{0, 0, R_0283C8_SQ_VTX_SEMANTIC_18},
|
||||
{0, 0, R_0283CC_SQ_VTX_SEMANTIC_19},
|
||||
{0, 0, R_0283D0_SQ_VTX_SEMANTIC_20},
|
||||
{0, 0, R_0283D4_SQ_VTX_SEMANTIC_21},
|
||||
{0, 0, R_0283D8_SQ_VTX_SEMANTIC_22},
|
||||
{0, 0, R_0283DC_SQ_VTX_SEMANTIC_23},
|
||||
{0, 0, R_0283E0_SQ_VTX_SEMANTIC_24},
|
||||
{0, 0, R_0283E4_SQ_VTX_SEMANTIC_25},
|
||||
{0, 0, R_0283E8_SQ_VTX_SEMANTIC_26},
|
||||
{0, 0, R_0283EC_SQ_VTX_SEMANTIC_27},
|
||||
{0, 0, R_0283F0_SQ_VTX_SEMANTIC_28},
|
||||
{0, 0, R_0283F4_SQ_VTX_SEMANTIC_29},
|
||||
{0, 0, R_0283F8_SQ_VTX_SEMANTIC_30},
|
||||
{0, 0, R_0283FC_SQ_VTX_SEMANTIC_31},
|
||||
{0, 0, R_0282D0_PA_SC_VPORT_ZMIN_0},
|
||||
{0, 0, R_0282D4_PA_SC_VPORT_ZMAX_0},
|
||||
{0, 0, R_028400_VGT_MAX_VTX_INDX},
|
||||
{0, 0, R_028404_VGT_MIN_VTX_INDX},
|
||||
{0, 0, R_028408_VGT_INDX_OFFSET},
|
||||
{0, 0, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX},
|
||||
{0, 0, R_028410_SX_ALPHA_TEST_CONTROL},
|
||||
{0, 0, R_028414_CB_BLEND_RED},
|
||||
{0, 0, R_028418_CB_BLEND_GREEN},
|
||||
{0, 0, R_02841C_CB_BLEND_BLUE},
|
||||
{0, 0, R_028420_CB_BLEND_ALPHA},
|
||||
{0, 0, R_028430_DB_STENCILREFMASK},
|
||||
{0, 0, R_028434_DB_STENCILREFMASK_BF},
|
||||
{0, 0, R_028438_SX_ALPHA_REF},
|
||||
{0, 0, R_02843C_PA_CL_VPORT_XSCALE_0},
|
||||
{0, 0, R_028440_PA_CL_VPORT_XOFFSET_0},
|
||||
{0, 0, R_028444_PA_CL_VPORT_YSCALE_0},
|
||||
{0, 0, R_028448_PA_CL_VPORT_YOFFSET_0},
|
||||
{0, 0, R_02844C_PA_CL_VPORT_ZSCALE_0},
|
||||
{0, 0, R_028450_PA_CL_VPORT_ZOFFSET_0},
|
||||
{0, 0, R_0285BC_PA_CL_UCP0_X},
|
||||
{0, 0, R_0285C0_PA_CL_UCP0_Y},
|
||||
{0, 0, R_0285C4_PA_CL_UCP0_Z},
|
||||
{0, 0, R_0285C8_PA_CL_UCP0_W},
|
||||
{0, 0, R_0285CC_PA_CL_UCP1_X},
|
||||
{0, 0, R_0285D0_PA_CL_UCP1_Y},
|
||||
{0, 0, R_0285D4_PA_CL_UCP1_Z},
|
||||
{0, 0, R_0285D8_PA_CL_UCP1_W},
|
||||
{0, 0, R_0285DC_PA_CL_UCP2_X},
|
||||
{0, 0, R_0285E0_PA_CL_UCP2_Y},
|
||||
{0, 0, R_0285E4_PA_CL_UCP2_Z},
|
||||
{0, 0, R_0285E8_PA_CL_UCP2_W},
|
||||
{0, 0, R_0285EC_PA_CL_UCP3_X},
|
||||
{0, 0, R_0285F0_PA_CL_UCP3_Y},
|
||||
{0, 0, R_0285F4_PA_CL_UCP3_Z},
|
||||
{0, 0, R_0285F8_PA_CL_UCP3_W},
|
||||
{0, 0, R_0285FC_PA_CL_UCP4_X},
|
||||
{0, 0, R_028600_PA_CL_UCP4_Y},
|
||||
{0, 0, R_028604_PA_CL_UCP4_Z},
|
||||
{0, 0, R_028608_PA_CL_UCP4_W},
|
||||
{0, 0, R_02860C_PA_CL_UCP5_X},
|
||||
{0, 0, R_028610_PA_CL_UCP5_Y},
|
||||
{0, 0, R_028614_PA_CL_UCP5_Z},
|
||||
{0, 0, R_028618_PA_CL_UCP5_W},
|
||||
{0, 0, R_02861C_SPI_VS_OUT_ID_0},
|
||||
{0, 0, R_028620_SPI_VS_OUT_ID_1},
|
||||
{0, 0, R_028624_SPI_VS_OUT_ID_2},
|
||||
{0, 0, R_028628_SPI_VS_OUT_ID_3},
|
||||
{0, 0, R_02862C_SPI_VS_OUT_ID_4},
|
||||
{0, 0, R_028630_SPI_VS_OUT_ID_5},
|
||||
{0, 0, R_028634_SPI_VS_OUT_ID_6},
|
||||
{0, 0, R_028638_SPI_VS_OUT_ID_7},
|
||||
{0, 0, R_02863C_SPI_VS_OUT_ID_8},
|
||||
{0, 0, R_028640_SPI_VS_OUT_ID_9},
|
||||
{0, 0, R_028644_SPI_PS_INPUT_CNTL_0},
|
||||
{0, 0, R_028648_SPI_PS_INPUT_CNTL_1},
|
||||
{0, 0, R_02864C_SPI_PS_INPUT_CNTL_2},
|
||||
{0, 0, R_028650_SPI_PS_INPUT_CNTL_3},
|
||||
{0, 0, R_028654_SPI_PS_INPUT_CNTL_4},
|
||||
{0, 0, R_028658_SPI_PS_INPUT_CNTL_5},
|
||||
{0, 0, R_02865C_SPI_PS_INPUT_CNTL_6},
|
||||
{0, 0, R_028660_SPI_PS_INPUT_CNTL_7},
|
||||
{0, 0, R_028664_SPI_PS_INPUT_CNTL_8},
|
||||
{0, 0, R_028668_SPI_PS_INPUT_CNTL_9},
|
||||
{0, 0, R_02866C_SPI_PS_INPUT_CNTL_10},
|
||||
{0, 0, R_028670_SPI_PS_INPUT_CNTL_11},
|
||||
{0, 0, R_028674_SPI_PS_INPUT_CNTL_12},
|
||||
{0, 0, R_028678_SPI_PS_INPUT_CNTL_13},
|
||||
{0, 0, R_02867C_SPI_PS_INPUT_CNTL_14},
|
||||
{0, 0, R_028680_SPI_PS_INPUT_CNTL_15},
|
||||
{0, 0, R_028684_SPI_PS_INPUT_CNTL_16},
|
||||
{0, 0, R_028688_SPI_PS_INPUT_CNTL_17},
|
||||
{0, 0, R_02868C_SPI_PS_INPUT_CNTL_18},
|
||||
{0, 0, R_028690_SPI_PS_INPUT_CNTL_19},
|
||||
{0, 0, R_028694_SPI_PS_INPUT_CNTL_20},
|
||||
{0, 0, R_028698_SPI_PS_INPUT_CNTL_21},
|
||||
{0, 0, R_02869C_SPI_PS_INPUT_CNTL_22},
|
||||
{0, 0, R_0286A0_SPI_PS_INPUT_CNTL_23},
|
||||
{0, 0, R_0286A4_SPI_PS_INPUT_CNTL_24},
|
||||
{0, 0, R_0286A8_SPI_PS_INPUT_CNTL_25},
|
||||
{0, 0, R_0286AC_SPI_PS_INPUT_CNTL_26},
|
||||
{0, 0, R_0286B0_SPI_PS_INPUT_CNTL_27},
|
||||
{0, 0, R_0286B4_SPI_PS_INPUT_CNTL_28},
|
||||
{0, 0, R_0286B8_SPI_PS_INPUT_CNTL_29},
|
||||
{0, 0, R_0286BC_SPI_PS_INPUT_CNTL_30},
|
||||
{0, 0, R_0286C0_SPI_PS_INPUT_CNTL_31},
|
||||
{0, 0, R_0286C4_SPI_VS_OUT_CONFIG},
|
||||
{0, 0, R_0286C8_SPI_THREAD_GROUPING},
|
||||
{0, 0, R_0286CC_SPI_PS_IN_CONTROL_0},
|
||||
{0, 0, R_0286D0_SPI_PS_IN_CONTROL_1},
|
||||
{0, 0, R_0286D4_SPI_INTERP_CONTROL_0},
|
||||
{0, 0, R_0286D8_SPI_INPUT_Z},
|
||||
{0, 0, R_0286DC_SPI_FOG_CNTL},
|
||||
{0, 0, R_0286E0_SPI_BARYC_CNTL},
|
||||
{0, 0, R_0286E4_SPI_PS_IN_CONTROL_2},
|
||||
{0, 0, R_0286E8_SPI_COMPUTE_INPUT_CNTL},
|
||||
{0, 0, R_028780_CB_BLEND0_CONTROL},
|
||||
{0, 0, R_028784_CB_BLEND1_CONTROL},
|
||||
{0, 0, R_028788_CB_BLEND2_CONTROL},
|
||||
{0, 0, R_02878C_CB_BLEND3_CONTROL},
|
||||
{0, 0, R_028790_CB_BLEND4_CONTROL},
|
||||
{0, 0, R_028794_CB_BLEND5_CONTROL},
|
||||
{0, 0, R_028798_CB_BLEND6_CONTROL},
|
||||
{0, 0, R_02879C_CB_BLEND7_CONTROL},
|
||||
{0, 0, R_028800_DB_DEPTH_CONTROL},
|
||||
{0, 0, R_02880C_DB_SHADER_CONTROL},
|
||||
{0, 0, R_028808_CB_COLOR_CONTROL},
|
||||
{0, 0, R_028810_PA_CL_CLIP_CNTL},
|
||||
{0, 0, R_028814_PA_SU_SC_MODE_CNTL},
|
||||
{0, 0, R_028818_PA_CL_VTE_CNTL},
|
||||
{0, 0, R_02881C_PA_CL_VS_OUT_CNTL},
|
||||
{0, 0, R_028820_PA_CL_NANINF_CNTL},
|
||||
{0, 0, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1},
|
||||
{1, 0, R_028840_SQ_PGM_START_PS},
|
||||
{0, 0, R_028844_SQ_PGM_RESOURCES_PS},
|
||||
{0, 0, R_028848_SQ_PGM_RESOURCES_2_PS},
|
||||
{0, 0, R_02884C_SQ_PGM_EXPORTS_PS},
|
||||
{1, 0, R_02885C_SQ_PGM_START_VS},
|
||||
{0, 0, R_028860_SQ_PGM_RESOURCES_VS},
|
||||
{0, 0, R_028864_SQ_PGM_RESOURCES_2_VS},
|
||||
{1, 0, R_0288A4_SQ_PGM_START_FS},
|
||||
{0, 0, R_0288A8_SQ_PGM_RESOURCES_FS},
|
||||
{0, 0, R_0288EC_SQ_LDS_ALLOC_PS},
|
||||
{0, 0, R_028900_SQ_ESGS_RING_ITEMSIZE},
|
||||
{0, 0, R_028904_SQ_GSVS_RING_ITEMSIZE},
|
||||
{0, 0, R_028908_SQ_ESTMP_RING_ITEMSIZE},
|
||||
{0, 0, R_02890C_SQ_GSTMP_RING_ITEMSIZE},
|
||||
{0, 0, R_028910_SQ_VSTMP_RING_ITEMSIZE},
|
||||
{0, 0, R_028914_SQ_PSTMP_RING_ITEMSIZE},
|
||||
{0, 0, R_02891C_SQ_GS_VERT_ITEMSIZE},
|
||||
{0, 0, R_028920_SQ_GS_VERT_ITEMSIZE_1},
|
||||
{0, 0, R_028924_SQ_GS_VERT_ITEMSIZE_2},
|
||||
{0, 0, R_028928_SQ_GS_VERT_ITEMSIZE_3},
|
||||
{1, 0, R_028940_ALU_CONST_CACHE_PS_0},
|
||||
{1, 0, R_028980_ALU_CONST_CACHE_VS_0},
|
||||
{0, 0, R_028A00_PA_SU_POINT_SIZE},
|
||||
{0, 0, R_028A04_PA_SU_POINT_MINMAX},
|
||||
{0, 0, R_028A08_PA_SU_LINE_CNTL},
|
||||
{0, 0, R_028A10_VGT_OUTPUT_PATH_CNTL},
|
||||
{0, 0, R_028A14_VGT_HOS_CNTL},
|
||||
{0, 0, R_028A18_VGT_HOS_MAX_TESS_LEVEL},
|
||||
{0, 0, R_028A1C_VGT_HOS_MIN_TESS_LEVEL},
|
||||
{0, 0, R_028A20_VGT_HOS_REUSE_DEPTH},
|
||||
{0, 0, R_028A24_VGT_GROUP_PRIM_TYPE},
|
||||
{0, 0, R_028A28_VGT_GROUP_FIRST_DECR},
|
||||
{0, 0, R_028A2C_VGT_GROUP_DECR},
|
||||
{0, 0, R_028A30_VGT_GROUP_VECT_0_CNTL},
|
||||
{0, 0, R_028A34_VGT_GROUP_VECT_1_CNTL},
|
||||
{0, 0, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL},
|
||||
{0, 0, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL},
|
||||
{0, 0, R_028A40_VGT_GS_MODE},
|
||||
{0, 0, R_028A48_PA_SC_MODE_CNTL_0},
|
||||
{0, 0, R_028A4C_PA_SC_MODE_CNTL_1},
|
||||
{0, 0, R_028AB4_VGT_REUSE_OFF},
|
||||
{0, 0, R_028AB8_VGT_VTX_CNT_EN},
|
||||
{0, 0, R_028ABC_DB_HTILE_SURFACE},
|
||||
{0, 0, R_028AC0_DB_SRESULTS_COMPARE_STATE0},
|
||||
{0, 0, R_028AC4_DB_SRESULTS_COMPARE_STATE1},
|
||||
{0, 0, R_028AC8_DB_PRELOAD_CONTROL},
|
||||
{0, 0, R_028B54_VGT_SHADER_STAGES_EN},
|
||||
{0, 0, R_028B70_DB_ALPHA_TO_MASK},
|
||||
{0, 0, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL},
|
||||
{0, 0, R_028B7C_PA_SU_POLY_OFFSET_CLAMP},
|
||||
{0, 0, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE},
|
||||
{0, 0, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET},
|
||||
{0, 0, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE},
|
||||
{0, 0, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET},
|
||||
{0, 0, R_028B94_VGT_STRMOUT_CONFIG},
|
||||
{0, 0, R_028B98_VGT_STRMOUT_BUFFER_CONFIG},
|
||||
{0, 0, R_028C00_PA_SC_LINE_CNTL},
|
||||
{0, 0, R_028C04_PA_SC_AA_CONFIG},
|
||||
{0, 0, R_028C08_PA_SU_VTX_CNTL},
|
||||
{0, 0, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ},
|
||||
{0, 0, R_028C10_PA_CL_GB_VERT_DISC_ADJ},
|
||||
{0, 0, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ},
|
||||
{0, 0, R_028C18_PA_CL_GB_HORZ_DISC_ADJ},
|
||||
{0, 0, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX},
|
||||
{0, 0, R_028C3C_PA_SC_AA_MASK},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028C60_CB_COLOR0_BASE},
|
||||
{0, 0, R_028C64_CB_COLOR0_PITCH},
|
||||
{0, 0, R_028C68_CB_COLOR0_SLICE},
|
||||
{0, 0, R_028C6C_CB_COLOR0_VIEW},
|
||||
{1, 0, R_028C70_CB_COLOR0_INFO},
|
||||
{0, 0, R_028C74_CB_COLOR0_ATTRIB},
|
||||
{0, 0, R_028C78_CB_COLOR0_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028C9C_CB_COLOR1_BASE},
|
||||
{0, 0, R_028CA0_CB_COLOR1_PITCH},
|
||||
{0, 0, R_028CA4_CB_COLOR1_SLICE},
|
||||
{0, 0, R_028CA8_CB_COLOR1_VIEW},
|
||||
{1, 0, R_028CAC_CB_COLOR1_INFO},
|
||||
{0, 0, R_028CB0_CB_COLOR1_ATTRIB},
|
||||
{0, 0, R_028CB8_CB_COLOR1_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028CD8_CB_COLOR2_BASE},
|
||||
{0, 0, R_028CDC_CB_COLOR2_PITCH},
|
||||
{0, 0, R_028CE0_CB_COLOR2_SLICE},
|
||||
{0, 0, R_028CE4_CB_COLOR2_VIEW},
|
||||
{1, 0, R_028CE8_CB_COLOR2_INFO},
|
||||
{0, 0, R_028CEC_CB_COLOR2_ATTRIB},
|
||||
{0, 0, R_028CF0_CB_COLOR2_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028D14_CB_COLOR3_BASE},
|
||||
{0, 0, R_028D18_CB_COLOR3_PITCH},
|
||||
{0, 0, R_028D1C_CB_COLOR3_SLICE},
|
||||
{0, 0, R_028D20_CB_COLOR3_VIEW},
|
||||
{1, 0, R_028D24_CB_COLOR3_INFO},
|
||||
{0, 0, R_028D28_CB_COLOR3_ATTRIB},
|
||||
{0, 0, R_028D2C_CB_COLOR3_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028D50_CB_COLOR4_BASE},
|
||||
{0, 0, R_028D54_CB_COLOR4_PITCH},
|
||||
{0, 0, R_028D58_CB_COLOR4_SLICE},
|
||||
{0, 0, R_028D5C_CB_COLOR4_VIEW},
|
||||
{1, 0, R_028D60_CB_COLOR4_INFO},
|
||||
{0, 0, R_028D64_CB_COLOR4_ATTRIB},
|
||||
{0, 0, R_028D68_CB_COLOR4_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028D8C_CB_COLOR5_BASE},
|
||||
{0, 0, R_028D90_CB_COLOR5_PITCH},
|
||||
{0, 0, R_028D94_CB_COLOR5_SLICE},
|
||||
{0, 0, R_028D98_CB_COLOR5_VIEW},
|
||||
{1, 0, R_028D9C_CB_COLOR5_INFO},
|
||||
{0, 0, R_028DA0_CB_COLOR5_ATTRIB},
|
||||
{0, 0, R_028DA4_CB_COLOR5_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028DC8_CB_COLOR6_BASE},
|
||||
{0, 0, R_028DCC_CB_COLOR6_PITCH},
|
||||
{0, 0, R_028DD0_CB_COLOR6_SLICE},
|
||||
{0, 0, R_028DD4_CB_COLOR6_VIEW},
|
||||
{1, 0, R_028DD8_CB_COLOR6_INFO},
|
||||
{0, 0, R_028DDC_CB_COLOR6_ATTRIB},
|
||||
{0, 0, R_028DE0_CB_COLOR6_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028E04_CB_COLOR7_BASE},
|
||||
{0, 0, R_028E08_CB_COLOR7_PITCH},
|
||||
{0, 0, R_028E0C_CB_COLOR7_SLICE},
|
||||
{0, 0, R_028E10_CB_COLOR7_VIEW},
|
||||
{1, 0, R_028E14_CB_COLOR7_INFO},
|
||||
{0, 0, R_028E18_CB_COLOR7_ATTRIB},
|
||||
{0, 0, R_028E1C_CB_COLOR7_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028E40_CB_COLOR8_BASE},
|
||||
{0, 0, R_028E44_CB_COLOR8_PITCH},
|
||||
{0, 0, R_028E48_CB_COLOR8_SLICE},
|
||||
{0, 0, R_028E4C_CB_COLOR8_VIEW},
|
||||
{1, 0, R_028E50_CB_COLOR8_INFO},
|
||||
{0, 0, R_028E54_CB_COLOR8_ATTRIB},
|
||||
{0, 0, R_028E58_CB_COLOR8_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028E5C_CB_COLOR9_BASE},
|
||||
{0, 0, R_028E60_CB_COLOR9_PITCH},
|
||||
{0, 0, R_028E64_CB_COLOR9_SLICE},
|
||||
{0, 0, R_028E68_CB_COLOR9_VIEW},
|
||||
{1, 0, R_028E6C_CB_COLOR9_INFO},
|
||||
{0, 0, R_028E70_CB_COLOR9_ATTRIB},
|
||||
{0, 0, R_028E74_CB_COLOR9_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028E78_CB_COLOR10_BASE},
|
||||
{0, 0, R_028E7C_CB_COLOR10_PITCH},
|
||||
{0, 0, R_028E80_CB_COLOR10_SLICE},
|
||||
{0, 0, R_028E84_CB_COLOR10_VIEW},
|
||||
{1, 0, R_028E88_CB_COLOR10_INFO},
|
||||
{0, 0, R_028E8C_CB_COLOR10_ATTRIB},
|
||||
{0, 0, R_028E90_CB_COLOR10_DIM},
|
||||
{0, 0, GROUP_FORCE_NEW_BLOCK},
|
||||
{1, 0, R_028E94_CB_COLOR11_BASE},
|
||||
{0, 0, R_028E98_CB_COLOR11_PITCH},
|
||||
{0, 0, R_028E9C_CB_COLOR11_SLICE},
|
||||
{0, 0, R_028EA0_CB_COLOR11_VIEW},
|
||||
{1, 0, R_028EA4_CB_COLOR11_INFO},
|
||||
{0, 0, R_028EA8_CB_COLOR11_ATTRIB},
|
||||
{0, 0, R_028EAC_CB_COLOR11_DIM},
|
||||
};
|
||||
|
||||
/* SHADER RESOURCE R600/R700 */
|
||||
static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
|
||||
{
|
||||
struct r600_reg r600_shader_resource[] = {
|
||||
{0, 0, R_030000_RESOURCE0_WORD0},
|
||||
{0, 0, R_030004_RESOURCE0_WORD1},
|
||||
{1, 0, R_030008_RESOURCE0_WORD2},
|
||||
{1, 0, R_03000C_RESOURCE0_WORD3},
|
||||
{0, 0, R_030010_RESOURCE0_WORD4},
|
||||
{0, 0, R_030014_RESOURCE0_WORD5},
|
||||
{0, 0, R_030018_RESOURCE0_WORD6},
|
||||
{0, 0, R_03001C_RESOURCE0_WORD7},
|
||||
};
|
||||
unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
|
||||
|
||||
for (int i = 0; i < nreg; i++) {
|
||||
r600_shader_resource[i].offset += offset;
|
||||
}
|
||||
return r600_context_add_block(ctx, r600_shader_resource, nreg);
|
||||
}
|
||||
|
||||
/* SHADER SAMPLER R600/R700 */
|
||||
static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
|
||||
{
|
||||
struct r600_reg r600_shader_sampler[] = {
|
||||
{0, 0, R_03C000_SQ_TEX_SAMPLER_WORD0_0},
|
||||
{0, 0, R_03C004_SQ_TEX_SAMPLER_WORD1_0},
|
||||
{0, 0, R_03C008_SQ_TEX_SAMPLER_WORD2_0},
|
||||
};
|
||||
unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
|
||||
|
||||
for (int i = 0; i < nreg; i++) {
|
||||
r600_shader_sampler[i].offset += offset;
|
||||
}
|
||||
return r600_context_add_block(ctx, r600_shader_sampler, nreg);
|
||||
}
|
||||
|
||||
int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
|
||||
{
|
||||
int r;
|
||||
|
||||
memset(ctx, 0, sizeof(struct r600_context));
|
||||
ctx->radeon = radeon;
|
||||
LIST_INITHEAD(&ctx->query_list);
|
||||
/* initialize groups */
|
||||
r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_CONFIG], EVERGREEN_CONFIG_REG_OFFSET, EVERGREEN_CONFIG_REG_END);
|
||||
if (r) {
|
||||
goto out_err;
|
||||
}
|
||||
r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_LOOP_CONST], EVERGREEN_LOOP_CONST_OFFSET, EVERGREEN_LOOP_CONST_END);
|
||||
if (r) {
|
||||
goto out_err;
|
||||
}
|
||||
r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_BOOL_CONST], EVERGREEN_BOOL_CONST_OFFSET, EVERGREEN_BOOL_CONST_END);
|
||||
if (r) {
|
||||
goto out_err;
|
||||
}
|
||||
r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_SAMPLER], EVERGREEN_SAMPLER_OFFSET, EVERGREEN_SAMPLER_END);
|
||||
if (r) {
|
||||
goto out_err;
|
||||
}
|
||||
r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_RESOURCE], EVERGREEN_RESOURCE_OFFSET, EVERGREEN_RESOURCE_END);
|
||||
if (r) {
|
||||
goto out_err;
|
||||
}
|
||||
r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_CONTEXT], EVERGREEN_CONTEXT_REG_OFFSET, EVERGREEN_CONTEXT_REG_END);
|
||||
if (r) {
|
||||
goto out_err;
|
||||
}
|
||||
ctx->ngroups = EVERGREEN_NGROUPS;
|
||||
|
||||
/* add blocks */
|
||||
r = r600_context_add_block(ctx, evergreen_reg_list, sizeof(evergreen_reg_list)/sizeof(struct r600_reg));
|
||||
if (r)
|
||||
goto out_err;
|
||||
|
||||
/* PS SAMPLER */
|
||||
for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
|
||||
r = r600_state_sampler_init(ctx, offset);
|
||||
if (r)
|
||||
goto out_err;
|
||||
}
|
||||
/* VS SAMPLER */
|
||||
for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
|
||||
r = r600_state_sampler_init(ctx, offset);
|
||||
if (r)
|
||||
goto out_err;
|
||||
}
|
||||
/* PS RESOURCE */
|
||||
for (int j = 0, offset = 0; j < 176; j++, offset += 0x1C) {
|
||||
r = evergreen_state_resource_init(ctx, offset);
|
||||
if (r)
|
||||
goto out_err;
|
||||
}
|
||||
/* VS RESOURCE */
|
||||
for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x1C) {
|
||||
r = evergreen_state_resource_init(ctx, offset);
|
||||
if (r)
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
/* allocate cs variables */
|
||||
ctx->nreloc = RADEON_CTX_MAX_PM4;
|
||||
ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
|
||||
if (ctx->reloc == NULL) {
|
||||
r = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
ctx->bo = calloc(ctx->nreloc, sizeof(void *));
|
||||
if (ctx->bo == NULL) {
|
||||
r = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
|
||||
ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
|
||||
if (ctx->pm4 == NULL) {
|
||||
r = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
return 0;
|
||||
out_err:
|
||||
r600_context_fini(ctx);
|
||||
return r;
|
||||
}
|
||||
|
||||
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
|
||||
{
|
||||
struct radeon_bo *cb[12];
|
||||
unsigned ndwords = 9;
|
||||
|
||||
if (draw->indices) {
|
||||
ndwords = 13;
|
||||
/* make sure there is enough relocation space before scheduling draw */
|
||||
if (ctx->creloc >= (ctx->nreloc - 1)) {
|
||||
r600_context_flush(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
/* find number of color buffer */
|
||||
cb[0] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028C60_CB_COLOR0_BASE);
|
||||
cb[1] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028C9C_CB_COLOR1_BASE);
|
||||
cb[2] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028CD8_CB_COLOR2_BASE);
|
||||
cb[3] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D14_CB_COLOR3_BASE);
|
||||
cb[4] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D50_CB_COLOR4_BASE);
|
||||
cb[5] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D8C_CB_COLOR5_BASE);
|
||||
cb[6] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028DC8_CB_COLOR6_BASE);
|
||||
cb[7] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E04_CB_COLOR7_BASE);
|
||||
cb[8] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E40_CB_COLOR8_BASE);
|
||||
cb[9] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E5C_CB_COLOR9_BASE);
|
||||
cb[10] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E78_CB_COLOR10_BASE);
|
||||
cb[11] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E94_CB_COLOR11_BASE);
|
||||
for (int i = 0; i < 12; i++) {
|
||||
if (cb[i]) {
|
||||
ndwords += 7;
|
||||
}
|
||||
}
|
||||
|
||||
if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
|
||||
/* need to flush */
|
||||
r600_context_flush(ctx);
|
||||
}
|
||||
/* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
|
||||
if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
|
||||
R600_ERR("context is too big to be scheduled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* enough room to copy packet */
|
||||
r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_CONFIG], PKT3_SET_CONFIG_REG);
|
||||
r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_CONTEXT], PKT3_SET_CONTEXT_REG);
|
||||
r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_RESOURCE], PKT3_SET_RESOURCE);
|
||||
r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_SAMPLER], PKT3_SET_SAMPLER);
|
||||
|
||||
/* draw packet */
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
|
||||
if (draw->indices) {
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = 0;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = 0;
|
||||
r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], radeon_bo_pb_get_bo(draw->indices->pb));
|
||||
} else {
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
|
||||
}
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
|
||||
|
||||
/* flush color buffer */
|
||||
for (int i = 0; i < 8; i++) {
|
||||
if (cb[i]) {
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
|
||||
S_0085F0_CB_ACTION_ENA(1);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
|
||||
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
|
||||
ctx->pm4[ctx->pm4_cdwords++] = 0;
|
||||
r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* all dirty state have been scheduled in current cs */
|
||||
ctx->pm4_dirty_cdwords = 0;
|
||||
}
|
||||
|
||||
static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
|
||||
{
|
||||
struct r600_group_block *block;
|
||||
unsigned id;
|
||||
|
||||
offset -= ctx->groups[EVERGREEN_GROUP_RESOURCE].start_offset;
|
||||
id = ctx->groups[EVERGREEN_GROUP_RESOURCE].offset_block_id[offset >> 2];
|
||||
block = &ctx->groups[EVERGREEN_GROUP_RESOURCE].blocks[id];
|
||||
block->pm4[0] = state->regs[0].value;
|
||||
block->pm4[1] = state->regs[1].value;
|
||||
block->pm4[2] = state->regs[2].value;
|
||||
block->pm4[3] = state->regs[3].value;
|
||||
block->pm4[4] = state->regs[4].value;
|
||||
block->pm4[5] = state->regs[5].value;
|
||||
block->pm4[6] = state->regs[6].value;
|
||||
block->pm4[7] = state->regs[7].value;
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
|
||||
radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
|
||||
if (state->regs[0].bo) {
|
||||
/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
|
||||
* we have single case btw VERTEX & TEXTURE resource
|
||||
*/
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
|
||||
} else {
|
||||
/* TEXTURE RESOURCE */
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
|
||||
}
|
||||
block->status |= R600_BLOCK_STATUS_ENABLED;
|
||||
block->status |= R600_BLOCK_STATUS_DIRTY;
|
||||
ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
|
||||
}
|
||||
|
||||
void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
|
||||
{
|
||||
unsigned offset = R_030000_RESOURCE0_WORD0 + 0x20 * rid;
|
||||
|
||||
evergreen_resource_set(ctx, state, offset);
|
||||
}
|
||||
|
||||
void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
|
||||
{
|
||||
unsigned offset = R_030000_RESOURCE0_WORD0 + 0x1600 + 0x20 * rid;
|
||||
|
||||
evergreen_resource_set(ctx, state, offset);
|
||||
}
|
||||
|
|
@ -38,6 +38,7 @@
|
|||
#include "util/u_inlines.h"
|
||||
#include <pipebuffer/pb_bufmgr.h>
|
||||
|
||||
#define GROUP_FORCE_NEW_BLOCK 0
|
||||
struct radeon_ws_bo {
|
||||
struct pipe_reference reference;
|
||||
struct pb_buffer *pb;
|
||||
|
|
@ -93,7 +94,7 @@ static int r600_group_id_register_offset(unsigned offset)
|
|||
return -1;
|
||||
}
|
||||
|
||||
static int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
|
||||
int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
|
||||
{
|
||||
struct r600_group_block *block, *tmp;
|
||||
struct r600_group *group;
|
||||
|
|
@ -101,13 +102,22 @@ static int r600_context_add_block(struct r600_context *ctx, const struct r600_re
|
|||
|
||||
for (unsigned i = 0, n = 0; i < nreg; i += n) {
|
||||
u32 j, r;
|
||||
/* find number of consecutive registers */
|
||||
for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) {
|
||||
if (r != reg[j].offset) {
|
||||
break;
|
||||
|
||||
/* register that need relocation are in their own group */
|
||||
n = 1;
|
||||
if (!reg[i].need_bo) {
|
||||
/* find number of consecutive registers */
|
||||
for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) {
|
||||
if (reg[i].need_bo || r != reg[j].offset) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ignore new block balise */
|
||||
if (reg[i].offset == GROUP_FORCE_NEW_BLOCK)
|
||||
continue;
|
||||
|
||||
/* find into which group this block is */
|
||||
group_id = r600_group_id_register_offset(reg[i].offset);
|
||||
assert(group_id >= 0);
|
||||
|
|
@ -158,7 +168,7 @@ static int r600_context_add_block(struct r600_context *ctx, const struct r600_re
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset)
|
||||
int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset)
|
||||
{
|
||||
group->start_offset = start_offset;
|
||||
group->end_offset = end_offset;
|
||||
|
|
@ -702,7 +712,7 @@ out_err:
|
|||
return r;
|
||||
}
|
||||
|
||||
static void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo)
|
||||
void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo)
|
||||
{
|
||||
int i, reloc_id;
|
||||
|
||||
|
|
@ -770,8 +780,8 @@ static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx
|
|||
block->pm4[4] = state->regs[4].value;
|
||||
block->pm4[5] = state->regs[5].value;
|
||||
block->pm4[6] = state->regs[6].value;
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, block->reloc[1].bo);
|
||||
radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, block->reloc[2].bo);
|
||||
radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
|
||||
radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
|
||||
if (state->regs[0].bo) {
|
||||
/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
|
||||
* we have single case btw VERTEX & TEXTURE resource
|
||||
|
|
@ -859,7 +869,7 @@ void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r60
|
|||
}
|
||||
}
|
||||
|
||||
static inline void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode)
|
||||
void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode)
|
||||
{
|
||||
struct radeon_bo *bo;
|
||||
int id;
|
||||
|
|
@ -887,7 +897,7 @@ static inline void r600_context_group_emit_dirty(struct r600_context *ctx, struc
|
|||
}
|
||||
}
|
||||
|
||||
static struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset)
|
||||
struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset)
|
||||
{
|
||||
struct r600_group_block *block;
|
||||
unsigned id;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue