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i965: Replace HW_REG with ARF/FIXED_GRF.

Browse source 
HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to
look at different fields for type, abs, negate, writemask, swizzle, and
a second file. They also caused annoying problems like immediate sources
being considered scheduling barriers (commit 6148e94e2) and other such
nonsense.

Instead use ARF/FIXED_GRF/MRF for fixed registers in those files.

After a sufficient amount of time has passed since "GRF" was used, we
can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful.

Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2015-10-26 17:52:57 -07:00
parent 4b0fbebf02
commit b3315a6f56
13 changed files with 157 additions and 211 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

120
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -77,7 +77,8 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
/* This will be the case for almost all instructions. */
switch (dst.file) {
case VGRF:
case HW_REG:
case ARF:
case FIXED_GRF:
case MRF:
case ATTR:
this->regs_written = DIV_ROUND_UP(dst.component_size(exec_size),
@ -423,7 +424,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
fs_reg::fs_reg(struct brw_reg reg) :
backend_reg(reg)
{
this->file = HW_REG;
this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->subreg_offset = 0;
this->reladdr = NULL;
@ -439,24 +440,17 @@ fs_reg::fs_reg(struct brw_reg reg) :
bool
fs_reg::equals(const fs_reg &r) const
{
return (file == r.file &&
nr == r.nr &&
return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
subreg_offset == r.subreg_offset &&
type == r.type &&
negate == r.negate &&
abs == r.abs &&
!reladdr && !r.reladdr &&
(file != HW_REG ||
memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0) &&
(file != IMM || d == r.d) &&
stride == r.stride);
}
fs_reg &
fs_reg::set_smear(unsigned subreg)
{
assert(file != HW_REG && file != IMM);
assert(file != ARF && file != FIXED_GRF && file != IMM);
subreg_offset = subreg * type_sz(type);
stride = 0;
return *this;
@ -471,7 +465,7 @@ fs_reg::is_contiguous() const
unsigned
fs_reg::component_size(unsigned width) const
{
const unsigned stride = (file != HW_REG ? this->stride :
const unsigned stride = ((file != ARF && file != FIXED_GRF) ? this->stride :
hstride == 0 ? 0 :
1 << (hstride - 1));
return MAX2(width * stride, 1) * type_sz(type);
@ -857,9 +851,10 @@ fs_inst::regs_read(int arg) const
case UNIFORM:
case IMM:
return 1;
case ARF:
case FIXED_GRF:
case VGRF:
case ATTR:
case HW_REG:
return DIV_ROUND_UP(components_read(arg) *
src[arg].component_size(exec_size),
REG_SIZE);
@ -1596,12 +1591,12 @@ fs_visitor::assign_urb_setup()
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->opcode == FS_OPCODE_LINTERP) {
assert(inst->src[1].file == HW_REG);
assert(inst->src[1].file == FIXED_GRF);
inst->src[1].nr += urb_start;
}
if (inst->opcode == FS_OPCODE_CINTERP) {
assert(inst->src[0].file == HW_REG);
assert(inst->src[0].file == FIXED_GRF);
inst->src[0].nr += urb_start;
}
}
@ -1682,7 +1677,7 @@ fs_visitor::assign_gs_urb_setup()
inst->base_mrf = -1;
}
/* Rewrite all ATTR file references to HW_REGs. */
/* Rewrite all ATTR file references to GRFs. */
convert_attr_sources_to_hw_regs(inst);
}
}
@ -2797,7 +2792,7 @@ fs_visitor::emit_repclear_shader()
assign_curb_setup();
/* Now that we have the uniform assigned, go ahead and force it to a vec4. */
assert(mov->src[0].file == HW_REG);
assert(mov->src[0].file == FIXED_GRF);
mov->src[0] = brw_vec4_grf(mov->src[0].nr, 0);
}
@ -2876,10 +2871,7 @@ clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len)
/* Clear the flag for registers that actually got read (as expected). */
for (int i = 0; i < inst->sources; i++) {
int grf;
if (inst->src[i].file == VGRF) {
grf = inst->src[i].nr;
} else if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
if (inst->src[i].file == VGRF || inst->src[i].file == FIXED_GRF) {
grf = inst->src[i].nr;
} else {
continue;
@ -4619,6 +4611,9 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fprintf(file, "+%d.%d",
inst->dst.reg_offset, inst->dst.subreg_offset);
break;
case FIXED_GRF:
fprintf(file, "g%d", inst->dst.nr);
break;
case MRF:
fprintf(file, "m%d", inst->dst.nr);
break;
@ -4631,29 +4626,23 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case ATTR:
fprintf(file, "***attr%d***", inst->dst.nr + inst->dst.reg_offset);
break;
case HW_REG:
if (inst->dst.brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (inst->dst.nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->dst.subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->dst.subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->dst.nr & 0xf,
inst->dst.subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->dst.nr & 0xf,
inst->dst.subnr);
break;
}
} else {
fprintf(file, "hw_reg%d", inst->dst.nr);
case ARF:
switch (inst->dst.nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->dst.subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->dst.subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
break;
}
if (inst->dst.subnr)
fprintf(file, "+%d", inst->dst.subnr);
@ -4676,6 +4665,9 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fprintf(file, "+%d.%d", inst->src[i].reg_offset,
inst->src[i].subreg_offset);
break;
case FIXED_GRF:
fprintf(file, "g%d", inst->src[i].nr);
break;
case MRF:
fprintf(file, "***m%d***", inst->src[i].nr);
break;
@ -4719,29 +4711,23 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
break;
}
break;
case HW_REG:
if (inst->src[i].brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (inst->src[i].nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->src[i].subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->src[i].subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->src[i].nr & 0xf,
inst->src[i].subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf,
inst->src[i].subnr);
break;
}
} else {
fprintf(file, "hw_reg%d", inst->src[i].nr);
case ARF:
switch (inst->src[i].nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->src[i].subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->src[i].subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
break;
}
if (inst->src[i].subnr)
fprintf(file, "+%d", inst->src[i].subnr);

5
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -70,9 +70,10 @@ offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
switch (reg.file) {
case BAD_FILE:
break;
case VGRF:
case ARF:
case FIXED_GRF:
case MRF:
case HW_REG:
case VGRF:
case ATTR:
return byte_offset(reg,
delta * reg.component_size(bld.dispatch_width()));

3
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
View file

@ -387,7 +387,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
switch (entry->src.file) {
case UNIFORM:
case BAD_FILE:
case HW_REG:
case ARF:
case FIXED_GRF:
inst->src[arg].reg_offset = entry->src.reg_offset;
inst->src[arg].subreg_offset = entry->src.subreg_offset;
break;

3
src/mesa/drivers/dri/i965/brw_fs_cse.cpp
View file

@ -226,7 +226,8 @@ fs_visitor::opt_cse_local(bblock_t *block)
foreach_inst_in_block(fs_inst, inst, block) {
/* Skip some cases. */
if (is_expression(this, inst) && !inst->is_partial_write() &&
(inst->dst.file != HW_REG || inst->dst.is_null()))
((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
inst->dst.is_null()))
{
bool found = false;
bool negate = false;

7
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -37,6 +37,9 @@ static enum brw_reg_file
brw_file_from_reg(fs_reg *reg)
{
switch (reg->file) {
case ARF:
return BRW_ARCHITECTURE_REGISTER_FILE;
case FIXED_GRF:
case VGRF:
return BRW_GENERAL_REGISTER_FILE;
case MRF:
@ -44,7 +47,6 @@ brw_file_from_reg(fs_reg *reg)
case IMM:
return BRW_IMMEDIATE_VALUE;
case BAD_FILE:
case HW_REG:
case ATTR:
case UNIFORM:
unreachable("not reached");
@ -118,7 +120,8 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
unreachable("not reached");
}
break;
case HW_REG:
case ARF:
case FIXED_GRF:
brw_reg = *static_cast<struct brw_reg *>(reg);
break;
case BAD_FILE:

5
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View file

@ -366,13 +366,12 @@ void fs_visitor::calculate_payload_ranges(int payload_node_count,
else
use_ip = ip;
/* Note that UNIFORM args have been turned into FIXED_HW_REG by
/* Note that UNIFORM args have been turned into FIXED_GRF by
* assign_curbe_setup(), and interpolation uses fixed hardware regs from
* the start (see interp_reg()).
*/
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
if (inst->src[i].file == FIXED_GRF) {
int node_nr = inst->src[i].nr;
if (node_nr >= payload_node_count)
continue;

9
src/mesa/drivers/dri/i965/brw_ir_fs.h
View file

@ -97,8 +97,9 @@ byte_offset(fs_reg reg, unsigned delta)
case MRF:
reg.nr += delta / 32;
break;
case ARF:
case FIXED_GRF:
case IMM:
case HW_REG:
case UNIFORM:
assert(delta == 0);
}
@ -121,7 +122,8 @@ horiz_offset(fs_reg reg, unsigned delta)
case MRF:
case ATTR:
return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
case HW_REG:
case ARF:
case FIXED_GRF:
assert(delta == 0);
}
return reg;
@ -163,8 +165,9 @@ half(fs_reg reg, unsigned idx)
case MRF:
return horiz_offset(reg, 8 * idx);
case ARF:
case FIXED_GRF:
case ATTR:
case HW_REG:
unreachable("Cannot take half of this register type");
}
return reg;

6
src/mesa/drivers/dri/i965/brw_ir_vec4.h
View file

@ -68,7 +68,8 @@ retype(src_reg reg, enum brw_reg_type type)
static inline src_reg
offset(src_reg reg, unsigned delta)
{
assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
assert(delta == 0 ||
(reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
reg.reg_offset += delta;
return reg;
}
@ -132,7 +133,8 @@ retype(dst_reg reg, enum brw_reg_type type)
static inline dst_reg
offset(dst_reg reg, unsigned delta)
{
assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
assert(delta == 0 ||
(reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
reg.reg_offset += delta;
return reg;
}

53
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
View file

@ -585,8 +585,7 @@ fs_instruction_scheduler::count_reads_remaining(backend_instruction *be)
if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]++;
} else if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
} else if (inst->src[i].file == FIXED_GRF) {
if (inst->src[i].nr >= hw_reg_count)
continue;
@ -670,8 +669,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]--;
} else if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
} else if (inst->src[i].file == FIXED_GRF &&
inst->src[i].nr < hw_reg_count) {
for (int off = 0; off < inst->regs_read(i); off++)
hw_reads_remaining[inst->src[i].nr + off]--;
@ -700,8 +698,7 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
reads_remaining[inst->src[i].nr] == 1)
benefit += v->alloc.sizes[inst->src[i].nr];
if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
if (inst->src[i].file == FIXED_GRF &&
inst->src[i].nr < hw_reg_count) {
for (int off = 0; off < inst->regs_read(i); off++) {
int reg = inst->src[i].nr + off;
@ -959,9 +956,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], n);
}
}
} else if (inst->src[i].file == HW_REG &&
(inst->src[i].brw_reg::file ==
BRW_GENERAL_REGISTER_FILE)) {
} else if (inst->src[i].file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_read(i); r++)
add_dep(last_grf_write[inst->src[i].nr + r], n);
@ -972,9 +967,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_accumulator_write, n);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
inst->src[i].file != UNIFORM &&
(inst->src[i].file != HW_REG ||
inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF);
add_barrier_deps(n);
}
@ -1024,8 +1017,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_mrf_write[reg], n);
last_mrf_write[reg] = n;
}
} else if (inst->dst.file == HW_REG &&
inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
} else if (inst->dst.file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_written; r++)
last_grf_write[inst->dst.nr + r] = n;
@ -1085,9 +1077,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(n, last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], 0);
}
}
} else if (inst->src[i].file == HW_REG &&
(inst->src[i].brw_reg::file ==
BRW_GENERAL_REGISTER_FILE)) {
} else if (inst->src[i].file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_read(i); r++)
add_dep(n, last_grf_write[inst->src[i].nr + r], 0);
@ -1098,9 +1088,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(n, last_accumulator_write, 0);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
inst->src[i].file != UNIFORM &&
(inst->src[i].file != HW_REG ||
inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF);
add_barrier_deps(n);
}
@ -1149,8 +1137,7 @@ fs_instruction_scheduler::calculate_deps()
last_mrf_write[reg] = n;
}
} else if (inst->dst.file == HW_REG &&
inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
} else if (inst->dst.file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_written; r++)
last_grf_write[inst->dst.nr + r] = n;
@ -1218,18 +1205,14 @@ vec4_instruction_scheduler::calculate_deps()
if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(last_grf_write[inst->src[i].nr + j], n);
} else if (inst->src[i].file == HW_REG &&
(inst->src[i].brw_reg::file ==
BRW_GENERAL_REGISTER_FILE)) {
} else if (inst->src[i].file == FIXED_GRF) {
add_dep(last_fixed_grf_write, n);
} else if (inst->src[i].is_accumulator()) {
assert(last_accumulator_write);
add_dep(last_accumulator_write, n);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
inst->src[i].file != UNIFORM &&
(inst->src[i].file != HW_REG ||
inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
inst->src[i].file != UNIFORM) {
/* No reads from MRF, and ATTR is already translated away */
assert(inst->src[i].file != MRF &&
inst->src[i].file != ATTR);
@ -1266,8 +1249,7 @@ vec4_instruction_scheduler::calculate_deps()
} else if (inst->dst.file == MRF) {
add_dep(last_mrf_write[inst->dst.nr], n);
last_mrf_write[inst->dst.nr] = n;
} else if (inst->dst.file == HW_REG &&
inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
} else if (inst->dst.file == FIXED_GRF) {
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
add_dep(last_accumulator_write, n);
@ -1316,17 +1298,13 @@ vec4_instruction_scheduler::calculate_deps()
if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(n, last_grf_write[inst->src[i].nr + j]);
} else if (inst->src[i].file == HW_REG &&
(inst->src[i].brw_reg::file ==
BRW_GENERAL_REGISTER_FILE)) {
} else if (inst->src[i].file == FIXED_GRF) {
add_dep(n, last_fixed_grf_write);
} else if (inst->src[i].is_accumulator()) {
add_dep(n, last_accumulator_write);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
inst->src[i].file != UNIFORM &&
(inst->src[i].file != HW_REG ||
inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF &&
inst->src[i].file != ATTR);
add_barrier_deps(n);
@ -1359,8 +1337,7 @@ vec4_instruction_scheduler::calculate_deps()
last_grf_write[inst->dst.nr + j] = n;
} else if (inst->dst.file == MRF) {
last_mrf_write[inst->dst.nr] = n;
} else if (inst->dst.file == HW_REG &&
inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
} else if (inst->dst.file == FIXED_GRF) {
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
last_accumulator_write = n;

8
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -733,18 +733,14 @@ backend_reg::is_negative_one() const
bool
backend_reg::is_null() const
{
return file == HW_REG &&
brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE &&
nr == BRW_ARF_NULL;
return file == ARF && nr == BRW_ARF_NULL;
}
bool
backend_reg::is_accumulator() const
{
return file == HW_REG &&
brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE &&
nr == BRW_ARF_ACCUMULATOR;
return file == ARF && nr == BRW_ARF_ACCUMULATOR;
}
bool

5
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -39,10 +39,11 @@
#define MAX_VGRF_SIZE 16
enum PACKED register_file {
VGRF,
ARF,
FIXED_GRF,
MRF,
IMM,
HW_REG, /* a struct brw_reg */
VGRF,
ATTR,
UNIFORM, /* prog_data->params[reg] */
BAD_FILE,

141
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -119,7 +119,7 @@ src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
src_reg::src_reg(struct brw_reg reg) :
backend_reg(reg)
{
this->file = HW_REG;
this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->reladdr = NULL;
}
@ -127,7 +127,7 @@ src_reg::src_reg(struct brw_reg reg) :
src_reg::src_reg(const dst_reg &reg) :
backend_reg(static_cast<struct brw_reg>(reg))
{
this->file = reg.file;
this->file = (enum register_file)reg.file;
this->reg_offset = reg.reg_offset;
this->reladdr = reg.reladdr;
this->swizzle = brw_swizzle_for_mask(reg.writemask);
@ -159,7 +159,7 @@ dst_reg::dst_reg(register_file file, int nr, const glsl_type *type,
{
init();
this->file = file;
this->file = (enum register_file)file;
this->nr = nr;
this->type = brw_type_for_base_type(type);
this->writemask = writemask;
@ -179,7 +179,7 @@ dst_reg::dst_reg(register_file file, int nr, brw_reg_type type,
dst_reg::dst_reg(struct brw_reg reg) :
backend_reg(reg)
{
this->file = HW_REG;
this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->reladdr = NULL;
}
@ -196,17 +196,10 @@ dst_reg::dst_reg(const src_reg &reg) :
bool
dst_reg::equals(const dst_reg &r) const
{
return (file == r.file &&
nr == r.nr &&
return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
type == r.type &&
negate == r.negate &&
abs == r.abs &&
writemask == r.writemask &&
(reladdr == r.reladdr ||
(reladdr && r.reladdr && reladdr->equals(*r.reladdr))) &&
(file != HW_REG ||
memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0));
(reladdr && r.reladdr && reladdr->equals(*r.reladdr))));
}
bool
@ -341,17 +334,9 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
bool
src_reg::equals(const src_reg &r) const
{
return (file == r.file &&
nr == r.nr &&
return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
type == r.type &&
negate == r.negate &&
abs == r.abs &&
swizzle == r.swizzle &&
!reladdr && !r.reladdr &&
(file != HW_REG ||
memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0) &&
(file != IMM || d == r.d));
!reladdr && !r.reladdr);
}
bool
@ -439,7 +424,9 @@ vec4_visitor::opt_reduce_swizzle()
bool progress = false;
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG ||
if (inst->dst.file == BAD_FILE ||
inst->dst.file == ARF ||
inst->dst.file == FIXED_GRF ||
inst->is_send_from_grf())
continue;
@ -914,7 +901,7 @@ vec4_visitor::opt_set_dependency_control()
int reg = inst->src[i].nr + inst->src[i].reg_offset;
if (inst->src[i].file == VGRF) {
last_grf_write[reg] = NULL;
} else if (inst->src[i].file == HW_REG) {
} else if (inst->src[i].file == FIXED_GRF) {
memset(last_grf_write, 0, sizeof(last_grf_write));
break;
}
@ -931,7 +918,7 @@ vec4_visitor::opt_set_dependency_control()
* against a previous one writing to its destination.
*/
int reg = inst->dst.nr + inst->dst.reg_offset;
if (inst->dst.file == VGRF) {
if (inst->dst.file == VGRF || inst->dst.file == FIXED_GRF) {
if (last_grf_write[reg] &&
!(inst->dst.writemask & grf_channels_written[reg])) {
last_grf_write[reg]->no_dd_clear = true;
@ -953,11 +940,6 @@ vec4_visitor::opt_set_dependency_control()
last_mrf_write[reg] = inst;
mrf_channels_written[reg] |= inst->dst.writemask;
} else if (inst->dst.nr == HW_REG) {
if (inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE)
memset(last_grf_write, 0, sizeof(last_grf_write));
if (inst->dst.brw_reg::file == BRW_MESSAGE_REGISTER_FILE)
memset(last_mrf_write, 0, sizeof(last_mrf_write));
}
}
}
@ -985,11 +967,8 @@ vec4_instruction::can_reswizzle(const struct brw_device_info *devinfo,
if (mlen > 0)
return false;
/* We can't use swizzles on the accumulator and that's really the only
* HW_REG we would care to reswizzle so just disallow them all.
*/
for (int i = 0; i < 3; i++) {
if (src[i].file == HW_REG)
if (src[i].is_accumulator())
return false;
}
@ -1381,32 +1360,29 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case VGRF:
fprintf(file, "vgrf%d.%d", inst->dst.nr, inst->dst.reg_offset);
break;
case FIXED_GRF:
fprintf(file, "g%d", inst->dst.nr);
break;
case MRF:
fprintf(file, "m%d", inst->dst.nr);
break;
case HW_REG:
if (inst->dst.brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (inst->dst.nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->dst.subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->dst.subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->dst.nr & 0xf,
inst->dst.subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->dst.nr & 0xf,
inst->dst.subnr);
break;
}
} else {
fprintf(file, "hw_reg%d", inst->dst.nr);
case ARF:
switch (inst->dst.nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->dst.subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->dst.subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
break;
}
if (inst->dst.subnr)
fprintf(file, "+%d", inst->dst.subnr);
@ -1444,6 +1420,9 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case VGRF:
fprintf(file, "vgrf%d", inst->src[i].nr);
break;
case FIXED_GRF:
fprintf(file, "g%d", inst->src[i].nr);
break;
case ATTR:
fprintf(file, "attr%d", inst->src[i].nr);
break;
@ -1473,29 +1452,23 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
break;
}
break;
case HW_REG:
if (inst->src[i].brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (inst->src[i].nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->src[i].subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->src[i].subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->src[i].nr & 0xf,
inst->src[i].subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf,
inst->src[i].subnr);
break;
}
} else {
fprintf(file, "hw_reg%d", inst->src[i].nr);
case ARF:
switch (inst->src[i].nr) {
case BRW_ARF_NULL:
fprintf(file, "null");
break;
case BRW_ARF_ADDRESS:
fprintf(file, "a0.%d", inst->src[i].subnr);
break;
case BRW_ARF_ACCUMULATOR:
fprintf(file, "acc%d", inst->src[i].subnr);
break;
case BRW_ARF_FLAG:
fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
break;
default:
fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
break;
}
if (inst->src[i].subnr)
fprintf(file, "+%d", inst->src[i].subnr);
@ -1812,7 +1785,8 @@ vec4_visitor::convert_to_hw_regs()
assert(!src.reladdr);
break;
case HW_REG:
case ARF:
case FIXED_GRF:
continue;
case BAD_FILE:
@ -1844,7 +1818,8 @@ vec4_visitor::convert_to_hw_regs()
reg.writemask = dst.writemask;
break;
case HW_REG:
case ARF:
case FIXED_GRF:
reg = dst;
break;

3
src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
View file

@ -143,7 +143,8 @@ vec4_visitor::opt_cse_local(bblock_t *block)
foreach_inst_in_block (vec4_instruction, inst, block) {
/* Skip some cases. */
if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
(inst->dst.file != HW_REG || inst->dst.is_null()))
((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
inst->dst.is_null()))
{
bool found = false;