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pvr: Fix for multiple attachments being assigned to the same tile buffer.

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When the first attachment is assigned to a tile buffer, the buffer
alloc mask was not been updated. This means when a second attachment
is added to the same tile buffer it will be assigned the same offset
as the first which will lead to incorrect behaviour.

Fixes for depq-vk:
dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.suballocation.attachment.4.568
dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.dedicated_allocation.attachment.4.568
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.suballocation.attachment.4.568
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.dedicated_allocation.attachment.4.568

Fixes: a7de9dae6b ("pvr: Add routine for filling out usc_mrt_setup from dynamic rendering state")

Signed-off-by: Nick Hamilton <nick.hamilton@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
(cherry picked from commit 96cfb1cb7f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40752>
This commit is contained in:
Nick Hamilton 2026-03-16 14:31:48 +00:00 • committed by Eric Engestrom
parent 5594cb90ac
commit b3197d6821
3 changed files with 11 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -5244,7 +5244,7 @@
"description": "pvr: Fix for multiple attachments being assigned to the same tile buffer.",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "a7de9dae6bd51a272d2462fef844f49e620803dd",
"notes": null

4
src/imagination/ci/bxs-4-64-fails.txt
View file

@ -34,10 +34,7 @@ dEQP-VK.pipeline.monolithic.stencil.no_stencil_att.dynamic_rendering.dynamic_ena
dEQP-VK.pipeline.monolithic.stencil.no_stencil_att.dynamic_rendering.dynamic_enable.d32_sfloat_s8_uint,Fail
dEQP-VK.pipeline.monolithic.stencil.no_stencil_att.dynamic_rendering.static_enable.d24_unorm_s8_uint,Fail
dEQP-VK.pipeline.monolithic.stencil.no_stencil_att.dynamic_rendering.static_enable.d32_sfloat_s8_uint,Fail
dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.dedicated_allocation.attachment.4.568,Fail
dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.suballocation.attachment.4.568,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.dedicated_allocation.attachment.4.568,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_multiview,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_multiview,Fail
@ -237,7 +234,6 @@ dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_multiview,
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_multiview,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99,Fail
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.suballocation.attachment.4.568,Fail
dEQP-VK.renderpasses.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_none_stencil_zero_testing_stencil,Fail
dEQP-VK.renderpasses.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_none_testing_depth,Fail
dEQP-VK.renderpasses.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint.depth_none_stencil_zero_testing_stencil,Fail

10
src/imagination/vulkan/pvr_arch_mrt.c
View file

@ -169,6 +169,16 @@ static VkResult pvr_alloc_mrt(const struct pvr_device_info *dev_info,
sizeof(alloc->tile_buffers[0U]) *
(resource->mem.tile_buffer + 1U - alloc->tile_buffers_count));
alloc->tile_buffers_count = resource->mem.tile_buffer + 1U;
/* Need to add the resource to the new tile buffer */
struct pvr_mrt_alloc_mask *tib_alloc =
&alloc->tile_buffers[resource->mem.tile_buffer];
ASSERTED const int32_t tile_buffer_offset =
pvr_mrt_alloc_from_buffer(dev_info,
tib_alloc,
pixel_size);
assert(tile_buffer_offset == 0);
}
/* The hardware makes the bit depth of the on-chip storage and memory