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radeonsi/test_image_copy: separate printing pipe_resource into a function
also print texture targets that are going to be tested Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16215>
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1 changed files with 55 additions and 41 deletions
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@ -28,6 +28,7 @@
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#include "si_pipe.h"
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#include "util/rand_xor.h"
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#include "util/u_surface.h"
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#include "amd/addrlib/inc/addrtypes.h"
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static uint64_t seed_xorshift128plus[2];
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@ -118,41 +119,6 @@ static enum pipe_format choose_format()
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return formats[rand() % ARRAY_SIZE(formats)];
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}
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static const char *array_mode_to_string(struct si_screen *sscreen, struct radeon_surf *surf)
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{
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if (sscreen->info.chip_class >= GFX9) {
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switch (surf->u.gfx9.swizzle_mode) {
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case 0:
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return " LINEAR";
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case 21:
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return " 4KB_S_X";
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case 22:
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return " 4KB_D_X";
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case 25:
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return "64KB_S_X";
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case 26:
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return "64KB_D_X";
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case 27:
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return "64KB_R_X";
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default:
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printf("Unhandled swizzle mode = %u\n", surf->u.gfx9.swizzle_mode);
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return " UNKNOWN";
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}
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} else {
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switch (surf->u.legacy.level[0].mode) {
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case RADEON_SURF_MODE_LINEAR_ALIGNED:
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return "LINEAR_ALIGNED";
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case RADEON_SURF_MODE_1D:
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return "1D_TILED_THIN1";
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case RADEON_SURF_MODE_2D:
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return "2D_TILED_THIN1";
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default:
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assert(0);
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return " UNKNOWN";
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}
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}
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}
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#define MAX_ALLOC_SIZE (128 * 1024 * 1024)
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static void set_random_image_attrs(struct pipe_resource *templ)
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@ -181,6 +147,55 @@ static void set_random_image_attrs(struct pipe_resource *templ)
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templ->width0 = align(templ->width0, 2);
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}
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static void print_image_attrs(struct si_screen *sscreen, struct si_texture *tex)
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{
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const char *mode;
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if (sscreen->info.chip_class >= GFX9) {
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static const char *modes[32] = {
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[ADDR_SW_LINEAR] = "LINEAR",
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[ADDR_SW_4KB_S_X] = "4KB_S_X",
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[ADDR_SW_4KB_D_X] = "4KB_D_X",
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[ADDR_SW_64KB_Z_X] = "64KB_Z_X",
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[ADDR_SW_64KB_S_X] = "64KB_S_X",
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[ADDR_SW_64KB_D_X] = "64KB_D_X",
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[ADDR_SW_64KB_R_X] = "64KB_R_X",
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};
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mode = modes[tex->surface.u.gfx9.swizzle_mode];
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} else {
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static const char *modes[32] = {
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[RADEON_SURF_MODE_LINEAR_ALIGNED] = "LINEAR",
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[RADEON_SURF_MODE_1D] = "1D_TILED",
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[RADEON_SURF_MODE_2D] = "2D_TILED",
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};
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mode = modes[tex->surface.u.legacy.level[0].mode];
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}
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if (!mode)
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mode = "UNKNOWN";
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static const char *targets[PIPE_MAX_TEXTURE_TYPES] = {
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[PIPE_TEXTURE_1D] = "1D",
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[PIPE_TEXTURE_2D] = "2D",
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[PIPE_TEXTURE_3D] = "3D",
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[PIPE_TEXTURE_RECT] = "RECT",
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[PIPE_TEXTURE_1D_ARRAY] = "1D_ARRAY",
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[PIPE_TEXTURE_2D_ARRAY] = "2D_ARRAY",
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};
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char size[64];
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if (tex->buffer.b.b.target == PIPE_TEXTURE_1D)
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snprintf(size, sizeof(size), "%u", tex->buffer.b.b.width0);
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else if (tex->buffer.b.b.target == PIPE_TEXTURE_2D ||
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tex->buffer.b.b.target == PIPE_TEXTURE_RECT)
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snprintf(size, sizeof(size), "%ux%u", tex->buffer.b.b.width0, tex->buffer.b.b.height0);
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else
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snprintf(size, sizeof(size), "%ux%ux%u", tex->buffer.b.b.width0, tex->buffer.b.b.height0,
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util_num_layers(&tex->buffer.b.b, 0));
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printf("%8s, %14s, %8s", targets[tex->buffer.b.b.target], size, mode);
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}
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void si_test_image_copy_region(struct si_screen *sscreen)
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{
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struct pipe_screen *screen = &sscreen->b;
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@ -228,12 +243,11 @@ void si_test_image_copy_region(struct si_screen *sscreen)
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alloc_cpu_texture(&src_cpu, &tsrc);
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alloc_cpu_texture(&dst_cpu, &tdst);
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printf("%4u: dst = (%5u x %5u x %u, %s), "
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" src = (%5u x %5u x %u, %s), format = %s, ",
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i, tdst.width0, tdst.height0, tdst.array_size,
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array_mode_to_string(sscreen, &sdst->surface), tsrc.width0, tsrc.height0,
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tsrc.array_size, array_mode_to_string(sscreen, &ssrc->surface),
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util_format_description(tsrc.format)->name);
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printf("%4u: dst = (", i);
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print_image_attrs(sscreen, sdst);
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printf("), src = (");
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print_image_attrs(sscreen, ssrc);
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printf("), format = %17s, ", util_format_description(tsrc.format)->short_name);
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fflush(stdout);
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/* set src pixels */
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