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pan/bi: Eliminate writemasks in the IR
Since the hardware doesn't support them, they're a burden to deal with, so let's ensure we never get to a place where we would need to at all. Disables COMBINE lowering for now. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
1622478fbd
commit
b2c6cf2b6d
10 changed files with 100 additions and 227 deletions
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@ -29,7 +29,7 @@ bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max)
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{
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/* live_in[s] = GEN[s] + (live_out[s] - KILL[s]) */
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pan_liveness_kill(live, ins->dest, max, ins->writemask);
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pan_liveness_kill(live, ins->dest, max, bi_writemask(ins));
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bi_foreach_src(ins, src) {
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unsigned node = ins->src[src];
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@ -38,7 +38,7 @@
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* component c is `x`, we are accessing v.x, and each of the succeeding
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* components y, z... up to the last component of the vector are accessed
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* sequentially, then we may perform the same rewrite. If this is not the case,
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* rewriting would require a swizzle or writemask (TODO), so we fallback on a
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* rewriting would require more complex vector features, so we fallback on a
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* move.
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*
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* Otherwise is the source is not SSA, we also fallback on a move. We could
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@ -46,18 +46,15 @@
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*/
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static void
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bi_insert_combine_mov(bi_context *ctx, bi_instruction *parent, unsigned comp, unsigned R)
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bi_combine_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp, unsigned R)
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{
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unsigned bits = nir_alu_type_get_type_size(parent->dest_type);
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unsigned bytes = bits / 8;
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bi_instruction move = {
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.type = BI_MOV,
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.dest = R,
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.dest_type = parent->dest_type,
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.writemask = ((1 << bytes) - 1) << (bytes * comp),
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.dest_type = nir_type_uint32,
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.dest_offset = comp,
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.src = { parent->src[comp] },
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.src_types = { parent->dest_type },
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.src_types = { nir_type_uint32 },
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.swizzle = { { parent->swizzle[comp][0] } }
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};
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@ -70,12 +67,11 @@ bi_insert_combine_mov(bi_context *ctx, bi_instruction *parent, unsigned comp, un
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* bookkeeping. */
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static bi_instruction *
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bi_get_parent(bi_context *ctx, unsigned idx, unsigned mask)
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bi_get_parent(bi_context *ctx, unsigned idx)
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{
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bi_foreach_instr_global(ctx, ins) {
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if (ins->dest == idx)
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if ((ins->writemask & mask) == mask)
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return ins;
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return ins;
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}
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return NULL;
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@ -103,76 +99,31 @@ bi_rewrite_uses(bi_context *ctx,
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}
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}
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/* Shifts the writemask of an instruction by a specified byte count,
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* rotating the sources to compensate. Returns true if successful, and
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* returns false if not (nondestructive in this case). */
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static bool
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bi_shift_mask(bi_instruction *ins, unsigned shift)
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{
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/* No op and handles the funny cases */
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if (!shift)
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return true;
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unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
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unsigned bytes = sz / 8;
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/* If things are misaligned, we bail. Check if shift % bytes is
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* nonzero. Note bytes is a power-of-two. */
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if (shift & (bytes - 1))
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return false;
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/* Ensure there are no funny types */
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bi_foreach_src(ins, s) {
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if (ins->src[s] && nir_alu_type_get_type_size(ins->src_types[s]) != sz)
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return false;
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}
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/* Shift swizzle so old i'th component is accessed by new (i + j)'th
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* component where j is component shift */
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unsigned component_shift = shift / bytes;
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/* Sanity check to avoid memory corruption */
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if (component_shift >= sizeof(ins->swizzle[0]))
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return false;
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/* Otherwise, shift is divisible by bytes, and all relevant src types
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* are the same size as the dest type. */
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ins->writemask <<= shift;
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bi_foreach_src(ins, s) {
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if (!ins->src[s]) continue;
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size_t overlap = sizeof(ins->swizzle[s]) - component_shift;
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memmove(ins->swizzle[s] + component_shift, ins->swizzle[s], overlap);
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}
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return true;
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}
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/* Checks if we have a nicely aligned vector prefix */
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static bool
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bi_is_aligned_vec(bi_instruction *combine, unsigned s, bi_instruction *parent,
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bi_is_aligned_vec32(bi_instruction *combine, unsigned s, bi_instruction *io,
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unsigned *count)
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{
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/* We only support prefixes */
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if (s != 0)
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return false;
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/* Is it a contiguous write? */
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unsigned writes = util_bitcount(parent->writemask);
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if (parent->writemask != ((1 << writes) - 1))
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if (!(bi_class_props[io->type] & BI_VECTOR))
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return false;
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/* Okay - how many components? */
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unsigned bytes = nir_alu_type_get_type_size(parent->dest_type) / 8;
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unsigned components = writes / bytes;
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if (nir_alu_type_get_type_size(combine->dest_type) != 32)
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return false;
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if (nir_alu_type_get_type_size(io->dest_type) != 32)
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return false;
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unsigned components = io->vector_channels;
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/* Are we contiguous like that? */
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for (unsigned i = 0; i < components; ++i) {
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if (combine->src[i] != parent->dest)
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if (combine->src[i] != io->dest)
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return false;
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if (combine->swizzle[i][0] != i)
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@ -184,6 +135,7 @@ bi_is_aligned_vec(bi_instruction *combine, unsigned s, bi_instruction *parent,
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return true;
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}
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#if 0
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/* Tries to lower a given source of a combine to an appropriate rewrite,
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* returning true if successful, and false with no changes otherwise. */
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@ -210,7 +162,7 @@ bi_lower_combine_src(bi_context *ctx, bi_instruction *ins, unsigned s, unsigned
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unsigned pbytes = nir_alu_type_get_type_size(parent->dest_type) / 8;
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if (pbytes != bytes) return false;
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bool scalar = (parent->writemask == ((1 << bytes) - 1));
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bool scalar = parent->vector_channels != 0;
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if (!(scalar || bi_is_aligned_vec(ins, s, parent, vec_count))) return false;
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if (!bi_shift_mask(parent, bytes * s)) return false;
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@ -218,6 +170,7 @@ bi_lower_combine_src(bi_context *ctx, bi_instruction *ins, unsigned s, unsigned
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parent->dest = R;
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return true;
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}
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#endif
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void
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bi_lower_combine(bi_context *ctx, bi_block *block)
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@ -225,9 +178,6 @@ bi_lower_combine(bi_context *ctx, bi_block *block)
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bi_foreach_instr_in_block_safe(block, ins) {
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if (ins->type != BI_COMBINE) continue;
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/* The vector itself can't be shifted */
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assert(ins->writemask & 0x1);
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unsigned R = bi_make_temp_reg(ctx);
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bi_foreach_src(ins, s) {
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@ -235,6 +185,7 @@ bi_lower_combine(bi_context *ctx, bi_block *block)
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if (!ins->src[s])
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continue;
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#if 0
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unsigned vec_count = 0;
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if (bi_lower_combine_src(ctx, ins, s, R, &vec_count)) {
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@ -244,6 +195,8 @@ bi_lower_combine(bi_context *ctx, bi_block *block)
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} else {
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bi_insert_combine_mov(ctx, ins, s, R);
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}
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#endif
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bi_combine_mov32(ctx, ins, s, R);
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}
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@ -968,10 +968,6 @@ bi_pack_add_ld_vary(bi_clause *clause, bi_instruction *ins, struct bi_registers
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BIFROST_ADD_OP_LD_VAR_32 :
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BIFROST_ADD_OP_LD_VAR_16;
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unsigned cmask = bi_from_bytemask(ins->writemask, size / 8);
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unsigned channels = util_bitcount(cmask);
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assert(cmask == ((1 << channels) - 1));
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unsigned packed_addr = 0;
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if (ins->src[0] & BIR_INDEX_CONSTANT) {
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@ -987,6 +983,7 @@ bi_pack_add_ld_vary(bi_clause *clause, bi_instruction *ins, struct bi_registers
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assert(ins->dest & BIR_INDEX_REGISTER);
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clause->data_register = ins->dest & ~BIR_INDEX_REGISTER;
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unsigned channels = ins->vector_channels;
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assert(channels >= 1 && channels <= 4);
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struct bifrost_ld_var pack = {
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@ -1076,7 +1073,7 @@ bi_pack_add_addmin(bi_instruction *ins, struct bi_registers *regs)
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static unsigned
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bi_pack_add_ld_ubo(bi_clause *clause, bi_instruction *ins, struct bi_registers *regs)
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{
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unsigned components = bi_load32_components(ins);
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assert(ins->vector_channels >= 1 && ins->vector_channels <= 4);
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const unsigned ops[4] = {
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BIFROST_ADD_OP_LD_UBO_1,
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@ -1086,7 +1083,7 @@ bi_pack_add_ld_ubo(bi_clause *clause, bi_instruction *ins, struct bi_registers *
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};
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bi_write_data_register(clause, ins);
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return bi_pack_add_2src(ins, regs, ops[components - 1]);
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return bi_pack_add_2src(ins, regs, ops[ins->vector_channels - 1]);
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}
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static enum bifrost_ldst_type
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@ -1119,11 +1116,13 @@ bi_pack_add_ld_var_addr(bi_clause *clause, bi_instruction *ins, struct bi_regist
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static unsigned
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bi_pack_add_ld_attr(bi_clause *clause, bi_instruction *ins, struct bi_registers *regs)
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{
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assert(ins->vector_channels >= 0 && ins->vector_channels <= 4);
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struct bifrost_ld_attr pack = {
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.src0 = bi_get_src(ins, regs, 1, false),
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.src1 = bi_get_src(ins, regs, 2, false),
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.location = bi_get_immediate(ins, 0),
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.channels = MALI_POSITIVE(bi_load32_components(ins)),
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.channels = MALI_POSITIVE(ins->vector_channels),
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.type = bi_pack_ldst_type(ins->dest_type),
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.op = BIFROST_ADD_OP_LD_ATTR
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};
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@ -1135,13 +1134,13 @@ bi_pack_add_ld_attr(bi_clause *clause, bi_instruction *ins, struct bi_registers
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static unsigned
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bi_pack_add_st_vary(bi_clause *clause, bi_instruction *ins, struct bi_registers *regs)
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{
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assert(ins->store_channels >= 1 && ins->store_channels <= 4);
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assert(ins->vector_channels >= 1 && ins->vector_channels <= 4);
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struct bifrost_st_vary pack = {
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.src0 = bi_get_src(ins, regs, 1, false),
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.src1 = bi_get_src(ins, regs, 2, false),
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.src2 = bi_get_src(ins, regs, 3, false),
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.channels = MALI_POSITIVE(ins->store_channels),
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.channels = MALI_POSITIVE(ins->vector_channels),
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.op = BIFROST_ADD_OP_ST_VAR
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};
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@ -244,12 +244,9 @@ bi_print_alu_type(nir_alu_type t, FILE *fp)
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static void
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bi_print_swizzle(bi_instruction *ins, unsigned src, FILE *fp)
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{
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unsigned size = nir_alu_type_get_type_size(ins->dest_type);
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unsigned count = (size == 64) ? 1 : (32 / size);
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fprintf(fp, ".");
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for (unsigned u = 0; u < count; ++u) {
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for (unsigned u = 0; u < bi_get_component_count(ins, src); ++u) {
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assert(ins->swizzle[src][u] < 4);
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fputc("xyzw"[ins->swizzle[src][u]], fp);
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}
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@ -348,27 +345,6 @@ bi_print_branch(struct bi_branch *branch, FILE *fp)
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fprintf(fp, ".%s", bi_cond_name(branch->cond));
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}
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static void
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bi_print_writemask(bi_instruction *ins, FILE *fp)
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{
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unsigned bits_per_comp = nir_alu_type_get_type_size(ins->dest_type);
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assert(bits_per_comp);
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unsigned bytes_per_comp = bits_per_comp / 8;
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unsigned comps = 16 / bytes_per_comp;
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unsigned smask = (1 << bytes_per_comp) - 1;
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fprintf(fp, ".");
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for (unsigned i = 0; i < comps; ++i) {
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unsigned masked = (ins->writemask >> (i * bytes_per_comp)) & smask;
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if (!masked)
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continue;
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assert(masked == smask);
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assert(i < 4);
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fputc("xyzw"[i], fp);
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}
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}
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void
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bi_print_instruction(bi_instruction *ins, FILE *fp)
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{
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@ -404,11 +380,12 @@ bi_print_instruction(bi_instruction *ins, FILE *fp)
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fprintf(fp, ".%s", bi_cond_name(ins->csel_cond));
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else if (ins->type == BI_BLEND)
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fprintf(fp, ".loc%u", ins->blend_location);
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else if (ins->type == BI_STORE || ins->type == BI_STORE_VAR)
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fprintf(fp, ".v%u", ins->store_channels);
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else if (ins->type == BI_TEX)
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fprintf(fp, ".%s", bi_tex_op_name(ins->op.texture));
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if (ins->vector_channels)
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fprintf(fp, ".v%u", ins->vector_channels);
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if (ins->dest)
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bi_print_alu_type(ins->dest_type, fp);
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@ -422,8 +399,8 @@ bi_print_instruction(bi_instruction *ins, FILE *fp)
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bool succ = bi_print_dest_index(fp, ins, ins->dest);
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assert(succ);
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if (ins->dest)
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bi_print_writemask(ins, fp);
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if (ins->dest_offset)
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fprintf(fp, "+%u", ins->dest_offset);
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fprintf(fp, ", ");
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@ -25,6 +25,7 @@
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*/
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#include "compiler.h"
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#include "bi_print.h"
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#include "panfrost/util/lcra.h"
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#include "util/u_memory.h"
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@ -44,7 +45,7 @@ bi_compute_interference(bi_context *ctx, struct lcra_state *l)
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if (ins->dest && (ins->dest < l->node_count)) {
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for (unsigned i = 1; i < l->node_count; ++i) {
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if (live[i])
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lcra_add_node_interference(l, ins->dest, ins->writemask, i, live[i]);
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lcra_add_node_interference(l, ins->dest, bi_writemask(ins), i, live[i]);
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}
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}
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@ -101,10 +102,10 @@ bi_reg_from_index(struct lcra_state *l, unsigned index, unsigned offset)
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if (solution < 0)
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return index;
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solution += offset;
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assert((solution & 0x3) == 0);
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unsigned reg = solution / 4;
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reg += offset;
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return BIR_INDEX_REGISTER | reg;
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}
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@ -121,19 +122,10 @@ bi_adjust_src_ra(bi_instruction *ins, struct lcra_state *l, unsigned src)
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/* TODO: Do we do anything here? */
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} else {
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/* Use the swizzle as component select */
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nir_alu_type T = ins->src_types[src];
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unsigned size = nir_alu_type_get_type_size(T);
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assert(size <= 32); /* TODO: 64-bit */
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unsigned comps_per_reg = 32 / size;
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unsigned components = bi_get_component_count(ins, src);
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for (unsigned i = 0; i < components; ++i) {
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/* If we're not writing the component, who cares? */
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if (!bi_writes_component(ins, i))
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continue;
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unsigned off = ins->swizzle[src][i] / comps_per_reg;
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off *= 4; /* 32-bit registers */
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unsigned off = ins->swizzle[src][i] / components;
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/* We can't cross register boundaries in a swizzle */
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if (i == 0)
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@ -141,7 +133,7 @@ bi_adjust_src_ra(bi_instruction *ins, struct lcra_state *l, unsigned src)
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else
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assert(off == offset);
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ins->swizzle[src][i] %= comps_per_reg;
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ins->swizzle[src][i] %= components;
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}
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}
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@ -154,25 +146,7 @@ bi_adjust_dest_ra(bi_instruction *ins, struct lcra_state *l)
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if (ins->dest >= l->node_count)
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return;
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bool vector = (bi_class_props[ins->type] & BI_VECTOR);
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unsigned offset = 0;
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if (!vector) {
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/* Look at the writemask to get an offset, specifically the
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* trailing zeros */
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unsigned tz = __builtin_ctz(ins->writemask);
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/* Recall writemask is one bit per byte, so tz is in eytes */
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unsigned regs = tz / 4;
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offset = regs * 4;
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|
||||
/* Adjust writemask to compensate */
|
||||
ins->writemask >>= offset;
|
||||
}
|
||||
|
||||
ins->dest = bi_reg_from_index(l, ins->dest, offset);
|
||||
|
||||
ins->dest = bi_reg_from_index(l, ins->dest, ins->dest_offset);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@ bi_emit_fexp2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.op = { .mscale = true },
|
||||
.dest = bi_make_temp(ctx),
|
||||
.dest_type = nir_type_float32,
|
||||
.writemask = 0xF,
|
||||
.src = {
|
||||
bir_src_index(&instr->src[0].src),
|
||||
BIR_INDEX_CONSTANT | 0,
|
||||
|
|
@ -68,7 +67,6 @@ bi_emit_fexp2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.type = BI_CONVERT,
|
||||
.dest = bi_make_temp(ctx),
|
||||
.dest_type = nir_type_int32,
|
||||
.writemask = 0xF,
|
||||
.src = { mscale.dest },
|
||||
.src_types = { nir_type_float32 },
|
||||
.roundmode = BIFROST_RTE
|
||||
|
|
@ -81,7 +79,6 @@ bi_emit_fexp2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.op = { .special = BI_SPECIAL_EXP2_LOW },
|
||||
.dest = bir_dest_index(&instr->dest.dest),
|
||||
.dest_type = nir_type_float32,
|
||||
.writemask = 0xF,
|
||||
.src = { f2i.dest, mscale.src[0] },
|
||||
.src_types = { nir_type_int32, nir_type_float32 },
|
||||
};
|
||||
|
|
@ -102,7 +99,6 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.op = { .frexp = BI_FREXPE_LOG },
|
||||
.dest = bi_make_temp(ctx),
|
||||
.dest_type = nir_type_int32,
|
||||
.writemask = 0xF,
|
||||
.src = { bir_src_index(&instr->src[0].src) },
|
||||
.src_types = { nir_type_float32 }
|
||||
};
|
||||
|
|
@ -112,7 +108,6 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.type = BI_CONVERT,
|
||||
.dest = bi_make_temp(ctx),
|
||||
.dest_type = nir_type_float32,
|
||||
.writemask = 0xF,
|
||||
.src = { frexpe.dest },
|
||||
.src_types = { nir_type_int32 },
|
||||
.roundmode = BIFROST_RTZ
|
||||
|
|
@ -124,7 +119,6 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.op = { .reduce = BI_REDUCE_ADD_FREXPM },
|
||||
.dest = bi_make_temp(ctx),
|
||||
.dest_type = nir_type_float32,
|
||||
.writemask = 0xF,
|
||||
.src = {
|
||||
BIR_INDEX_CONSTANT,
|
||||
bir_src_index(&instr->src[0].src),
|
||||
|
|
@ -141,7 +135,6 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.op = { .table = BI_TABLE_LOG2_U_OVER_U_1_LOW },
|
||||
.dest = bi_make_temp(ctx),
|
||||
.dest_type = nir_type_float32,
|
||||
.writemask = 0xF,
|
||||
.src = { bir_src_index(&instr->src[0].src) },
|
||||
.src_types = { nir_type_float32 },
|
||||
};
|
||||
|
|
@ -151,7 +144,6 @@ bi_emit_flog2_new(bi_context *ctx, nir_alu_instr *instr)
|
|||
.type = BI_FMA,
|
||||
.dest = bir_dest_index(&instr->dest.dest),
|
||||
.dest_type = nir_type_float32,
|
||||
.writemask = 0xF,
|
||||
.src = {
|
||||
help.dest,
|
||||
x_minus_1.dest,
|
||||
|
|
|
|||
|
|
@ -59,19 +59,12 @@ emit_jump(bi_context *ctx, nir_jump_instr *instr)
|
|||
pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
|
||||
}
|
||||
|
||||
/* Gets a bytemask for a complete vecN write */
|
||||
static unsigned
|
||||
bi_mask_for_channels_32(unsigned i)
|
||||
{
|
||||
return (1 << (4 * i)) - 1;
|
||||
}
|
||||
|
||||
static bi_instruction
|
||||
bi_load(enum bi_class T, nir_intrinsic_instr *instr)
|
||||
{
|
||||
bi_instruction load = {
|
||||
.type = T,
|
||||
.writemask = bi_mask_for_channels_32(instr->num_components),
|
||||
.vector_channels = instr->num_components,
|
||||
.src = { BIR_INDEX_CONSTANT },
|
||||
.src_types = { nir_type_uint32 },
|
||||
.constant = { .u64 = nir_intrinsic_base(instr) },
|
||||
|
|
@ -135,7 +128,6 @@ bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
|
|||
},
|
||||
.dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
|
||||
.dest_type = nir_type_uint32,
|
||||
.writemask = 0xF
|
||||
};
|
||||
|
||||
bi_emit(ctx, ins);
|
||||
|
|
@ -160,7 +152,7 @@ bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
|
|||
},
|
||||
.dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
|
||||
.dest_type = nir_type_uint32,
|
||||
.writemask = 0xF
|
||||
.vector_channels = 4
|
||||
};
|
||||
|
||||
assert(blend.blend_location < 8);
|
||||
|
|
@ -190,7 +182,7 @@ bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
|
|||
bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
|
||||
address.dest = bi_make_temp(ctx);
|
||||
address.dest_type = nir_type_uint32;
|
||||
address.writemask = (1 << 12) - 1;
|
||||
address.vector_channels = 3;
|
||||
|
||||
unsigned nr = nir_intrinsic_src_components(instr, 0);
|
||||
assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
|
||||
|
|
@ -209,7 +201,7 @@ bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
|
|||
{ 0 },
|
||||
{ 0 }, { 1 }, { 2}
|
||||
},
|
||||
.store_channels = nr,
|
||||
.vector_channels = nr,
|
||||
};
|
||||
|
||||
for (unsigned i = 0; i < nr; ++i)
|
||||
|
|
@ -253,7 +245,7 @@ bi_emit_sysval(bi_context *ctx, nir_instr *instr,
|
|||
|
||||
bi_instruction load = {
|
||||
.type = BI_LOAD_UNIFORM,
|
||||
.writemask = (1 << (nr_components * 4)) - 1,
|
||||
.vector_channels = nr_components,
|
||||
.src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
|
||||
.src_types = { nir_type_uint32, nir_type_uint32 },
|
||||
.constant = { (uniform * 16) + offset },
|
||||
|
|
@ -327,7 +319,6 @@ emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
|
|||
.type = BI_MOV,
|
||||
.dest = bir_ssa_index(&instr->def),
|
||||
.dest_type = instr->def.bit_size | nir_type_uint,
|
||||
.writemask = (1 << (instr->def.bit_size / 8)) - 1,
|
||||
.src = {
|
||||
BIR_INDEX_CONSTANT
|
||||
},
|
||||
|
|
@ -476,7 +467,7 @@ bi_cond_for_nir(nir_op op, bool soft)
|
|||
|
||||
static void
|
||||
bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
|
||||
unsigned *constants_left, unsigned *constant_shift)
|
||||
unsigned *constants_left, unsigned *constant_shift, unsigned comps)
|
||||
{
|
||||
unsigned bits = nir_src_bit_size(instr->src[i].src);
|
||||
unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
|
||||
|
|
@ -506,13 +497,19 @@ bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
|
|||
|
||||
alu->src[to] = bir_src_index(&instr->src[i].src);
|
||||
|
||||
/* We assert scalarization above */
|
||||
alu->swizzle[to][0] = instr->src[i].swizzle[0];
|
||||
/* Copy swizzle for all vectored components, replicating last component
|
||||
* to fill undersized */
|
||||
|
||||
unsigned vec = alu->type == BI_COMBINE ? 1 :
|
||||
MAX2(1, 32 / dest_bits);
|
||||
|
||||
for (unsigned j = 0; j < vec; ++j)
|
||||
alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
|
||||
}
|
||||
|
||||
static void
|
||||
bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
|
||||
unsigned *constants_left, unsigned *constant_shift)
|
||||
unsigned *constants_left, unsigned *constant_shift, unsigned comps)
|
||||
{
|
||||
/* Bail for vector weirdness */
|
||||
if (cond.swizzle[0] != 0)
|
||||
|
|
@ -537,8 +534,8 @@ bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
|
|||
|
||||
/* We found one, let's fuse it in */
|
||||
csel->csel_cond = bcond;
|
||||
bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
|
||||
bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift);
|
||||
bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift, comps);
|
||||
bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift, comps);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -567,22 +564,14 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
|
|||
/* TODO: Implement lowering of special functions for older Bifrost */
|
||||
assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
|
||||
|
||||
if (instr->dest.dest.is_ssa) {
|
||||
/* Construct a writemask */
|
||||
unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
|
||||
unsigned comps = instr->dest.dest.ssa.num_components;
|
||||
unsigned comps = nir_dest_num_components(instr->dest.dest);
|
||||
|
||||
if (alu.type != BI_COMBINE)
|
||||
assert(comps == 1);
|
||||
if (alu.type != BI_COMBINE)
|
||||
assert(comps <= MAX2(1, 32 / comps));
|
||||
|
||||
unsigned bits = bits_per_comp * comps;
|
||||
unsigned bytes = bits / 8;
|
||||
alu.writemask = (1 << bytes) - 1;
|
||||
} else {
|
||||
unsigned comp_mask = instr->dest.write_mask;
|
||||
|
||||
alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
|
||||
comp_mask);
|
||||
if (!instr->dest.dest.is_ssa) {
|
||||
for (unsigned i = 0; i < comps; ++i)
|
||||
assert(instr->dest.write_mask);
|
||||
}
|
||||
|
||||
/* We inline constants as we go. This tracks how many constants have
|
||||
|
|
@ -607,7 +596,7 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
|
|||
if (i && alu.type == BI_CSEL)
|
||||
f++;
|
||||
|
||||
bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift);
|
||||
bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift, comps);
|
||||
}
|
||||
|
||||
/* Op-specific fixup */
|
||||
|
|
@ -676,7 +665,7 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
|
|||
alu.src_types[1] = alu.src_types[0];
|
||||
|
||||
bi_fuse_csel_cond(&alu, instr->src[0],
|
||||
&constants_left, &constant_shift);
|
||||
&constants_left, &constant_shift, comps);
|
||||
}
|
||||
|
||||
bi_emit(ctx, alu);
|
||||
|
|
@ -698,8 +687,7 @@ emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
|
|||
.dest = bir_dest_index(&instr->dest),
|
||||
.dest_type = instr->dest_type,
|
||||
.src_types = { nir_type_float32, nir_type_float32 },
|
||||
.writemask = instr->dest_type == nir_type_float32 ?
|
||||
0xFFFF : 0xFF,
|
||||
.vector_channels = 4
|
||||
};
|
||||
|
||||
for (unsigned i = 0; i < instr->num_srcs; ++i) {
|
||||
|
|
|
|||
|
|
@ -93,28 +93,17 @@ bi_from_bytemask(uint16_t bytemask, unsigned bytes)
|
|||
}
|
||||
|
||||
unsigned
|
||||
bi_get_component_count(bi_instruction *ins, unsigned src)
|
||||
bi_get_component_count(bi_instruction *ins, signed src)
|
||||
{
|
||||
if (bi_class_props[ins->type] & BI_VECTOR) {
|
||||
return (src == 0) ? 4 : 1;
|
||||
assert(ins->vector_channels);
|
||||
return (src <= 0) ? ins->vector_channels : 1;
|
||||
} else {
|
||||
/* Stores imply VECTOR */
|
||||
assert(ins->dest_type);
|
||||
unsigned bytes = nir_alu_type_get_type_size(ins->dest_type);
|
||||
return 32 / bytes;
|
||||
unsigned bytes = nir_alu_type_get_type_size(src < 0 ? ins->dest_type : ins->src_types[src]);
|
||||
return MAX2(32 / bytes, 1);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned
|
||||
bi_load32_components(bi_instruction *ins)
|
||||
{
|
||||
unsigned mask = bi_from_bytemask(ins->writemask, 4);
|
||||
unsigned count = util_bitcount(mask);
|
||||
assert(mask == ((1 << count) - 1));
|
||||
assert(count >= 1 && count <= 4);
|
||||
return count;
|
||||
}
|
||||
|
||||
uint16_t
|
||||
bi_bytemask_of_read_components(bi_instruction *ins, unsigned node)
|
||||
{
|
||||
|
|
@ -157,11 +146,18 @@ bi_get_immediate(bi_instruction *ins, unsigned index)
|
|||
bool
|
||||
bi_writes_component(bi_instruction *ins, unsigned comp)
|
||||
{
|
||||
/* TODO: Do we want something less coarse? */
|
||||
if (bi_class_props[ins->type] & BI_VECTOR)
|
||||
return true;
|
||||
return comp < bi_get_component_count(ins, -1);
|
||||
}
|
||||
|
||||
unsigned
|
||||
bi_writemask(bi_instruction *ins)
|
||||
{
|
||||
nir_alu_type T = ins->dest_type;
|
||||
unsigned size = nir_alu_type_get_type_size(T);
|
||||
return ins->writemask & (0xF << (comp * (size / 8)));
|
||||
unsigned bytes_per_comp = size / 8;
|
||||
unsigned components = bi_get_component_count(ins, -1);
|
||||
unsigned bytes = bytes_per_comp * components;
|
||||
unsigned mask = (1 << bytes) - 1;
|
||||
unsigned shift = ins->dest_offset * 4; /* 32-bit words */
|
||||
return (mask << shift);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -114,8 +114,7 @@ extern unsigned bi_class_props[BI_NUM_CLASSES];
|
|||
* the end of a clause. Implies ADD */
|
||||
#define BI_SCHED_HI_LATENCY (1 << 7)
|
||||
|
||||
/* Intrinsic is vectorized and should read 4 components in the first source
|
||||
* regardless of writemask */
|
||||
/* Intrinsic is vectorized and acts with `vector_channels` components */
|
||||
#define BI_VECTOR (1 << 8)
|
||||
|
||||
/* Use a data register for src0/dest respectively, bypassing the usual
|
||||
|
|
@ -229,6 +228,10 @@ typedef struct {
|
|||
unsigned dest;
|
||||
unsigned src[BIR_SRC_COUNT];
|
||||
|
||||
/* 32-bit word offset for destination, added to the register number in
|
||||
* RA when lowering combines */
|
||||
unsigned dest_offset;
|
||||
|
||||
/* If one of the sources has BIR_INDEX_CONSTANT */
|
||||
union {
|
||||
uint64_t u64;
|
||||
|
|
@ -246,14 +249,6 @@ typedef struct {
|
|||
/* Round mode (requires BI_ROUNDMODE) */
|
||||
enum bifrost_roundmode roundmode;
|
||||
|
||||
/* Writemask (bit for each affected byte). This is quite restricted --
|
||||
* ALU ops can only write to a single channel (exception: <32 in which
|
||||
* you can write to 32/N contiguous aligned channels). Load/store can
|
||||
* only write to all channels at once, in a sense. But it's still
|
||||
* better to use this generic form than have synthetic ops flying
|
||||
* about, since we're not essentially vector for RA purposes. */
|
||||
uint16_t writemask;
|
||||
|
||||
/* Destination type. Usually the type of the instruction
|
||||
* itself, but if sources and destination have different
|
||||
* types, the type of the destination wins (so f2i would be
|
||||
|
|
@ -269,6 +264,9 @@ typedef struct {
|
|||
* selection, so we don't have to special case extraction. */
|
||||
uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
|
||||
|
||||
/* For VECTOR ops, how many channels are written? */
|
||||
unsigned vector_channels;
|
||||
|
||||
/* A class-specific op from which the actual opcode can be derived
|
||||
* (along with the above information) */
|
||||
|
||||
|
|
@ -299,9 +297,6 @@ typedef struct {
|
|||
|
||||
/* For BLEND -- the location 0-7 */
|
||||
unsigned blend_location;
|
||||
|
||||
/* For STORE, STORE_VAR -- channel count */
|
||||
unsigned store_channels;
|
||||
};
|
||||
} bi_instruction;
|
||||
|
||||
|
|
@ -578,11 +573,11 @@ bool bi_has_source_mods(bi_instruction *ins);
|
|||
bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
|
||||
bool bi_has_arg(bi_instruction *ins, unsigned arg);
|
||||
uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
|
||||
unsigned bi_get_component_count(bi_instruction *ins, unsigned s);
|
||||
unsigned bi_load32_components(bi_instruction *ins);
|
||||
unsigned bi_get_component_count(bi_instruction *ins, signed s);
|
||||
uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
|
||||
uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
|
||||
bool bi_writes_component(bi_instruction *ins, unsigned comp);
|
||||
unsigned bi_writemask(bi_instruction *ins);
|
||||
|
||||
/* BIR passes */
|
||||
|
||||
|
|
|
|||
|
|
@ -56,12 +56,12 @@ bit_test_single(struct panfrost_device *dev,
|
|||
},
|
||||
.dest = BIR_INDEX_REGISTER | 0,
|
||||
.dest_type = nir_type_uint32,
|
||||
.writemask = 0xFFFF
|
||||
.vector_channels = 4,
|
||||
};
|
||||
|
||||
bi_instruction ldva = {
|
||||
.type = BI_LOAD_VAR_ADDRESS,
|
||||
.writemask = (1 << 12) - 1,
|
||||
.vector_channels = 3,
|
||||
.dest = BIR_INDEX_REGISTER | 32,
|
||||
.dest_type = nir_type_uint32,
|
||||
.src = {
|
||||
|
|
@ -88,7 +88,7 @@ bit_test_single(struct panfrost_device *dev,
|
|||
nir_type_uint32,
|
||||
nir_type_uint32, nir_type_uint32, nir_type_uint32,
|
||||
},
|
||||
.store_channels = 4
|
||||
.vector_channels = 4
|
||||
};
|
||||
|
||||
bi_context *ctx = rzalloc(NULL, bi_context);
|
||||
|
|
@ -382,7 +382,6 @@ bit_convert_helper(struct panfrost_device *dev, unsigned from_size,
|
|||
bi_instruction ins = {
|
||||
.type = BI_CONVERT,
|
||||
.dest = BIR_INDEX_REGISTER | 0,
|
||||
.writemask = 0xF,
|
||||
.src = { BIR_INDEX_REGISTER | 0 }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue