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nvfx: improve and correct nvfx_shader.h
This commit is contained in:
Luca Barbieri
parent
928cce672a
commit
b2bad53478
1 changed files with 65 additions and 13 deletions
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@ -1,6 +1,8 @@
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#ifndef __NVFX_SHADER_H__
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#define __NVFX_SHADER_H__
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#define NVFX_SWZ_IDENTITY ((3 << 6) | (2 << 4) | (1 << 2) | (0 << 0))
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/* this will resolve to either the NV30 or the NV40 version
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* depending on the current hardware */
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/* unusual, but very fast and compact method */
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@ -71,11 +73,58 @@
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/*
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* Each fragment program opcode appears to be comprised of 4 32-bit values.
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*
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* 0 - Opcode, output reg/mask, ATTRIB source
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* 1 - Source 0
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* 2 - Source 1
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* 3 - Source 2
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* 0: OPDEST
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* 0: program end
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* 1-6: destination register
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* 7: destination register is fp16?? (use for outputs)
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* 8: set condition code
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* 9: writemask x
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* 10: writemask y
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* 11: writemask z
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* 12: writemask w
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* 13-16: source attribute register number (e.g. COL0)
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* 17-20: texture unit number
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* 21: expand value on texture operation (x -> 2x - 1)
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* 22-23: precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = s0.8 fixed (nv40-only))
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* 24-29: opcode
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* 30: no destination
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* 31: saturate
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* 1 - SRC0
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* 0-17: see common source fields
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* 18: execute if condition code less
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* 19: execute if condition code equal
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* 20: execute if condition code greater
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* 21-22: condition code swizzle x source component
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* 23-24: condition code swizzle y source component
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* 25-26: condition code swizzle z source component
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* 27-28: condition code swizzle w source component
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* 29: source 0 absolute
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* 30: always 0 in renouveau tests
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* 31: always 0 in renouveau tests
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* 2 - SRC1
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* 0-17: see common source fields
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* 18: source 1 absolute
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* 19-20: input precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = ???
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* 21-27: always 0 in renouveau tests
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* 28-30: scale (0 = 1x, 1 = 2x, 2 = 4x, 3 = 8x, 4 = ???, 5, = 1/2, 6 = 1/4, 7 = 1/8)
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* 31: opcode is branch
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* 3 - SRC2
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* 0-17: see common source fields
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* 18: source 2 absolute
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* 19-29: address register displacement
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* 30: use index register
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* 31: disable perspective-correct interpolation?
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*
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* Common fields of 0, 1, 2 - SRC
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* 0-1: source register type (0 = temp, 1 = input, 2 = immediate, 3 = ???)
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* 2-7: source temp register index
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* 8: source register is fp16??
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* 9-10: source swizzle x source component
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* 11-12: source swizzle y source component
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* 13-14: source swizzle z source component
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* 15-16: source swizzle w source component
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* 17: negate
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* There appears to be no special difference between result regs and temp regs.
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* result.color == R0.xyzw
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* result.depth == R1.z
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@ -210,6 +259,7 @@
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/* NV40 only fragment program opcodes */
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#define NVFX_FP_OP_OPCODE_TXL_NV40 0x2F
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/* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
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#define NV40_FP_OP_BRA_OPCODE_BRK 0x0
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#define NV40_FP_OP_BRA_OPCODE_CAL 0x1
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@ -218,10 +268,11 @@
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#define NV40_FP_OP_BRA_OPCODE_REP 0x4
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#define NV40_FP_OP_BRA_OPCODE_RET 0x5
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#define NV40_FP_OP_OUT_NONE (1 << 30)
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#define NVFX_FP_OP_OUT_SAT (1 << 31)
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/* high order bits of SRC0 */
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#define NVFX_FP_OP_OUT_ABS (1 << 29)
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#define NVFX_FP_OP_SRC0_ABS (1 << 29)
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#define NVFX_FP_OP_COND_SWZ_W_SHIFT 27
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#define NVFX_FP_OP_COND_SWZ_W_MASK (3 << 27)
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#define NVFX_FP_OP_COND_SWZ_Z_SHIFT 25
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@ -254,6 +305,7 @@
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#define NVFX_FP_OP_DST_SCALE_INV_2X 5
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#define NVFX_FP_OP_DST_SCALE_INV_4X 6
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#define NVFX_FP_OP_DST_SCALE_INV_8X 7
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#define NVFX_FP_OP_SRC1_ABS (1 << 18)
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/* SRC1 LOOP */
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#define NV40_FP_OP_LOOP_INCR_SHIFT 19
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@ -263,13 +315,13 @@
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#define NV40_FP_OP_LOOP_COUNT_SHIFT 2
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#define NV40_FP_OP_LOOP_COUNT_MASK (0xFF << 2)
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/* SRC1 IF */
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#define NV40_FP_OP_ELSE_ID_SHIFT 2
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#define NV40_FP_OP_ELSE_ID_MASK (0xFF << 2)
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/* SRC1 IF: absolute offset in dwords */
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#define NV40_FP_OP_ELSE_OFFSET_SHIFT 0
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#define NV40_FP_OP_ELSE_OFFSET_MASK (0x7FFFFFFF << 0)
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/* SRC1 CAL */
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#define NV40_FP_OP_IADDR_SHIFT 2
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#define NV40_FP_OP_IADDR_MASK (0xFF << 2)
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#define NV40_FP_OP_SUB_OFFSET_SHIFT 0
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#define NV40_FP_OP_SUB_OFFSET_MASK (0x7FFFFFFF << 0)
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/* SRC1 REP
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* I have no idea why there are 3 count values here.. but they
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@ -283,9 +335,9 @@
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#define NV40_FP_OP_REP_COUNT3_SHIFT 19
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#define NV40_FP_OP_REP_COUNT3_MASK (0xFF << 19)
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/* SRC2 REP/IF */
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#define NV40_FP_OP_END_ID_SHIFT 2
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#define NV40_FP_OP_END_ID_MASK (0xFF << 2)
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/* SRC2 REP/IF: absolute offset in dwords */
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#define NV40_FP_OP_END_OFFSET_SHIFT 0
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#define NV40_FP_OP_END_OFFSET_MASK (0x7FFFFFFF << 0)
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/* high order bits of SRC2 */
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#define NVFX_FP_OP_INDEX_INPUT (1 << 30)
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