diff --git a/.pick_status.json b/.pick_status.json
index eb9cf71ec7f..a0d887f3ca5 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1394,7 +1394,7 @@
         "description": "radv: fix flushing DB meta cache on GFX11.5",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c
index 61412ed4db6..4e33c3aa410 100644
--- a/src/amd/vulkan/radv_cs.c
+++ b/src/amd/vulkan/radv_cs.c
@@ -186,8 +186,9 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level
          *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB;
       }
 
+      /* GFX11 can't flush DB_META and should use a TS event instead. */
       /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
-      if (gfx_level < GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
+      if (gfx_level != GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
          /* Flush HTILE. Will wait for idle later. */
          radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
          radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));