diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 68cf39629f1..e03c401400a 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -90,7 +90,7 @@ mesa_shader_stage_is_compute(mesa_shader_stage stage)
 }
 
 static inline bool
-gl_shader_stage_is_mesh(mesa_shader_stage stage)
+mesa_shader_stage_is_mesh(mesa_shader_stage stage)
 {
    return stage == MESA_SHADER_TASK ||
           stage == MESA_SHADER_MESH;
diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi_info.c b/src/gallium/auxiliary/nir/nir_to_tgsi_info.c
index 4aae1216b0a..6addb1814b8 100644
--- a/src/gallium/auxiliary/nir/nir_to_tgsi_info.c
+++ b/src/gallium/auxiliary/nir/nir_to_tgsi_info.c
@@ -321,7 +321,7 @@ void nir_tgsi_scan_shader(const struct nir_shader *nir,
    }
 
    if (mesa_shader_stage_is_compute(nir->info.stage) ||
-       gl_shader_stage_is_mesh(nir->info.stage)) {
+       mesa_shader_stage_is_mesh(nir->info.stage)) {
       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.workgroup_size[0];
       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.workgroup_size[1];
       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.workgroup_size[2];
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 90139ee12b7..4f8f312d957 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -171,7 +171,7 @@ brw_shader_stage_is_bindless(mesa_shader_stage stage)
 static inline bool
 brw_shader_stage_requires_bindless_resources(mesa_shader_stage stage)
 {
-   return brw_shader_stage_is_bindless(stage) || gl_shader_stage_is_mesh(stage);
+   return brw_shader_stage_is_bindless(stage) || mesa_shader_stage_is_mesh(stage);
 }
 
 static inline bool
diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp
index 1f29e1a6366..cf8cc102755 100644
--- a/src/intel/compiler/brw_from_nir.cpp
+++ b/src/intel/compiler/brw_from_nir.cpp
@@ -218,7 +218,7 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block)
          /* For Task/Mesh, draw_id will be handled later in
           * nir_emit_mesh_task_intrinsic().
           */
-         if (!gl_shader_stage_is_mesh(s.stage))
+         if (!mesa_shader_stage_is_mesh(s.stage))
             UNREACHABLE("should be lowered by brw_nir_lower_vs_inputs().");
          break;
 
@@ -255,7 +255,7 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block)
          break;
 
       case nir_intrinsic_load_workgroup_id:
-         if (gl_shader_stage_is_mesh(s.stage))
+         if (mesa_shader_stage_is_mesh(s.stage))
             UNREACHABLE("should be lowered by nir_lower_compute_system_values().");
          assert(mesa_shader_stage_is_compute(s.stage));
          reg = &ntb.system_values[SYSTEM_VALUE_WORKGROUP_ID];
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 9c8d6b6affd..0268dc1b432 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -660,7 +660,7 @@ brw_shader::assign_curb_setup()
    const bool pull_constants =
       devinfo->verx10 >= 125 &&
       (mesa_shader_stage_is_compute(stage) ||
-       gl_shader_stage_is_mesh(stage)) &&
+       mesa_shader_stage_is_mesh(stage)) &&
       uniform_push_length;
 
    if (pull_constants) {
@@ -668,7 +668,7 @@ brw_shader::assign_curb_setup()
          (gl_shader_stage_is_rt(stage) &&
           brw_bs_prog_data(prog_data)->uses_inline_push_addr) ||
          ((mesa_shader_stage_is_compute(stage) ||
-           gl_shader_stage_is_mesh(stage)) &&
+           mesa_shader_stage_is_mesh(stage)) &&
           brw_cs_prog_data(prog_data)->uses_inline_push_addr);
       assert(devinfo->has_lsc);
       brw_builder ubld = brw_builder(this, 1).exec_all().at_start(cfg->first_block());
diff --git a/src/intel/vulkan/anv_internal_kernels.c b/src/intel/vulkan/anv_internal_kernels.c
index 4c123a3f8f7..bef4631c290 100644
--- a/src/intel/vulkan/anv_internal_kernels.c
+++ b/src/intel/vulkan/anv_internal_kernels.c
@@ -104,7 +104,7 @@ compile_shader(struct anv_device *device,
       nir_lower_compute_system_values_options options = {
          .has_base_workgroup_id = true,
          .lower_cs_local_id_to_index = true,
-         .lower_workgroup_id_to_index = gl_shader_stage_is_mesh(stage),
+         .lower_workgroup_id_to_index = mesa_shader_stage_is_mesh(stage),
       };
       NIR_PASS(_, nir, nir_lower_compute_system_values, &options);
       NIR_PASS(_, nir, nir_shader_intrinsics_pass, lower_base_workgroup_id,
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 52472568cd6..e5895c4a059 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -2051,7 +2051,7 @@ lower_num_workgroups(nir_builder *b, nir_intrinsic_instr *intrin,
                      struct apply_pipeline_layout_state *state)
 {
    /* For those stages, HW will generate values through payload registers. */
-   if (gl_shader_stage_is_mesh(b->shader->info.stage))
+   if (mesa_shader_stage_is_mesh(b->shader->info.stage))
       return false;
 
    b->cursor = nir_instr_remove(&intrin->instr);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 98576e46358..d3c7868e204 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -980,7 +980,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
                });
    }
 
-   if (gl_shader_stage_is_mesh(nir->info.stage)) {
+   if (mesa_shader_stage_is_mesh(nir->info.stage)) {
       nir_lower_compute_system_values_options options = {
             .lower_workgroup_id_to_index = true,
             /* nir_lower_idiv generates expensive code */
@@ -1160,7 +1160,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
    }
 
    if (mesa_shader_stage_is_compute(nir->info.stage) ||
-       gl_shader_stage_is_mesh(nir->info.stage)) {
+       mesa_shader_stage_is_mesh(nir->info.stage)) {
       NIR_PASS(_, nir, brw_nir_lower_cs_intrinsics, compiler->devinfo,
                &stage->prog_data.cs);
    }