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radeon/vcn: handle tiled buffers when decoding

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Set the swizzle mode when decoding.

Add a safe-guard to make sure the provided surface isn't DCC, because
we don't handle this situation.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
This commit is contained in:
Simon Ser 2021-04-09 10:18:44 +02:00 • committed by Marge Bot
parent 029bc53be6
commit b26a546b2f
1 changed files with 6 additions and 1 deletions
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7
src/gallium/drivers/radeon/radeon_vcn_dec.c
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@ -1651,8 +1651,13 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
decode->dt_uv_pitch = decode->dt_pitch / 2;
if (luma->surface.meta_offset) {
RVID_ERR("DCC surfaces not supported.\n");
return NULL;
}
decode->dt_tiling_mode = 0;
decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR;
decode->dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode;
decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
decode->dt_surf_tile_config = 0;