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ac/nir: move all RADV related code to radv_nir_to_llvm.c

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Now the "ac/nir" prefix will really be the shared code between
RadeonSI and RADV, that might avoid confusions in the future.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2018-03-09 16:58:10 +01:00
parent 8e15824b9d
commit b2653007b9
7 changed files with 3482 additions and 3425 deletions
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3403
src/amd/common/ac_nir_to_llvm.c
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File diff suppressed because it is too large Load diff

17
src/amd/common/ac_nir_to_llvm.h
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@ -219,23 +219,6 @@ static inline unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
return (index * 4) + chan;
}
void ac_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct ac_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
const struct ac_nir_compiler_options *options,
bool dump_shader);
void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
struct nir_shader *geom_shader,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct ac_shader_variant_info *shader_info,
const struct ac_nir_compiler_options *options,
bool dump_shader);
void ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class);
void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,

1
src/amd/vulkan/Makefile.sources
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@ -53,6 +53,7 @@ VULKAN_FILES := \
radv_meta_resolve.c \
radv_meta_resolve_cs.c \
radv_meta_resolve_fs.c \
radv_nir_to_llvm.c \
radv_pass.c \
radv_pipeline.c \
radv_pipeline_cache.c \

1
src/amd/vulkan/meson.build
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@ -80,6 +80,7 @@ libradv_files = files(
'radv_meta_resolve.c',
'radv_meta_resolve_cs.c',
'radv_meta_resolve_fs.c',
'radv_nir_to_llvm.c',
'radv_pass.c',
'radv_pipeline.c',
'radv_pipeline_cache.c',

3456
src/amd/vulkan/radv_nir_to_llvm.c Normal file
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File diff suppressed because it is too large Load diff

18
src/amd/vulkan/radv_private.h
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@ -1677,6 +1677,24 @@ struct radv_fence {
uint32_t temp_syncobj;
};
/* radv_nir_to_llvm.c */
void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
struct nir_shader *geom_shader,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct ac_shader_variant_info *shader_info,
const struct ac_nir_compiler_options *options,
bool dump_shader);
void radv_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct ac_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
const struct ac_nir_compiler_options *options,
bool dump_shader);
struct radeon_winsys_sem;
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \

11
src/amd/vulkan/radv_shader.c
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@ -473,12 +473,13 @@ shader_variant_create(struct radv_device *device,
if (gs_copy_shader) {
assert(shader_count == 1);
ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
&variant->info, options, dump_shaders);
radv_compile_gs_copy_shader(tm, *shaders, &binary,
&variant->config, &variant->info,
options, dump_shaders);
} else {
ac_compile_nir_shader(tm, &binary, &variant->config,
&variant->info, shaders, shader_count, options,
dump_shaders);
radv_compile_nir_shader(tm, &binary, &variant->config,
&variant->info, shaders, shader_count,
options, dump_shaders);
}
LLVMDisposeTargetMachine(tm);